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White Rabbit Switch - Gateware
Commits
318021ef
Commit
318021ef
authored
Dec 05, 2010
by
Maciej Lipinski
Browse files
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Plain Diff
swcore: removing synthesis warnings, cleaning
parent
55d9f347
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Showing
14 changed files
with
61 additions
and
222 deletions
+61
-222
swc_input_block.vhd
swc_input_block.vhd
+1
-8
swc_multiport_page_allocator.vhd
swc_multiport_page_allocator.vhd
+6
-6
swc_ob_prio_queue.vhd
swc_ob_prio_queue.vhd
+1
-3
swc_onehot_decoder.vhd
swc_onehot_decoder.vhd
+0
-153
swc_output_block.vhd
swc_output_block.vhd
+2
-2
swc_packet_mem.vhd
swc_packet_mem.vhd
+1
-1
swc_packet_mem_read_pump.vhd
swc_packet_mem_read_pump.vhd
+3
-3
swc_packet_mem_write_pump.vhd
swc_packet_mem_write_pump.vhd
+25
-25
swc_page_alloc.vhd
swc_page_alloc.vhd
+14
-14
swc_pck_transfer_arbiter.vhd
swc_pck_transfer_arbiter.vhd
+2
-1
swc_pck_transfer_input.vhd
swc_pck_transfer_input.vhd
+3
-3
swc_prio_encoder.vhd
swc_prio_encoder.vhd
+1
-1
swc_rr_arbiter.vhd
swc_rr_arbiter.vhd
+1
-1
swc_swcore_pkg.vhd
swc_swcore_pkg.vhd
+1
-1
No files found.
swc_input_block.vhd
View file @
318021ef
...
...
@@ -209,7 +209,7 @@ signal pta_pageaddr : std_logic_vector(c_swc_page_addr_width - 1 downto 0);
signal
pta_mask
:
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
signal
pta_prio
:
std_logic_vector
(
c_swc_prio_width
-
1
downto
0
);
signal
pta_pck_size
:
std_logic_vector
(
c_swc_max_pck_size_width
-
1
downto
0
);
signal
transfering_pck_on_wait
:
std_logic
;
signal
write_ctrl_in
:
std_logic_vector
(
1
downto
0
);
...
...
@@ -224,7 +224,6 @@ signal read_prio : std_logic_vector(c_swc_prio_width - 1 downto 0);
signal
read_usecnt
:
std_logic_vector
(
c_swc_usecount_width
-
1
downto
0
);
signal
write_mask
:
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
signal
write_pck_size
:
std_logic_vector
(
c_swc_max_pck_size_width
-
1
downto
0
);
signal
write_prio
:
std_logic_vector
(
c_swc_prio_width
-
1
downto
0
);
signal
write_usecnt
:
std_logic_vector
(
c_swc_usecount_width
-
1
downto
0
);
...
...
@@ -321,8 +320,6 @@ type t_read_state is (S_IDLE, -- we wait for other processes (
signal
mpm_pckstart
:
std_logic
;
signal
mpm_pageaddr
:
std_logic_vector
(
c_swc_page_addr_width
-
1
downto
0
);
signal
mpm_pagereq
:
std_logic
;
signal
mpm_data
:
std_logic_vector
(
c_swc_data_width
-
1
downto
0
);
signal
mpm_ctrl
:
std_logic_vector
(
c_swc_ctrl_width
-
1
downto
0
);
signal
flush_sig
:
std_logic
;
signal
flush_reg
:
std_logic
;
...
...
@@ -787,15 +784,12 @@ begin --arch
current_pckstart_pageaddr
<=
(
others
=>
'1'
);
write_mask
<=
(
others
=>
'0'
);
write_pck_size
<=
(
others
=>
'0'
);
write_prio
<=
(
others
=>
'0'
);
write_usecnt
<=
(
others
=>
'0'
);
mpm_pckstart
<=
'0'
;
mpm_pageaddr
<=
(
others
=>
'1'
);
mpm_pagereq
<=
'0'
;
mpm_data
<=
(
others
=>
'0'
);
mpm_ctrl
<=
(
others
=>
'0'
);
flush_reg
<=
'0'
;
mmu_force_free_addr
<=
(
others
=>
'0'
);
...
...
@@ -1258,7 +1252,6 @@ end process;
pta_mask
<=
(
others
=>
'0'
);
pta_prio
<=
(
others
=>
'0'
);
pta_pck_size
<=
(
others
=>
'0'
);
transfering_pck_on_wait
<=
'0'
;
--===================================================
else
...
...
swc_multiport_page_allocator.vhd
View file @
318021ef
...
...
@@ -13,7 +13,7 @@
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 Tomasz Wlostowski / CERN
-- Copyright (c) 2010 Tomasz Wlostowski
, Maciej Lipinski
/ CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
@@ -88,8 +88,8 @@ architecture syn of swc_multiport_page_allocator is
signal
pg_addr_usecnt
:
std_logic_vector
(
c_swc_page_addr_width
-1
downto
0
);
signal
pg_addr
:
std_logic_vector
(
c_swc_page_addr_width
-1
downto
0
);
signal
pg_addr_valid
:
std_logic
;
signal
pg_idle
:
std_logic
;
signal
pg_addr_valid
:
std_logic
;
-- used by symulation , don't remove
--
signal pg_idle : std_logic;
signal
pg_done
:
std_logic
;
signal
pg_nomem
:
std_logic
;
...
...
@@ -146,7 +146,7 @@ architecture syn of swc_multiport_page_allocator is
signal
set_usecnt_done_feedback
:
std_logic_vector
(
c_swc_num_ports
-1
downto
0
);
signal
set_usecnt_done
:
std_logic_vector
(
c_swc_num_ports
-1
downto
0
);
--
signal set_usecnt_done : std_logic_vector(c_swc_num_ports-1 downto 0);
begin
-- syn
...
...
@@ -171,7 +171,7 @@ begin -- syn
pgaddr_i
=>
pg_addr
,
--pg_addr_free,
pgaddr_o
=>
pg_addr_alloc
,
pgaddr_valid_o
=>
pg_addr_valid
,
idle_o
=>
pg_idle
,
idle_o
=>
open
,
--
pg_idle,
done_o
=>
pg_done
,
nomem_o
=>
pg_nomem
);
...
...
@@ -285,7 +285,7 @@ begin -- syn
alloc_done
<=
alloc_done_feedback
;
free_done
<=
free_done_feedback
;
set_usecnt_done
<=
set_usecnt_done_feedback
;
--
set_usecnt_done <= set_usecnt_done_feedback;
force_free_done
<=
force_free_done_feedback
;
end
if
;
end
if
;
...
...
swc_ob_prio_queue.vhd
View file @
318021ef
...
...
@@ -80,7 +80,6 @@ architecture behavoural of swc_ob_prio_queue is
signal
tail
:
std_logic_vector
(
c_swc_output_fifo_addr_width
-
1
downto
0
);
signal
not_full
:
std_logic
;
signal
not_empty
:
std_logic
;
signal
read
:
std_logic
;
begin
-- behavoural
...
...
@@ -92,8 +91,7 @@ begin -- behavoural
head
<=
(
others
=>
'0'
);
tail
<=
(
others
=>
'0'
);
read
<=
'0'
;
else
if
(
write_i
=
'1'
and
not_full
=
'1'
)
then
...
...
swc_onehot_decoder.vhd
deleted
100644 → 0
View file @
55d9f347
-------------------------------------------------------------------------------
-- Title : Onehot decoder
-- Project : WhiteRabbit switch
-------------------------------------------------------------------------------
-- File : swc_onehot_decoder.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-08
-- Last update: 2010-04-08
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 Tomasz Wlostowski / CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-04-08 1.0 twlostow Created
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
entity
swc_prio_encoder
is
generic
(
g_num_inputs
:
integer
range
2
to
64
:
=
32
;
g_output_bits
:
integer
range
1
to
6
:
=
5
);
port
(
in_i
:
in
std_logic_vector
(
g_num_inputs
-1
downto
0
);
out_o
:
out
std_logic_vector
(
g_output_bits
-1
downto
0
);
mask_o
:
out
std_logic_vector
(
g_num_inputs
-1
downto
0
);
zero_o
:
out
std_logic
);
end
swc_prio_encoder
;
architecture
syn
of
swc_prio_encoder
is
signal
w
:
std_logic_vector
(
63
downto
0
);
signal
q
:
std_logic_vector
(
5
downto
0
);
begin
-- syn
w
(
63
downto
g_num_inputs
)
<=
(
others
=>
'0'
);
w
(
g_num_inputs
-1
downto
0
)
<=
in_i
;
q
<=
"000000"
when
w
(
0
)
=
'1'
else
"000001"
when
w
(
1
)
=
'1'
else
"000010"
when
w
(
2
)
=
'1'
else
"000011"
when
w
(
3
)
=
'1'
else
"000100"
when
w
(
4
)
=
'1'
else
"000101"
when
w
(
5
)
=
'1'
else
"000110"
when
w
(
6
)
=
'1'
else
"000111"
when
w
(
7
)
=
'1'
else
"001000"
when
w
(
8
+
0
)
=
'1'
else
"001001"
when
w
(
8
+
1
)
=
'1'
else
"001010"
when
w
(
8
+
2
)
=
'1'
else
"001011"
when
w
(
8
+
3
)
=
'1'
else
"001100"
when
w
(
8
+
4
)
=
'1'
else
"001101"
when
w
(
8
+
5
)
=
'1'
else
"001110"
when
w
(
8
+
6
)
=
'1'
else
"001111"
when
w
(
8
+
7
)
=
'1'
else
"010000"
when
w
(
16
+
0
)
=
'1'
else
"010001"
when
w
(
16
+
1
)
=
'1'
else
"010010"
when
w
(
16
+
2
)
=
'1'
else
"010011"
when
w
(
16
+
3
)
=
'1'
else
"010100"
when
w
(
16
+
4
)
=
'1'
else
"010101"
when
w
(
16
+
5
)
=
'1'
else
"010110"
when
w
(
16
+
6
)
=
'1'
else
"010111"
when
w
(
16
+
7
)
=
'1'
else
"011000"
when
w
(
24
+
0
)
=
'1'
else
"011001"
when
w
(
24
+
1
)
=
'1'
else
"011010"
when
w
(
24
+
2
)
=
'1'
else
"011011"
when
w
(
24
+
3
)
=
'1'
else
"011100"
when
w
(
24
+
4
)
=
'1'
else
"011101"
when
w
(
24
+
5
)
=
'1'
else
"011110"
when
w
(
24
+
6
)
=
'1'
else
"011111"
when
w
(
24
+
7
)
=
'1'
else
"100000"
when
w
(
32
+
0
)
=
'1'
else
"100001"
when
w
(
32
+
1
)
=
'1'
else
"100010"
when
w
(
32
+
2
)
=
'1'
else
"100011"
when
w
(
32
+
3
)
=
'1'
else
"100100"
when
w
(
32
+
4
)
=
'1'
else
"100101"
when
w
(
32
+
5
)
=
'1'
else
"100110"
when
w
(
32
+
6
)
=
'1'
else
"100111"
when
w
(
32
+
7
)
=
'1'
else
"101000"
when
w
(
32
+
8
+
0
)
=
'1'
else
"101001"
when
w
(
32
+
8
+
1
)
=
'1'
else
"101010"
when
w
(
32
+
8
+
2
)
=
'1'
else
"101011"
when
w
(
32
+
8
+
3
)
=
'1'
else
"101100"
when
w
(
32
+
8
+
4
)
=
'1'
else
"101101"
when
w
(
32
+
8
+
5
)
=
'1'
else
"101110"
when
w
(
32
+
8
+
6
)
=
'1'
else
"101111"
when
w
(
32
+
8
+
7
)
=
'1'
else
"110000"
when
w
(
32
+
16
+
0
)
=
'1'
else
"110001"
when
w
(
32
+
16
+
1
)
=
'1'
else
"110010"
when
w
(
32
+
16
+
2
)
=
'1'
else
"110011"
when
w
(
32
+
16
+
3
)
=
'1'
else
"110100"
when
w
(
32
+
16
+
4
)
=
'1'
else
"110101"
when
w
(
32
+
16
+
5
)
=
'1'
else
"110110"
when
w
(
32
+
16
+
6
)
=
'1'
else
"110111"
when
w
(
32
+
16
+
7
)
=
'1'
else
"111000"
when
w
(
32
+
24
+
0
)
=
'1'
else
"111001"
when
w
(
32
+
24
+
1
)
=
'1'
else
"111010"
when
w
(
32
+
24
+
2
)
=
'1'
else
"111011"
when
w
(
32
+
24
+
3
)
=
'1'
else
"111100"
when
w
(
32
+
24
+
4
)
=
'1'
else
"111101"
when
w
(
32
+
24
+
5
)
=
'1'
else
"111110"
when
w
(
32
+
24
+
6
)
=
'1'
else
"111111"
when
w
(
32
+
24
+
7
)
=
'1'
else
"XXXXXX"
;
out_o
<=
q
(
g_output_bits
-1
downto
0
);
zero_o
<=
'1'
when
(
in_i
=
std_logic_vector
(
to_unsigned
(
0
,
g_num_inputs
)))
else
'0'
;
mask_o
(
0
)
<=
w
(
0
);
genmask
:
for
i
in
1
to
g_num_inputs
-1
generate
mask_o
(
i
)
<=
'1'
when
(
w
(
i
)
=
'1'
and
w
(
i
-1
downto
0
)
=
std_logic_vector
(
to_unsigned
(
0
,
i
)))
else
'0'
;
end
generate
genmask
;
end
syn
;
swc_output_block.vhd
View file @
318021ef
...
...
@@ -135,7 +135,7 @@ architecture behavoural of swc_output_block is
signal
read
:
std_logic_vector
(
c_swc_output_prio_num
-
1
downto
0
);
signal
write_array
:
std_logic_vector
(
c_swc_output_prio_num
-
1
downto
0
);
signal
write
:
std_logic_vector
(
c_swc_output_prio_num
-
1
downto
0
);
signal
wr_en_array
:
std_logic_vector
(
c_swc_output_prio_num
-
1
downto
0
);
--
signal wr_en_array : std_logic_vector(c_swc_output_prio_num - 1 downto 0);
signal
wr_en
:
std_logic
;
signal
rd_data_valid
:
std_logic
;
signal
zeros
:
std_logic_vector
(
c_swc_output_prio_num
-
1
downto
0
);
...
...
@@ -266,7 +266,7 @@ begin -- behavoural
read_i
=>
read
(
i
),
not_full_o
=>
not_full_array
(
i
),
not_empty_o
=>
not_empty_array
(
i
),
wr_en_o
=>
wr_en_array
(
i
),
wr_en_o
=>
open
,
--
wr_en_array(i),
wr_addr_o
=>
wr_array
(
i
),
rd_addr_o
=>
rd_array
(
i
)
);
...
...
swc_packet_mem.vhd
View file @
318021ef
...
...
@@ -50,7 +50,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 Tomasz Wlostowski / CERN
-- Copyright (c) 2010 Tomasz Wlostowski
, Maciej Lipinski
/ CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
swc_packet_mem_read_pump.vhd
View file @
318021ef
...
...
@@ -30,7 +30,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 Tomasz Wlostowski / CERN
-- Copyright (c) 2010 Tomasz Wlostowski
, Maciej Lipinski
/ CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
@@ -173,7 +173,7 @@ architecture syn of swc_packet_mem_read_pump is
signal
load_out_reg
:
std_logic
;
-- seems not used ....
signal
nothing_read
:
std_logic
;
--
signal nothing_read : std_logic;
-- HI indicates that current page is done, and that the parent entity must
-- select another page in following clock cycles (c_swc_packet_mem_multiply
...
...
@@ -236,7 +236,7 @@ begin -- syn
reg_not_empty
<=
'0'
;
mem_addr
<=
(
others
=>
'0'
);
advance_addr
<=
'0'
;
nothing_read
<=
'0'
;
--
nothing_read <= '0';
pgend
<=
'0'
;
pckend
<=
'0'
;
current_page_addr
<=
(
others
=>
'0'
);
...
...
swc_packet_mem_write_pump.vhd
View file @
318021ef
...
...
@@ -41,7 +41,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 Tomasz Wlostowski / CERN
-- Copyright (c) 2010 Tomasz Wlostowski
, Maciej Lipinski
/ CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
@@ -75,11 +75,11 @@ use ieee.numeric_std.all;
use
ieee
.
math_real
.
log2
;
use
ieee
.
math_real
.
ceil
;
use
std
.
textio
.
all
;
--
use std.textio.all;
library
work
;
use
work
.
swc_swcore_pkg
.
all
;
use
work
.
pck_fio
.
all
;
--
use work.pck_fio.all;
entity
swc_packet_mem_write_pump
is
...
...
@@ -208,7 +208,7 @@ architecture rtl of swc_packet_mem_write_pump is
-- we all love VHDL :)
signal
allones
:
std_logic_vector
(
63
downto
0
);
signal
zeros
:
std_logic_vector
(
63
downto
0
);
--
signal zeros : std_logic_vector(63 downto 0);
-- HI indicates that current page is done, and that the parent entity must
-- select another page in following clock cycles (c_swc_packet_mem_multiply
...
...
@@ -218,7 +218,7 @@ architecture rtl of swc_packet_mem_write_pump is
-- start of package
signal
pckstart
:
std_logic
;
signal
before_sync
:
std_logic
;
--
signal before_sync : std_logic;
--=================================================================================
...
...
@@ -256,8 +256,8 @@ architecture rtl of swc_packet_mem_write_pump is
signal
state_write
:
t_state_write
;
signal
cnt_last_word
:
std_logic
;
signal
next_page_loaded
:
std_logic
;
--
signal cnt_last_word : std_logic;
--
signal next_page_loaded : std_logic;
signal
pgreq_reg
:
std_logic
;
signal
pckstart_reg
:
std_logic
;
...
...
@@ -267,7 +267,7 @@ architecture rtl of swc_packet_mem_write_pump is
signal
sync_d
:
std_logic_vector
(
c_swc_packet_mem_multiply
-
1
downto
0
);
signal
nasty_wait_full
:
std_logic
;
--
signal nasty_wait_full : std_logic;
...
...
@@ -275,7 +275,7 @@ begin -- rtl
-- VHDL sucks...
allones
<=
(
others
=>
'1'
);
zeros
<=
(
others
=>
'0'
);
--
zeros <= (others => '0');
write_on_sync
<=
'1'
when
(
cntr
=
to_unsigned
(
0
,
cntr
'length
))
else
'0'
;
...
...
@@ -298,7 +298,7 @@ begin -- rtl
end
process
;
before_sync
<=
sync_d
(
c_swc_packet_mem_multiply
-
2
);
--
before_sync <= sync_d(c_swc_packet_mem_multiply - 2);
write_fsm
:
process
(
clk_i
,
rst_n_i
)
begin
...
...
@@ -307,7 +307,7 @@ begin -- rtl
we_int
<=
'0'
;
reg_full
<=
'0'
;
cnt_last_word
<=
'0'
;
--
cnt_last_word <='0';
else
-- main finite state machine
...
...
@@ -333,7 +333,7 @@ begin -- rtl
elsif
(
cntr
=
to_unsigned
(
c_swc_packet_mem_multiply
-
2
,
cntr
'length
)
and
drdy_i
=
'1'
)
then
state_write
<=
S_READ_LAST_DATA_WORD
;
cnt_last_word
<=
'1'
;
--
cnt_last_word <= '1';
end
if
;
...
...
@@ -347,7 +347,7 @@ begin -- rtl
reg_full
<=
'1'
;
state_write
<=
S_WAIT_WRITE
;
cnt_last_word
<=
'0'
;
--
cnt_last_word <= '0';
-- during the last address of the page, the Linked list is being written, so we need
...
...
@@ -362,14 +362,14 @@ begin -- rtl
state_write
<=
S_WRITE_DATA
;
we_int
<=
'1'
;
reg_full
<=
'0'
;
cnt_last_word
<=
'0'
;
--
cnt_last_word <= '0';
else
state_write
<=
S_NASTY_WAIT
;
we_int
<=
'0'
;
reg_full
<=
'0'
;
cnt_last_word
<=
'0'
;
--
cnt_last_word <= '0';
end
if
;
...
...
@@ -389,7 +389,7 @@ begin -- rtl
--==== needs test - end ===
reg_full
<=
'1'
;
state_write
<=
S_WAIT_WRITE
;
cnt_last_word
<=
'0'
;
--
cnt_last_word <= '0';
--==== needs test - start ===
end
if
;
--==== needs test - end ===
...
...
@@ -410,13 +410,13 @@ begin -- rtl
state_write
<=
S_WRITE_DATA
;
we_int
<=
'1'
;
reg_full
<=
'0'
;
cnt_last_word
<=
'0'
;
--
cnt_last_word <= '0';
elsif
(
drdy_i
=
'1'
and
sync_i
=
'0'
)
then
reg_full
<=
'1'
;
state_write
<=
S_WAIT_WRITE
;
cnt_last_word
<=
'0'
;
--
cnt_last_word <= '0';
end
if
;
...
...
@@ -495,7 +495,7 @@ begin -- rtl
state_write
<=
S_WRITE_DATA
;
we_int
<=
'1'
;
reg_full
<=
'0'
;
cnt_last_word
<=
'0'
;
--
cnt_last_word <= '0';
end
if
;
when
others
=>
...
...
@@ -530,7 +530,7 @@ begin -- rtl
cntr
<=
(
others
=>
'0'
);
mem_addr
<=
(
others
=>
'0'
);
pgend
<=
'0'
;
next_page_loaded
<=
'0'
;
--
next_page_loaded <= '0';
--pckstart <= '0';
for
i
in
0
to
c_swc_packet_mem_multiply
-1
loop
in_reg
(
i
)
<=
(
others
=>
'0'
);
...
...
@@ -573,13 +573,13 @@ begin -- rtl
mem_addr
(
c_swc_packet_mem_addr_width
-1
downto
c_swc_page_offset_width
)
<=
pgaddr_i
;
mem_addr
(
c_swc_page_offset_width
-1
downto
0
)
<=
(
others
=>
'0'
);
-- pgend <= '0';
next_page_loaded
<=
'1'
;
--
next_page_loaded <= '1';
elsif
(
state_write
=
S_WRITE_DATA
)
then
if
(
mem_addr
(
c_swc_page_offset_width
-1
downto
0
)
=
allones
(
c_swc_page_offset_width
-1
downto
0
)
)
then
-- pgend <= '1';
next_page_loaded
<=
'0'
;
--
next_page_loaded <= '0';
else
mem_addr
(
c_swc_page_offset_width
-1
downto
0
)
<=
std_logic_vector
(
unsigned
(
mem_addr
(
c_swc_page_offset_width
-1
downto
0
))
+
1
);
...
...
@@ -676,8 +676,8 @@ begin -- rtl
fsm
:
process
(
clk_i
,
rst_n_i
)
variable
l
:
line
;
file
fout
:
text
open
write_mode
is
"stdout"
;
--
variable l:line;
--
file fout:text open write_mode is "stdout" ;
begin
if
rising_edge
(
clk_i
)
then
if
(
rst_n_i
=
'0'
)
then
...
...
@@ -845,7 +845,7 @@ begin -- rtl
end
process
;
nasty_wait_full
<=
'1'
when
(
state_write
=
S_NASTY_WAIT
)
else
'0'
;
--
nasty_wait_full <= '1' when (state_write = S_NASTY_WAIT) else '0';
ll_idle
<=
'1'
when
(
state
=
IDLE
)
else
'0'
;
...
...
swc_page_alloc.vhd
View file @
318021ef
...
...
@@ -66,7 +66,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 Tomasz Wlostowski / CERN
-- Copyright (c) 2010 Tomasz Wlostowski
, Maciej Lipinski
/ CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
@@ -98,8 +98,8 @@ use ieee.numeric_std.all;
use
work
.
platform_specific
.
all
;
use
work
.
swc_swcore_pkg
.
all
;
use
std
.
textio
.
all
;
use
work
.
pck_fio
.
all
;
--
use std.textio.all;
--
use work.pck_fio.all;
entity
swc_page_allocator
is
generic
(
...
...
@@ -233,10 +233,10 @@ architecture syn of swc_page_allocator is
signal
tmp_page
:
std_logic_vector
(
g_page_addr_bits
-1
downto
0
);
signal
tmp_pgs
:
std_logic_vector
(
1023
downto
0
);
--
signal tmp_pgs : std_logic_vector(1023 downto 0);
signal
tmp_dbg_dealloc
:
std_logic
;
signal
tmp_dbg_alloc
:
std_logic
;
signal
tmp_dbg_dealloc
:
std_logic
;
-- used for symulation debugging, don't remove
--
signal tmp_dbg_alloc : std_logic;
begin
-- syn
...
...
@@ -298,8 +298,8 @@ begin -- syn
fsm
:
process
(
clk_i
,
rst_n_i
)
variable
l
:
line
;
file
fout
:
text
open
write_mode
is
"dupa.txt"
;
--"stdout" ;
--
variable l:line;
--
file fout:text open write_mode is "dupa.txt";--"stdout" ;
variable
cnt
:
integer
:
=
-1
;
variable
usecnt_mem_rdaddr_v
:
integer
:
=
0
;
...
...
@@ -320,8 +320,8 @@ begin -- syn
l0_wr_data
<=
(
others
=>
'0'
);
nomem
<=
'0'
;
tmp_page
<=
(
others
=>
'0'
);
tmp_pgs
<=
(
others
=>
'0'
);
tmp_page
<=
(
others
=>
'0'
);
-- used for symulation debugging, don't remove
--
tmp_pgs <= (others => '0');
-- bugfix by ML (two consecutive page free of the same page addr)
page_freeing_in_last_operation
<=
'0'
;
previously_freed_page
<=
(
others
=>
'0'
);
...
...
@@ -490,7 +490,7 @@ begin -- syn
state
<=
IDLE
;
--if(l1_first_free & l0_first_free = x"0E5")
fprint
(
fout
,
l
,
"==> Allocate page %d , usecnt %d, free blocks: %d \n"
,
fo
(
l1_first_free
&
l0_first_free
),
fo
(
usecnt_i
),
fo
(
free_blocks
-1
));
--
fprint(fout, l, "==> Allocate page %d , usecnt %d, free blocks: %d \n", fo(l1_first_free & l0_first_free),fo(usecnt_i), fo(free_blocks-1));
-- tmp_pgs(to_integer(unsigned(l1_first_free & l0_first_free))) <= '1';
-- done_o <= '0';
...
...
@@ -525,7 +525,7 @@ begin -- syn
state
<=
IDLE
;
done_o
<=
'0'
;
fprint
(
fout
,
l
,
"<== Release page: %d, free blocks: %d \n"
,
fo
(
tmp_page
),
fo
(
free_blocks
+
1
));
--
fprint(fout, l, "<== Release page: %d, free blocks: %d \n",fo(tmp_page),fo(free_blocks+ 1));
--tmp_pgs(to_integer(unsigned(tmp_page))) <= '0';
when
FREE_DECREASE_UCNT
=>
...
...
@@ -533,7 +533,7 @@ begin -- syn
usecnt_mem_wr
<=
'1'
;
state
<=
IDLE
;
fprint
(
fout
,
l
,
" Free page: %d (usecnt = %d)\n"
,
fo
(
tmp_page
),
fo
(
std_logic_vector
(
unsigned
(
usecnt_mem_rddata
)
-
1
)));
--
fprint(fout, l, " Free page: %d (usecnt = %d)\n",fo(tmp_page),fo(std_logic_vector(unsigned(usecnt_mem_rddata) - 1)));
when
SET_UCNT
=>
...
...
@@ -543,7 +543,7 @@ begin -- syn
state
<=
IDLE
;
done_o
<=
'0'
;
fprint
(
fout
,
l
,
" Usecnt set: %d (usecnt = %d)\n"
,
fo
(
tmp_page
),
fo
(
usecnt_i
));
--
fprint(fout, l, " Usecnt set: %d (usecnt = %d)\n",fo(tmp_page),fo(usecnt_i));
when
others
=>
state
<=
IDLE
;
...
...
swc_pck_transfer_arbiter.vhd
View file @
318021ef
...
...
@@ -159,7 +159,8 @@ begin --arch
-- multiplex mask from input to output
multimux_out
:
process
(
sync_cntr
,
pto_output_mask
,
pto_pageaddr
,
pto_prio
)
--multimux_out : process(sync_cntr,pto_output_mask,pto_pageaddr,pto_prio)
multimux_out
:
process
(
sync_cntr
,
pto_output_mask
,
pto_pageaddr
,
pto_prio
,
pto_pck_size
)
begin
for
i
in
0
to
c_swc_num_ports
-
1
loop
...
...
swc_pck_transfer_input.vhd
View file @
318021ef
...
...
@@ -100,7 +100,7 @@ architecture syn of swc_pck_transfer_input is
signal
ib_prio
:
std_logic_vector
(
c_swc_prio_width
-
1
downto
0
);
signal
ib_pck_size
:
std_logic_vector
(
c_swc_max_pck_size_width
-
1
downto
0
);
signal
ib_mask
:
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
signal
pto_read_mask
:
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
--
signal pto_read_mask : std_logic_vector(c_swc_num_ports - 1 downto 0);
signal
pto_output_mask
:
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
signal
zeros
:
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
...
...
@@ -116,7 +116,7 @@ begin --arch
if
(
rst_n_i
=
'0'
)
then
--===================================================
ib_mask
<=
(
others
=>
'0'
);
pto_read_mask
<=
(
others
=>
'0'
);
--
pto_read_mask <= (others => '0');
pto_output_mask
<=
(
others
=>
'0'
);
ib_prio
<=
(
others
=>
'0'
);
ib_pck_size
<=
(
others
=>
'0'
);
...
...
@@ -136,7 +136,7 @@ begin --arch
if
(
ib_transfer_pck_i
=
'1'
and
pto_output_mask
=
zeros
)
then
pto_read_mask
<=
(
others
=>
'0'
);
--
pto_read_mask <= (others => '0');
pto_output_mask
<=
ib_mask_i
;
--(others => '0');
else
...
...
swc_prio_encoder.vhd
View file @
318021ef
...
...
@@ -13,7 +13,7 @@
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 Tomasz Wlostowski / CERN
-- Copyright (c) 2010 Tomasz Wlostowski
, Maciej Lipinski
/ CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
swc_rr_arbiter.vhd
View file @
318021ef
...
...
@@ -13,7 +13,7 @@
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 Tomasz Wlostowski / CERN
-- Copyright (c) 2010 Tomasz Wlostowski
, Maciej Lipinski
/ CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
swc_swcore_pkg.vhd
View file @
318021ef
...
...
@@ -13,7 +13,7 @@
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 Tomasz Wlostowski / CERN
-- Copyright (c) 2010 Tomasz Wlostowski
, Maciej Lipinski
/ CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
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