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Commit 23979725 authored by li hongming's avatar li hongming
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change 8ports to 2ports to reduce compiling time.

parent 95746526
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Showing with 1676 additions and 1102 deletions
wr-cores @ bb0e1b6d
Subproject commit 3c2a6c72fd6e6c1594212b03d75ed2c8863cb8b3
Subproject commit bb0e1b6d5a285547f83b3a9bcd526d5545a52a00
syn/scb_8ports/test_scb.xise
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top/scb_8ports/scb_top_synthesis.ucf
View file @ 23979725
......@@ -131,17 +131,17 @@ NET "clk_sel_o" LOC="AK17";
#NET "gtx4_7_clk_n_i" IOSTANDARD="LVPECL_25";
#NET "gtx4_7_clk_p_i" IOSTANDARD="LVPECL_25";
NET "gtx8_11_clk_n_i" LOC="V5";
NET "gtx8_11_clk_p_i" LOC="V6";
# NET "gtx8_11_clk_n_i" LOC="V5";
# NET "gtx8_11_clk_p_i" LOC="V6";
NET "gtx8_11_clk_n_i" IOSTANDARD="LVPECL_25";
NET "gtx8_11_clk_p_i" IOSTANDARD="LVPECL_25";
# NET "gtx8_11_clk_n_i" IOSTANDARD="LVPECL_25";
# NET "gtx8_11_clk_p_i" IOSTANDARD="LVPECL_25";
NET "gtx12_15_clk_n_i" LOC="P5";
NET "gtx12_15_clk_p_i" LOC="P6";
# NET "gtx12_15_clk_n_i" LOC="P5";
# NET "gtx12_15_clk_p_i" LOC="P6";
NET "gtx12_15_clk_n_i" IOSTANDARD="LVPECL_25";
NET "gtx12_15_clk_p_i" IOSTANDARD="LVPECL_25";
# NET "gtx12_15_clk_n_i" IOSTANDARD="LVPECL_25";
# NET "gtx12_15_clk_p_i" IOSTANDARD="LVPECL_25";
NET "gtx16_19_clk_n_i" LOC="H5";
NET "gtx16_19_clk_p_i" LOC="H6";
......@@ -210,41 +210,41 @@ NET "gtx16_19_clk_p_i" IOSTANDARD="LVPECL_25";
#NET "gtx_txp_o[9]" LOC="V1";
#NET "gtx_txn_o[9]" LOC="V2";
NET "gtx_rxp_i[7]" LOC="U3";
NET "gtx_rxn_i[7]" LOC="U4";
# NET "gtx_rxp_i[7]" LOC="U3";
# NET "gtx_rxn_i[7]" LOC="U4";
NET "gtx_txp_o[7]" LOC="T1";
NET "gtx_txn_o[7]" LOC="T2";
# NET "gtx_txp_o[7]" LOC="T1";
# NET "gtx_txn_o[7]" LOC="T2";
NET "gtx_rxp_i[6]" LOC="R3";
NET "gtx_rxn_i[6]" LOC="R4";
# NET "gtx_rxp_i[6]" LOC="R3";
# NET "gtx_rxn_i[6]" LOC="R4";
NET "gtx_txp_o[6]" LOC="P1";
NET "gtx_txn_o[6]" LOC="P2";
# NET "gtx_txp_o[6]" LOC="P1";
# NET "gtx_txn_o[6]" LOC="P2";
NET "gtx_rxp_i[5]" LOC="N3";
NET "gtx_rxn_i[5]" LOC="N4";
# NET "gtx_rxp_i[5]" LOC="N3";
# NET "gtx_rxn_i[5]" LOC="N4";
NET "gtx_txp_o[5]" LOC="M1";
NET "gtx_txn_o[5]" LOC="M2";
# NET "gtx_txp_o[5]" LOC="M1";
# NET "gtx_txn_o[5]" LOC="M2";
NET "gtx_rxp_i[4]" LOC="L3";
NET "gtx_rxn_i[4]" LOC="L4";
# NET "gtx_rxp_i[4]" LOC="L3";
# NET "gtx_rxn_i[4]" LOC="L4";
NET "gtx_txp_o[4]" LOC="K1";
NET "gtx_txn_o[4]" LOC="K2";
# NET "gtx_txp_o[4]" LOC="K1";
# NET "gtx_txn_o[4]" LOC="K2";
NET "gtx_rxp_i[3]" LOC="K5"; #gtx14
NET "gtx_rxn_i[3]" LOC="K6";
# NET "gtx_rxp_i[3]" LOC="K5"; #gtx14
# NET "gtx_rxn_i[3]" LOC="K6";
NET "gtx_txp_o[3]" LOC="H1";
NET "gtx_txn_o[3]" LOC="H2";
# NET "gtx_txp_o[3]" LOC="H1";
# NET "gtx_txn_o[3]" LOC="H2";
NET "gtx_rxp_i[2]" LOC="J3"; # gtx15
NET "gtx_rxn_i[2]" LOC="J4";
# NET "gtx_rxp_i[2]" LOC="J3"; # gtx15
# NET "gtx_rxn_i[2]" LOC="J4";
NET "gtx_txp_o[2]" LOC="F1";
NET "gtx_txn_o[2]" LOC="F2";
# NET "gtx_txp_o[2]" LOC="F1";
# NET "gtx_txn_o[2]" LOC="F2";
NET "gtx_rxp_i[1]" LOC="G3"; # gtx16
NET "gtx_rxn_i[1]" LOC="G4";
......@@ -260,13 +260,13 @@ NET "gtx_txn_o[0]" LOC="C4";
NET "led_act_o[0]" LOC="AE33";
NET "led_act_o[1]" LOC="AE34";
NET "led_act_o[2]" LOC="AB30";
NET "led_act_o[3]" LOC="AC30";
# NET "led_act_o[2]" LOC="AB30";
# NET "led_act_o[3]" LOC="AC30";
NET "led_act_o[4]" LOC="AA26";
NET "led_act_o[5]" LOC="AA25";
NET "led_act_o[6]" LOC="AB27";
NET "led_act_o[7]" LOC="AC27";
# NET "led_act_o[4]" LOC="AA26";
# NET "led_act_o[5]" LOC="AA25";
# NET "led_act_o[6]" LOC="AB27";
# NET "led_act_o[7]" LOC="AC27";
NET "clk_dmtd_divsel_o" LOC="AN15";
......@@ -318,7 +318,7 @@ TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%;
#NET "gen_phys[7].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[7].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_7__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[7].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[8].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[8].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_8__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[8].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
# TIMESPEC TS_gen_phys_8__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[8].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[8].U_PHY/tx_out_clk_bufin" TNM_NET = gen_phys[8].U_PHY/tx_out_clk_bufin;
#TIMESPEC TS_gen_phys_8__U_PHY_tx_out_clk_bufin = PERIOD "gen_phys[8].U_PHY/tx_out_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[9].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[9].U_PHY/rx_rec_clk_bufin;
......@@ -355,10 +355,10 @@ TIMESPEC TS_gen_phys_8__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[8].U_PHY/rx_re
#TIMESPEC TS_gtx8_11_clk_n_i = PERIOD "gtx8_11_clk_n_i" 8 ns HIGH 50%;
#NET "gtx8_11_clk_p_i" TNM_NET = gtx8_11_clk_p_i;
#TIMESPEC TS_gtx8_11_clk_p_i = PERIOD "gtx8_11_clk_p_i" 8 ns HIGH 50%;
NET "gtx12_15_clk_n_i" TNM_NET = gtx12_15_clk_n_i;
TIMESPEC TS_gtx12_15_clk_n_i = PERIOD "gtx12_15_clk_n_i" 8 ns HIGH 50%;
NET "gtx12_15_clk_p_i" TNM_NET = gtx12_15_clk_p_i;
TIMESPEC TS_gtx12_15_clk_p_i = PERIOD "gtx12_15_clk_p_i" 8 ns HIGH 50%;
# NET "gtx12_15_clk_n_i" TNM_NET = gtx12_15_clk_n_i;
# TIMESPEC TS_gtx12_15_clk_n_i = PERIOD "gtx12_15_clk_n_i" 8 ns HIGH 50%;
# NET "gtx12_15_clk_p_i" TNM_NET = gtx12_15_clk_p_i;
# TIMESPEC TS_gtx12_15_clk_p_i = PERIOD "gtx12_15_clk_p_i" 8 ns HIGH 50%;
NET "gtx16_19_clk_n_i" TNM_NET = gtx16_19_clk_n_i;
TIMESPEC TS_gtx16_19_clk_n_i = PERIOD "gtx16_19_clk_n_i" 8 ns HIGH 50%;
NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i;
......
top/scb_8ports/scb_top_synthesis.vhd
View file @ 23979725
......@@ -153,11 +153,11 @@ entity scb_top_synthesis is
--gtx4_7_clk_n_i : in std_logic;
--gtx4_7_clk_p_i : in std_logic;
gtx8_11_clk_n_i : in std_logic;
gtx8_11_clk_p_i : in std_logic;
--gtx8_11_clk_n_i : in std_logic;
--gtx8_11_clk_p_i : in std_logic;
gtx12_15_clk_n_i : in std_logic;
gtx12_15_clk_p_i : in std_logic;
--gtx12_15_clk_n_i : in std_logic;
--gtx12_15_clk_p_i : in std_logic;
gtx16_19_clk_n_i : in std_logic;
gtx16_19_clk_p_i : in std_logic;
......@@ -168,11 +168,11 @@ entity scb_top_synthesis is
--gtx_txp_o : out std_logic_vector(17 downto 0);
--gtx_txn_o : out std_logic_vector(17 downto 0);
gtx_rxp_i : in std_logic_vector(7 downto 0);
gtx_rxn_i : in std_logic_vector(7 downto 0);
gtx_rxp_i : in std_logic_vector(1 downto 0);
gtx_rxn_i : in std_logic_vector(1 downto 0);
gtx_txp_o : out std_logic_vector(7 downto 0);
gtx_txn_o : out std_logic_vector(7 downto 0);
gtx_txp_o : out std_logic_vector(1 downto 0);
gtx_txn_o : out std_logic_vector(1 downto 0);
---------------------------------------------------------------------------
-- Mini-Backplane signals
......@@ -223,8 +223,8 @@ architecture Behavioral of scb_top_synthesis is
end component;
constant c_NUM_PHYS : integer := 8;
constant c_NUM_PORTS : integer := 8;
constant c_NUM_PHYS : integer := 2;
constant c_NUM_PORTS : integer := 2;
function f_bool2int(x : boolean) return integer is
begin
......@@ -299,8 +299,8 @@ architecture Behavioral of scb_top_synthesis is
attribute buffer_type of clk_aux : signal is "BUFG";
attribute buffer_type of clk_sys : signal is "BUFG";
signal local_reset, ext_pll_reset : std_logic;
signal clk_ext, clk_ext_mul : std_logic;
signal local_reset, ext_pll_reset : std_logic;
signal clk_ext, clk_ext_mul : std_logic;
signal clk_ext_100 : std_logic;
signal ext_pll_100_locked, ext_pll_62_locked : std_logic;
signal clk_ext_mul_locked : std_logic;
......@@ -323,8 +323,8 @@ architecture Behavioral of scb_top_synthesis is
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
......@@ -439,25 +439,25 @@ begin
-- IB => gtx4_7_clk_n_i
-- );
U_Clk_Buf_GTX8_11 : IBUFDS_GTXE1
port map
(
O => clk_gtx8_11,
ODIV2 => open,
CEB => '0',
I => gtx8_11_clk_p_i,
IB => gtx8_11_clk_n_i
);
--U_Clk_Buf_GTX8_11 : IBUFDS_GTXE1
-- port map
-- (
-- O => clk_gtx8_11,
-- ODIV2 => open,
-- CEB => '0',
-- I => gtx8_11_clk_p_i,
-- IB => gtx8_11_clk_n_i
-- );
U_Clk_Buf_GTX12_15 : IBUFDS_GTXE1
port map
(
O => clk_gtx12_15,
ODIV2 => open,
CEB => '0',
I => gtx12_15_clk_p_i,
IB => gtx12_15_clk_n_i
);
--U_Clk_Buf_GTX12_15 : IBUFDS_GTXE1
-- port map
-- (
-- O => clk_gtx12_15,
-- ODIV2 => open,
-- CEB => '0',
-- I => gtx12_15_clk_p_i,
-- IB => gtx12_15_clk_n_i
-- );
U_Clk_Buf_GTX16_19 : IBUFDS_GTXE1
port map
......@@ -562,7 +562,7 @@ begin
g_width => 1000)
port map(
clk_i => clk_sys,
rst_n_i => sys_rst_n_i,
rst_n_i => sys_rst_n_i,
pulse_i => local_reset,
extended_o => ext_pll_reset);
......@@ -620,13 +620,13 @@ begin
-------------------------------------------------------------------------------
clk_gtx(1 downto 0) <= (others => clk_gtx16_19);
clk_gtx(5 downto 2) <= (others => clk_gtx12_15);
clk_gtx(7 downto 6) <= (others => clk_gtx8_11);
--clk_gtx(5 downto 2) <= (others => clk_gtx12_15);
--clk_gtx(7 downto 6) <= (others => clk_gtx8_11);
--clk_gtx(11 downto 8) <= (others => clk_gtx8_11);
--clk_gtx(14 downto 12) <= (others => clk_gtx12_15);
--clk_gtx(17 downto 16) <= (others => clk_gtx16_19);
--generate first 4 GTXes with BUFR to reduce the number of global clocks
gen_phys_bufr : for i in 0 to 3 generate
gen_phys_bufr : for i in 0 to 1 generate
U_PHY : wr_gtx_phy_virtex6
generic map (
......@@ -657,36 +657,36 @@ begin
from_phys(i).ref_clk <= clk_ref;
end generate gen_phys_bufr;
gen_phys : for i in 4 to c_NUM_PHYS-1 generate
U_PHY : wr_gtx_phy_virtex6
generic map (
g_simulation => f_bool2int(g_simulation),
g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4),
g_use_bufr => false)
port map (
clk_gtx_i => clk_gtx(i),
clk_ref_i => clk_ref,
tx_data_i => to_phys(i).tx_data,
tx_k_i => to_phys(i).tx_k,
tx_disparity_o => from_phys(i).tx_disparity,
tx_enc_err_o => from_phys(i).tx_enc_err,
rx_rbclk_o => from_phys(i).rx_clk,
rx_data_o => from_phys(i).rx_data,
rx_k_o => from_phys(i).rx_k,
rx_enc_err_o => from_phys(i).rx_enc_err,
rx_bitslide_o => from_phys(i).rx_bitslide,
rst_i => to_phys(i).rst,
loopen_i => to_phys(i).loopen,
pad_txn_o => gtx_txn_o(i),
pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i),
pad_rxp_i => gtx_rxp_i(i),
rdy_o => from_phys(i).rdy);
from_phys(i).ref_clk <= clk_ref;
end generate gen_phys;
--gen_phys : for i in 4 to c_NUM_PHYS-1 generate
-- U_PHY : wr_gtx_phy_virtex6
-- generic map (
-- g_simulation => f_bool2int(g_simulation),
-- g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4),
-- g_use_bufr => false)
-- port map (
-- clk_gtx_i => clk_gtx(i),
-- clk_ref_i => clk_ref,
-- tx_data_i => to_phys(i).tx_data,
-- tx_k_i => to_phys(i).tx_k,
-- tx_disparity_o => from_phys(i).tx_disparity,
-- tx_enc_err_o => from_phys(i).tx_enc_err,
-- rx_rbclk_o => from_phys(i).rx_clk,
-- rx_data_o => from_phys(i).rx_data,
-- rx_k_o => from_phys(i).rx_k,
-- rx_enc_err_o => from_phys(i).rx_enc_err,
-- rx_bitslide_o => from_phys(i).rx_bitslide,
-- rst_i => to_phys(i).rst,
-- loopen_i => to_phys(i).loopen,
-- pad_txn_o => gtx_txn_o(i),
-- pad_txp_o => gtx_txp_o(i),
-- pad_rxn_i => gtx_rxn_i(i),
-- pad_rxp_i => gtx_rxp_i(i),
-- rdy_o => from_phys(i).rdy);
-- from_phys(i).ref_clk <= clk_ref;
--end generate gen_phys;
gen_terminate_unused_phys : for i in c_NUM_PORTS to c_NUM_PHYS-1 generate
to_phys(i).tx_data <= (others => '0');
......@@ -722,7 +722,7 @@ begin
clk_dmtd_i => clk_dmtd,
clk_sys_o => clk_sys,
clk_aux_i => clk_aux,
clk_ext_mul_i => clk_ext_mul,
clk_ext_mul_i => clk_ext_mul,
clk_ext_mul_locked_i=> clk_ext_mul_locked,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
......
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