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White Rabbit Switch - Gateware
Commit 1844c34e authored by Maciej Lipinski's avatar Maciej Lipinski
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scb_top_sim: bugfixes

parent 917a7488
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Showing with 17 additions and 8 deletions
testbench/scb_top/main.sv
View file @ 1844c34e
......@@ -17,8 +17,9 @@ module main;
reg clk_ref=0;
reg clk_sys=0;
reg clk_mpm_core=0;
reg rst_n=0;
parameter g_num_ports = 6;
......@@ -33,6 +34,7 @@ module main;
);
-----/\----- EXCLUDED -----/\----- */
always #5ns clk_mpm_core <=~clk_mpm_core;
always #8ns clk_sys <= ~clk_sys;
always #7.998ns clk_ref <= ~clk_ref;
......@@ -116,7 +118,8 @@ module main;
.clk_sys_i(clk_sys),
.clk_ref_i(clk_ref),
.rst_n_i(rst_n),
.cpu_irq(cpu_irq)
.cpu_irq(cpu_irq),
.clk_mpm_core_i(clk_mpm_core)
);
typedef struct {
......
testbench/scb_top/scb_top_sim_svwrap.svh
View file @ 1844c34e
......@@ -44,15 +44,15 @@ module scb_top_sim_svwrap
clk_sys_i,
clk_ref_i,
rst_n_i,
cpu_irq
cpu_irq,
clk_mpm_core_i
);
parameter g_num_ports = 6;
input clk_sys_i, clk_ref_i,rst_n_i;
input clk_sys_i, clk_ref_i,rst_n_i,clk_mpm_core_i;
output cpu_irq;
......@@ -260,6 +260,7 @@ scb_top_sim
.clk_ref_i ( clk_ref_i),
.clk_dmtd_i ( clk_ref_i),
.clk_sys_i ( clk_sys_i),
.clk_mpm_core_i ( clk_mpm_core_i),
.wb_adr_i ( cpu.master.adr),
.wb_dat_i ( cpu.master.dat_o),
.wb_dat_o ( cpu.master.dat_i),
......
top/bare_top/scb_top_sim.vhd
View file @ 1844c34e
......@@ -130,7 +130,7 @@ begin -- rtl
clk_swc_mpm_core_i => clk_swc_mpm_core_i,
cpu_wb_i => cpu_wb_in,
cpu_wb_o => cpu_wb_out,
cpu_irq_n_o => cpu_irq_n,
cpu_irq_n_o => cpu_irq_n,
pps_i => pps_i,
pps_o => pps_o,
dac_helper_sync_n_o => dac_helper_sync_n_o,
......@@ -153,7 +153,10 @@ begin -- rtl
phys_o => phys_out,
phys_i => phys_in,
led_link_o => led_link_o,
led_act_o => led_act_o);
led_act_o => led_act_o,
gpio_o => open,
gpio_i => (others => '0')
);
gen_phys : for i in 0 to g_num_ports-1 generate
td_o(18 * i + 15 downto 18 * i) <= phys_out(i).tx_data;
......
top/bare_top/wrsw_top_pkg.vhd
View file @ 1844c34e
......@@ -243,7 +243,9 @@ package wrsw_top_pkg is
phys_o : out t_phyif_output_array(g_num_ports-1 downto 0);
phys_i : in t_phyif_input_array(g_num_ports-1 downto 0);
led_link_o : out std_logic_vector(g_num_ports-1 downto 0);
led_act_o : out std_logic_vector(g_num_ports-1 downto 0));
led_act_o : out std_logic_vector(g_num_ports-1 downto 0);
gpio_o : out std_logic_vector(31 downto 0);
gpio_i : in std_logic_vector(31 downto 0));
end component;
component xswc_core is
......
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