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W
White Rabbit Switch - Gateware
Commit 0e2e8d7c authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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wrs_ljd: use bufr for 8port like to 18port

parent 8d17a35c
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Showing with 9 additions and 2 deletions
top/scb_8ports/scb_top_synthesis.vhd
View file @ 0e2e8d7c
...@@ -344,7 +344,7 @@ architecture Behavioral of scb_top_synthesis is ...@@ -344,7 +344,7 @@ architecture Behavioral of scb_top_synthesis is
signal ext_board_detected : std_logic := '0'; signal ext_board_detected : std_logic := '0';
signal ext_clk_10MHz, ext_clk_10MHz_bufr, clk_10mhz : std_logic; signal ext_clk_10MHz, ext_clk_10MHz_bufr, clk_10mhz : std_logic;
signal ext_clk_62mhz : std_logic; signal ext_clk_62mhz, ext_clk_62mhz_bufr : std_logic;
signal dac_main_sync_n : std_logic; signal dac_main_sync_n : std_logic;
signal dac_main_sclk : std_logic; signal dac_main_sclk : std_logic;
signal dac_main_data : std_logic; signal dac_main_data : std_logic;
...@@ -551,6 +551,13 @@ begin ...@@ -551,6 +551,13 @@ begin
I => ext_clk_62mhz_p_i, I => ext_clk_62mhz_p_i,
IB => ext_clk_62mhz_n_i); IB => ext_clk_62mhz_n_i);
U_Buf_ext_clk_62mhz_bufr : BUFR
port map (
CE => '1',
CLR => '0',
I => ext_clk_62mhz,
O => ext_clk_62mhz_bufr);
U_Buf_ext_clk10mhz : IBUFDS U_Buf_ext_clk10mhz : IBUFDS
generic map ( generic map (
DIFF_TERM => true, DIFF_TERM => true,
...@@ -681,7 +688,7 @@ begin ...@@ -681,7 +688,7 @@ begin
clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked; clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked;
clk_ext_mul_vec(0) <= clk_ext_mul; clk_ext_mul_vec(0) <= clk_ext_mul;
clk_ext_mul_vec(1) <= ext_clk_62mhz; clk_ext_mul_vec(1) <= ext_clk_62mhz_bufr;
--dbg_clk_ext_o <= clk_ext_mul; --dbg_clk_ext_o <= clk_ext_mul;
local_reset <= not sys_rst_n_i; local_reset <= not sys_rst_n_i;
......
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