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White Rabbit Switch - Gateware
Commit 0cd8fbe6 authored by Maciej Lipinski's avatar Maciej Lipinski
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[SYN 8/18] added BUFG attributes

parent 0dd531bc
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Showing with 20 additions and 7 deletions
top/scb_18ports/scb_top_synthesis.vhd
View file @ 0cd8fbe6
......@@ -176,7 +176,7 @@ architecture Behavioral of scb_top_synthesis is
attribute maxskew: string;
attribute maxskew of clk_dmtd : signal is "0.5ns";
attribute buffer_type : string;
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
......@@ -212,6 +212,11 @@ architecture Behavioral of scb_top_synthesis is
signal clk_gtx12_15 : std_logic;
signal clk_gtx16_19 : std_logic;
attribute buffer_type of clk_dmtd : signal is "BUFG";
attribute buffer_type of clk_ref : signal is "BUFG";
attribute buffer_type of clk_aux : signal is "BUFG";
attribute buffer_type of clk_sys : signal is "BUFG";
signal clk_gtx : std_logic_vector(c_NUM_PHYS-1 downto 0);
signal cpu_nwait_int : std_logic;
......@@ -225,6 +230,7 @@ architecture Behavioral of scb_top_synthesis is
signal i2c_sda_out : std_logic_vector(2 downto 0);
signal i2c_sda_in : std_logic_vector(2 downto 0);
signal i2c_scl_in : std_logic_vector(2 downto 0);
component scb_top_bare
generic (
g_num_ports : integer;
......@@ -232,7 +238,8 @@ architecture Behavioral of scb_top_synthesis is
g_without_network : boolean;
g_with_TRU : boolean;
g_with_TATSU : boolean;
g_with_HWDU : boolean);
g_with_HWDU : boolean;
g_with_PSTATS : boolean);
port (
sys_rst_n_i : in std_logic;
clk_startup_i : in std_logic;
......@@ -262,7 +269,7 @@ architecture Behavioral of scb_top_synthesis is
uart_rxd_i : in std_logic;
clk_en_o : out std_logic;
clk_sel_o : out std_logic;
-- uart_sel_o : out std_logic;
uart_sel_o : out std_logic;
clk_dmtd_divsel_o : out std_logic;
phys_o : out t_phyif_output_array(g_num_ports-1 downto 0);
phys_i : in t_phyif_input_array(g_num_ports-1 downto 0);
......@@ -556,9 +563,10 @@ begin
g_num_ports => c_NUM_PORTS,
g_simulation => g_simulation,
g_without_network => false,
g_with_TRU => true,
g_with_TATSU => true,
g_with_HWDU => true)
g_with_TRU => false,
g_with_TATSU => false,
g_with_HWDU => false,
g_with_PSTATS => false)
port map (
sys_rst_n_i => sys_rst_n_i,
clk_startup_i => clk_sys_startup,
......
top/scb_8ports/scb_top_synthesis.vhd
View file @ 0cd8fbe6
......@@ -177,7 +177,7 @@ architecture Behavioral of scb_top_synthesis is
signal clk_sys, clk_ref, clk_25mhz , clk_dmtd : std_logic;
signal pllout_clk_fb : std_logic;
attribute buffer_type : string;
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
......@@ -213,6 +213,11 @@ architecture Behavioral of scb_top_synthesis is
signal clk_gtx12_15 : std_logic;
signal clk_gtx16_19 : std_logic;
attribute buffer_type of clk_dmtd : signal is "BUFG";
attribute buffer_type of clk_ref : signal is "BUFG";
attribute buffer_type of clk_aux : signal is "BUFG";
attribute buffer_type of clk_sys : signal is "BUFG";
signal clk_gtx : std_logic_vector(c_NUM_PHYS-1 downto 0);
signal cpu_nwait_int : std_logic;
......
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