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White Rabbit Switch - Gateware
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White Rabbit Switch - Gateware
Commits
08c1eba5
Commit
08c1eba5
authored
Jul 17, 2012
by
Tomasz Wlostowski
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wrsw_txtsu: re-generated WB slave using newer wbgen
parent
f559a450
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2 changed files
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237 additions
and
242 deletions
+237
-242
wrsw_txtsu_wb.vhd
modules/wrsw_txtsu/wrsw_txtsu_wb.vhd
+226
-231
xwrsw_txtsu.vhd
modules/wrsw_txtsu/xwrsw_txtsu.vhd
+11
-11
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modules/wrsw_txtsu/wrsw_txtsu_wb.vhd
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08c1eba5
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modules/wrsw_txtsu/xwrsw_txtsu.vhd
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08c1eba5
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-26
-- Last update: 2012-0
3-16
-- Last update: 2012-0
7-12
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -81,16 +81,16 @@ architecture syn of xwrsw_tx_tsu is
component
wrsw_txtsu_wb
port
(
rst_n_i
:
in
std_logic
;
wb_clk
_i
:
in
std_logic
;
wb_ad
d
r_i
:
in
std_logic_vector
(
2
downto
0
);
wb_dat
a
_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat
a
_o
:
out
std_logic_vector
(
31
downto
0
);
clk_sys
_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
2
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_i
rq
_o
:
out
std_logic
;
wb_i
nt
_o
:
out
std_logic
;
txtsu_tsf_wr_req_i
:
in
std_logic
;
txtsu_tsf_wr_full_o
:
out
std_logic
;
txtsu_tsf_wr_empty_o
:
out
std_logic
;
...
...
@@ -198,16 +198,16 @@ begin -- syn
U_WB_SLAVE
:
wrsw_txtsu_wb
port
map
(
rst_n_i
=>
rst_n_i
,
wb_clk
_i
=>
clk_sys_i
,
wb_ad
d
r_i
=>
wb_in
.
adr
(
2
downto
0
),
wb_dat
a
_i
=>
wb_in
.
dat
,
wb_dat
a
_o
=>
wb_out
.
dat
,
clk_sys
_i
=>
clk_sys_i
,
wb_adr_i
=>
wb_in
.
adr
(
2
downto
0
),
wb_dat_i
=>
wb_in
.
dat
,
wb_dat_o
=>
wb_out
.
dat
,
wb_cyc_i
=>
wb_in
.
cyc
,
wb_sel_i
=>
wb_in
.
sel
,
wb_stb_i
=>
wb_in
.
stb
,
wb_we_i
=>
wb_in
.
we
,
wb_ack_o
=>
wb_out
.
ack
,
wb_i
rq
_o
=>
wb_out
.
int
,
wb_i
nt
_o
=>
wb_out
.
int
,
txtsu_tsf_wr_req_i
=>
txtsu_tsf_wr_req
,
txtsu_tsf_wr_full_o
=>
txtsu_tsf_wr_full
,
txtsu_tsf_wr_empty_o
=>
txtsu_tsf_wr_empty
,
...
...
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