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White Rabbit Switch - Gateware
Commit 00d5427c authored by Maciej Lipinski's avatar Maciej Lipinski
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[swcore/rtu] added abort from input_block@swcore to rtu - in case where frame is… 

[swcore/rtu] added abort from input_block@swcore to rtu - in case where frame is dropped (ouput stuck) and rtu is processing when we finish with the frame... we abort the decision
parent 9dc13c74
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Showing with 32 additions and 18 deletions
modules/wrsw_rtu/rtu_port_new.vhd
View file @ 00d5427c
......@@ -333,8 +333,8 @@ begin
-- request to aboard full match
full_match_aboard <= (not full_match_valid) and -- suppress when we have replay from full match
((aboard_possible and fast_match_wr_req) or -- new request when full match busy
(rtu_rsp_abort_i)); -- other externa, e.g. from swcore, **not implemented yet
((aboard_possible and fast_match_wr_req));-- or -- new request when full match busy
-- (rtu_rsp_abort_i)); -- other externa, e.g. from swcore, **not implemented yet
--------------------------------------------------------------------------------------------
-- register input request to make it available for both matches (full/fast)
......@@ -513,7 +513,7 @@ begin
------------------------------------------------------------------------------------------------------------
when S_FAST_MATCH =>
if(rtu_rq_abort_i = '1') then
if(rtu_rq_abort_i = '1' or rtu_rsp_abort_i = '1') then
port_state <= S_IDLE;
elsif(dbg_force_full_match_only = '1') then
port_state <= S_FULL_MATCH;
......@@ -544,11 +544,11 @@ begin
delayed_full_match_wr_req <= '1';
end if;
end if;
elsif(rtu_rsp_abort_i = '1' and fast_match.valid = '0') then
-- TODO: this should not happen -> handle exeption
port_state <= S_FINAL_MASK;
rsp <= c_rtu_rsp_drop;
delayed_full_match_wr_req <= '0';
-- elsif(rtu_rsp_abort_i = '1' and fast_match.valid = '0') then
-- -- TODO: this should not happen -> handle exeption
-- port_state <= S_FINAL_MASK;
-- rsp <= c_rtu_rsp_drop;
-- delayed_full_match_wr_req <= '0';
end if;
------------------------------------------------------------------------------------------------------------
......@@ -559,7 +559,7 @@ begin
------------------------------------------------------------------------------------------------------------
when S_FULL_MATCH =>
if(rtu_rq_abort_i = '1') then
if(rtu_rq_abort_i = '1' or rtu_rsp_abort_i = '1') then
port_state <= S_IDLE;
delayed_full_match_wr_req <= '0';
elsif(full_match_aboard = '0' and full_match_req_in_progress = '0' and full_match_wr_full_i = '0' and rq_rsp_cnt = 0) then
......@@ -588,7 +588,7 @@ begin
------------------------------------------------------------------------------------------------------------
when S_FINAL_MASK =>
if(rtu_rq_abort_i = '1') then
if(rtu_rq_abort_i = '1' or rtu_rsp_abort_i = '1') then
port_state <= S_IDLE;
delayed_full_match_wr_req <= '0';
elsif(rsp.valid = '0') then
......
modules/wrsw_rtu/xwrsw_rtu_new.vhd
View file @ 00d5427c
......@@ -153,6 +153,7 @@ entity xwrsw_rtu_new is
rsp_o : out t_rtu_response_array(g_num_ports-1 downto 0);
rsp_ack_i : in std_logic_vector(g_num_ports-1 downto 0);
rq_abort_i : in std_logic_vector(g_num_ports-1 downto 0);
rsp_abort_i : in std_logic_vector(g_num_ports-1 downto 0);
tru_req_o : out t_tru_request;
tru_resp_i : in t_tru_response;
rtu2tru_o : out t_rtu2tru;
......@@ -348,7 +349,7 @@ begin
rtu_idle_o => port_idle(i), -- TODO: req_full_o ??/
rtu_rq_i => req_i(i),
rtu_rq_abort_i => rq_abort_i(i),
rtu_rsp_abort_i => '0', -- new stuff from SWcore
rtu_rsp_abort_i => rsp_abort_i(i),--'0', -- new stuff from SWcore
rtu_rsp_o => rsp(i),
rtu_rsp_ack_i => rsp_ack_i(i),
......
modules/wrsw_swcore/xswc_input_block.vhd
View file @ 00d5427c
......@@ -797,7 +797,8 @@ begin --archS_PCKSTART_SET_AND_REQ
rp_in_pck_err <= '0';
rp_accept_rtu <= '1';
rp_rcv_first_page <= '0';
rp_rcv_first_page <= '0';
rtu_rsp_abort_o <= '0';
--========================================
else
......@@ -817,6 +818,7 @@ begin --archS_PCKSTART_SET_AND_REQ
snk_stall_force_l <= '1';
in_pck_dvalid_d0 <= '0';
in_pck_dat_d0 <= (others => '0');
rtu_rsp_abort_o <= '0';
-- Sync with trasnfer_pck FSM and ll_write FSM:
if(lw_sync_first_stage = '1' and rp_sync = '1' and tp_sync = '1') then
......@@ -848,7 +850,7 @@ begin --archS_PCKSTART_SET_AND_REQ
snk_stall_force_l <= '0';
snk_stall_force_h <= '1';
rp_drop_on_stuck <= '1';
rp_accept_rtu <= '1';
rp_accept_rtu <= '0'; -- high one cycle later (in drop)
else -- by default: stall when stuck
snk_stall_force_h <= '1';
snk_stall_force_l <= '1';
......@@ -1026,11 +1028,18 @@ begin --archS_PCKSTART_SET_AND_REQ
when S_DROP =>
--===========================================================================================
if (in_pck_eof = '1' or in_pck_err = '1') then
rp_drop_on_stuck <= '0';
snk_stall_force_h <= '1';
snk_stall_force_l <= '1';
s_rcv_pck <= S_IDLE;
if(rp_accept_rtu = '1' and rtu_rsp_valid_i = '0' ) then
-- no RTU decision for the frame, abort rtu match
rtu_rsp_abort_o <= '1';
end if;
end if;
--===========================================================================================
......@@ -1087,7 +1096,8 @@ begin --archS_PCKSTART_SET_AND_REQ
if(g_input_block_cannot_accept_data = "drop_pck") then
snk_stall_force_l <= '0';
if (in_pck_sof = '1') then
s_rcv_pck <= S_DROP;
rp_accept_rtu <= '1';
s_rcv_pck <= S_DROP;
end if;
-- by default: stall when stuck
......
top/bare_top/scb_top_bare.vhd
View file @ 00d5427c
......@@ -139,7 +139,7 @@ end scb_top_bare;
architecture rtl of scb_top_bare is
constant c_GW_VERSION : std_logic_vector(31 downto 0) := x"13_11_13_03"; --DD_MM_YY_VV
constant c_GW_VERSION : std_logic_vector(31 downto 0) := x"14_11_13_02"; --DD_MM_YY_VV
constant c_NUM_WB_SLAVES : integer := 16;
constant c_NUM_PORTS : integer := g_num_ports;
constant c_MAX_PORTS : integer := 18;
......@@ -271,7 +271,7 @@ architecture rtl of scb_top_bare is
signal rtu_req : t_rtu_request_array(c_NUM_PORTS downto 0);
signal rtu_rsp : t_rtu_response_array(c_NUM_PORTS downto 0);
signal rtu_req_ack, rtu_full, rtu_rsp_ack, rtu_rq_abort: std_logic_vector(c_NUM_PORTS downto 0);
signal rtu_req_ack, rtu_full, rtu_rsp_ack, rtu_rq_abort, rtu_rsp_abort: std_logic_vector(c_NUM_PORTS downto 0);
-- System clock selection: 0 = startup clock, 1 = PLL clock
signal sel_clk_sys, sel_clk_sys_int : std_logic;
......@@ -746,7 +746,7 @@ begin
rtu_rsp_i => rtu_rsp,
rtu_ack_o => rtu_rsp_ack,
rtu_abort_o => open --rtu_rsp_abort
rtu_abort_o =>rtu_rsp_abort-- open --rtu_rsp_abort
);
-- SWcore global pause nr=0 assigned to TRU
......@@ -787,7 +787,8 @@ begin
req_full_o => rtu_full(g_num_ports-1 downto 0),
rsp_o => rtu_rsp(g_num_ports-1 downto 0),
rsp_ack_i => rtu_rsp_ack(g_num_ports-1 downto 0),
rq_abort_i => rtu_rq_abort(g_num_ports-1 downto 0),
rsp_abort_i=> rtu_rsp_abort(g_num_ports-1 downto 0), -- this is request from response receiving node
rq_abort_i => rtu_rq_abort(g_num_ports-1 downto 0), -- this is request from requesting module
------ new TRU stuff ----------
tru_req_o => tru_req,
tru_resp_i => tru_resp,
......
top/bare_top/wrsw_components_pkg.vhd
View file @ 00d5427c
......@@ -298,6 +298,7 @@ package wrsw_components_pkg is
rsp_o : out t_rtu_response_array(g_num_ports-1 downto 0);
rsp_ack_i : in std_logic_vector(g_num_ports-1 downto 0);
rq_abort_i : in std_logic_vector(g_num_ports-1 downto 0);
rsp_abort_i : in std_logic_vector(g_num_ports-1 downto 0);
tru_req_o : out t_tru_request;
tru_resp_i : in t_tru_response;
rtu2tru_o : out t_rtu2tru;
......
top/bare_top/wrsw_top_pkg.vhd
View file @ 00d5427c
......@@ -350,6 +350,7 @@ package wrsw_top_pkg is
rsp_o : out t_rtu_response_array(g_num_ports-1 downto 0);
rsp_ack_i : in std_logic_vector(g_num_ports-1 downto 0);
rq_abort_i : in std_logic_vector(g_num_ports-1 downto 0);
rsp_abort_i : in std_logic_vector(g_num_ports-1 downto 0);
tru_req_o : out t_tru_request;
tru_resp_i : in t_tru_response;
rtu2tru_o : out t_rtu2tru;
......
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