... | ... | @@ -31,8 +31,27 @@ syn - contains ISE project files for sythesis (e.g. if you want to |
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sythesize for 18-port switch, you should go into syn/scb\_18ports)
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testbench - contains testbenches for top-level of the switch and
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separate modules, also for a network of switches
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top - contains top-levels and constraint (UCF) files
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\----
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top - contains top-levels and constraint (UCF) files
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-----
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The top/bare\_top/ contains scb\_top\_bare.vhd which is a configurable
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top level entity of the switch. This entity is used by both, sythesis
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top levels and testbench of the switch. In other words, this is a
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configurable IP which needs some more VHDL to simulate or sythesize.
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### Switch Testbench
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The testbench of the switch is written in SystemVerilog and contained in
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testbench/scb\_top/main.sv. It uses top/bare\_top/scb\_top\_bare.vhd
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indirectly:
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- scb\_top\_bare.vhd is instantiated in
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top/bare\_top/scb\_top\_sim.vhd
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- scb\_top\_sim.vhd is wrapped by
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testbench/scb\_top/scb\_top\_sim\_svwrap.svh
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- scb\_top\_sim\_svwrap.svh is used in the main testbench:
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testbench/scb\_top/main.sv
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## Simulation
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