... | ... | @@ -73,19 +73,61 @@ indirectly: |
|
|
- scb\_top\_sim\_svwrap.svh is used in the main testbench:
|
|
|
testbench/scb\_top/main.sv
|
|
|
|
|
|
### Switch Synthesis
|
|
|
## WRS gateware synthesis (v4.2)
|
|
|
|
|
|
ISE projects for switch synthesis are defined for different number of
|
|
|
ports (i.e. 8, 15, and 18) in the syn directory (e.g.: syn/scb\_18ports
|
|
|
for 18-switch synthesis). We synthesize for 8 ports to speed up
|
|
|
development process: synthesis for 18 ports takes 4h, for 8 ports 1h, so
|
|
|
we develop synthesizing for 8 ports.
|
|
|
ports (i.e. 8, 15, and 18) in the *syn* directory (e.g.:
|
|
|
syn/scb\_18ports for 18 port synthesis). The 8-port version is used by
|
|
|
developers to speed up testing all new functionalities and bugfixes
|
|
|
since the full 18-port synthesis takes ~3h. The ISE project in
|
|
|
*syn/scb\_18ports* relates to the top entity and UCF files in
|
|
|
*top/scb\_18ports* directory (*scb\_top\_synthesis.vhd* and
|
|
|
*scb\_top\_sythesis.ucf*). The *scb\_top\_sythesis.vhd* instantiates
|
|
|
*top/bare\_top/scb\_top\_bare.vhd* with proper parameters.
|
|
|
|
|
|
The ISE project in syn/scb\_18ports relates to the top entity and UCF
|
|
|
files in top/scb\_18ports directory, i.e. scb\_top\_synthesis.vhd and
|
|
|
scb\_top\_sythesis.ucf.
|
|
|
The scb\_top\_sythesis.vhd instantiates top/bare\_top/scb\_top\_bare.vhd
|
|
|
with proper parameters.
|
|
|
You need to make sure that you have all the tools for the switch
|
|
|
synthesis. You will need:
|
|
|
|
|
|
- *git* - to download the sources from our official repository
|
|
|
- *hdlmake* and *make* - to create a project file and run the
|
|
|
synthesis
|
|
|
- 64-bit version of Xilinx ISE 14.5 or above - for the actual
|
|
|
synthesis and bitstream generation
|
|
|
|
|
|
\# First you need to setup your environment
|
|
|
|
|
|
/opt/Xilinx/<version>/ISE_DS/settings64.sh
|
|
|
export XILINX=/opt/Xilinx/<version>/ISE_DS
|
|
|
|
|
|
\# Download the HDL
|
|
|
sources
|
|
|
|
|
|
git clone --recursive git:https://www.ohwr.org/white-rabbit/wr-switch-hdl.git
|
|
|
cd wr-switch-hdl
|
|
|
git checkout wr-switch-sw-v4.2
|
|
|
git submodule update
|
|
|
|
|
|
\# Generate SDB Metadata package with synthesis information
|
|
|
|
|
|
cd top/bare_top
|
|
|
./gen_sdbsyn.py --user <your name> --project WRS_18p --ver <ISE version>
|
|
|
|
|
|
\# Run the synthesis
|
|
|
|
|
|
cd ../../syn/scb_18ports
|
|
|
hdlmake --ise-proj --make-ise
|
|
|
make
|
|
|
|
|
|
This can take ~3 hours
|
|
|
|
|
|
\# Deploy your new
|
|
|
gateware
|
|
|
|
|
|
```
|
|
|
scp scb_top_synthesis.bin root@<your_switch_ip_address>:/wr/lib/firmware/18p_mb-LX240T.bin
|
|
|
```
|
|
|
|
|
|
1. Reboot the switch so that your new gateware is loaded
|
|
|
|
|
|
## Steps to run switch simulation
|
|
|
|
... | ... | @@ -202,30 +244,9 @@ The following steps are needed to simulate the switch |
|
|
do run.do
|
|
|
6. You should see frames flowing
|
|
|
|
|
|
## Steps to synthesize switch HDL (master/v4)
|
|
|
|
|
|
The following steps are needed to sythesize the switch for 18 ports
|
|
|
|
|
|
1. Clone the repo with submodules
|
|
|
git clone --recursive
|
|
|
git:https://www.ohwr.org/white-rabbit/wr-switch-hdl.git
|
|
|
2. Enter syn/scb\_8ports
|
|
|
cd syn/scb\_18ports
|
|
|
3. Generate/update ISE project by running
|
|
|
hdlmake --ise-proj
|
|
|
4. Generate Makefile:
|
|
|
hdlmake --make-ise
|
|
|
5. This should result in generation of proper Makefile (such as the
|
|
|
[Makefile](https://www.ohwr.org/2977)
|
|
|
generated for me - it will not work you your PC, but can be useful
|
|
|
to see)
|
|
|
6. Run synthesis:
|
|
|
make
|
|
|
7. Go for lunch now
|
|
|
|
|
|
-----
|
|
|
|
|
|
27 June 2014
|
|
|
30 October 2015
|
|
|
|
|
|
|
|
|
|
... | ... | |