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# For Developers
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Here is some information for people who want to contribute to the
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development of switch's HDL
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## HDLmake
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- Tool for generating multi-purpose makefiles for FPGA projects that
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is used to simulate and synthesize switch HDL
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- This page explains how to simulate/synthesize switch HDL using
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HDLmake
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- The website of the project is [here](projects/hdl-make)
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- Handful information about using HDLmake can be found in Chapter
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3.4.2 of the [Getting Started with the
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SPEC](https://www.ohwr.org/project/white-rabbit/uploads/e747a4d84a62dcb0f9d784621137b003/spec-getting-started-v1.0-201403.pdf)
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tutorial that is part of [Getting Started with
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SPEC](https://www.ohwr.org/project/spec-getting-started) project
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- Beware: we are currently using ISYP branch of the HDLmake
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## HDL directory structure
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-----
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ip\_cores - contains external cores used by the project (included in the
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git repo as submodules)
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modules - include specific-switch and FPGA-independent modules
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platform - contains FPGA-dependent stuff
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sim - contains SystemVerilog modeles, drivers and register layouts used
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by testbenches
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syn - contains ISE project files for sythesis (e.g. if you want to
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sythesize for 18-port switch, you should go into syn/scb\_18ports)
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testbench - contains testbenches for top-level of the switch and
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separate modules, also for a network of switches
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top - contains top-levels and constraint (UCF) files
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\----
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## Simulation
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- We use ModelSim as a simulation tool
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-
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### Files
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* [SwitchGWarchitecture.jpg](/uploads/63a1d6b10a371fb27f72cb6c5b41ac3c/SwitchGWarchitecture.jpg) |
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\ No newline at end of file |