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ML-tmp-btrain-debug-v6
cedf5726
·
hack wr-cores to make sim work
·
Jan 08, 2021
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ML-tmp-btrain-debug-CS
f7f16cfc
·
upated chipscipe (v3)
·
Jan 13, 2021
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ML-tmp-btrain-debug-CS-v6
b1dcf5f8
·
chipscope v6
·
Jan 18, 2021
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wr-switch-sw-lj-v6.0.1-dev
16b2efe3
·
Fixed DMTD BUFR and BUFG locations in design
·
Jan 19, 2022
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tom-10g-hacks
f0137c5c
·
rudimentary testbench for the RISC-V RT subsys
·
Nov 28, 2023
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hm-wrslj-v6
0b26cfb9
·
add dac_sel for new hardware and add some modifications from wrslj.
·
Nov 29, 2023
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ml_lj_unification
af344aa3
·
LJ: improve/generalize Low-Jitter functionality detection/handling (WIP)
·
Nov 29, 2023
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wr-switch-sw-v7.0-ddmtd-rev
ae063030
·
CI: experiment
·
Dec 01, 2023
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latest-hdlmake-fix
4fdd1d8a
·
HDLMAKE: fix to adapt to the latest changes (temp)
·
Dec 11, 2023
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harvey-v4
9a3b3c9f
·
added initial build scripts for wrsv4 bringup
·
Mar 20, 2024
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v7.0-DDMTD-enabled-reverse
3d4a19f5
·
Revert "DDMTD: disable reverse option, it needs to be coupled with relevant changes to wrpc-sw"
·
Apr 11, 2024
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adam-proposed_master
73ed763b
·
.gitlab-ci.yml: fix artifacts name for 18 ports
·
Apr 11, 2024
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v7.0-Jumbo-frames-fix-only
7fddb8cf
·
.gitlab-ci.yml: add CI from commit
73ed763b
·
Apr 11, 2024
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v7.0-back-to-v6.0
e5403f03
·
Revert "lpdc: fix for jumbo frames"
·
Apr 11, 2024
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wrs-v7.0-changed_ise_config
7c53f750
·
ISE config from v5.0 (should have better timing results...)
·
May 02, 2024
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adam-test
198139ab
·
revert add generated files by python
·
May 10, 2024
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adam-test2
37bde422
·
.gitlab-ci.yml: test2
·
May 10, 2024
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wr-switch-sw-v7.0_ise_properties
149f8dd3
·
.gitlab-ci.yml: test2
·
May 11, 2024
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adam-test3
23b98cda
·
.gitlab-ci.yml: test new image for 18ports
·
May 11, 2024
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ML-test-properties
ddf522b3
·
[ise] remove xise and xds files
·
May 12, 2024
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