... | @@ -5,7 +5,7 @@ The aim of this project is to evaluate resourcesrequired to run wr switch HDL on |
... | @@ -5,7 +5,7 @@ The aim of this project is to evaluate resourcesrequired to run wr switch HDL on |
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## Results
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## Results
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Based on the code in this repository, a short report was created. It may be found in the repository in `doc/report/main.pdf` [main.pdf](uploads/6cb9b1abf6696472f5fb4c0eb661a0ef/main.pdf).
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Based on the code in this repository, a short report was created [WRS resource utilisation on Xilinx US+ FPGA](uploads/6cb9b1abf6696472f5fb4c0eb661a0ef/main.pdf) (see `doc/report/` in the repository).
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## General question about project
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## General question about project
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... | @@ -16,4 +16,7 @@ Based on the code in this repository, a short report was created. It may be foun |
... | @@ -16,4 +16,7 @@ Based on the code in this repository, a short report was created. It may be foun |
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|**Date**|**Event**|
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|**Date**|**Event**|
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|01-08-2019| Project started | |
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|01-08-2019| Project started |
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|23-08-2019| 1Gb version (without and with redundancy features) synthesized for US+ (repoted in conf-call) |
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|06-09-2019| 10Gb version (without and with redundancy features) synthesized for US+ (repoted in conf-call) |
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|09-09-2019| Project with documentation delivered to CERN for feedback | |
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