... | ... | @@ -30,7 +30,6 @@ Result utilization for of switch HDL on Xilinx Ultrascale+ FPGA is presented bel |
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(post-synthesis report)
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![wrs_10g_redundancy_after_implementation](https://ohwr.org/project/wr-switch-hdl/wikis/uploads/a0ba5a6b54360fe24355c91d0ab3eead/wrs_10g_redundancy_after_implementation.PNG)
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(post-implementation report)<br />
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