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## Project Description
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The aim of this project is to evaluate resourcesrequired to run wr switch HDL on Xilinx Ultrascale+ FPGA.
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## General question about project
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- [Maciej Lipinski](mailto:maciej.lipinski@cern.ch) - CERN
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- [Marek Guminski](mailto:Marek.Guminski@creotech.pl) - Creotech
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## Status
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|**Date**|**Event**|
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|----|----|
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|01-08-2019| Project started | |
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