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The aim of this project is to evaluate resourcesrequired to run wr switch HDL on Xilinx Ultrascale+ FPGA.
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The aim of this project is to evaluate resourcesrequired to run wr switch HDL on Xilinx Ultrascale+ FPGA.
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## Results
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Based on the code in this repository, a short report was created. It may be found in the repository in `doc/report/main.pdf` [main.pdf](uploads/6cb9b1abf6696472f5fb4c0eb661a0ef/main.pdf).
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## General question about project
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## General question about project
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- [Maciej Lipinski](mailto:maciej.lipinski@cern.ch) - CERN
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- [Maciej Lipinski](mailto:maciej.lipinski@cern.ch) - CERN
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