... | ... | @@ -39,3 +39,4 @@ Result utilization for of switch HDL on Xilinx Ultrascale+ FPGA is presented bel |
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|23-08-2019| 1Gb version (without and with redundancy features) synthesized for US+ (repoted in conf-call) |
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|06-09-2019| 10Gb version (without and with redundancy features) synthesized for US+ (repoted in conf-call) |
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|09-09-2019| Project with documentation delivered to CERN for feedback |
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|09-10-2019| Final version approved by CERN - project closed | |
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