... | ... | @@ -38,4 +38,5 @@ Result utilization for of switch HDL on Xilinx Ultrascale+ FPGA is presented bel |
|
|
|01-08-2019| Project started |
|
|
|
|23-08-2019| 1Gb version (without and with redundancy features) synthesized for US+ (repoted in conf-call) |
|
|
|
|06-09-2019| 10Gb version (without and with redundancy features) synthesized for US+ (repoted in conf-call) |
|
|
|
|09-09-2019| Project with documentation delivered to CERN for feedback | |
|
|
\ No newline at end of file |
|
|
|09-09-2019| Project with documentation delivered to CERN for feedback |
|
|
|
|09-10-2019| Final version approved by CERN - project closed | |
|
|
\ No newline at end of file |