... | ... | @@ -5,26 +5,26 @@ The aim of this project is to evaluate resourcesrequired to run wr switch HDL on |
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## Results
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Based on the code in this repository, a short report was prepared: [WRS resource utilisation on Xilinx US+ FPGA](uploads/6cb9b1abf6696472f5fb4c0eb661a0ef/main.pdf) (see `doc/report/` in the repository).
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Based on the code in this repository, a short report was prepared: [WRS resource utilisation on Xilinx US+ FPGA](uploads/4e5d9590831242bb91cefa1efcaced47/main.pdf) (see `doc/report/` in the repository).
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Result utilization for of switch HDL on Xilinx Ultrascale+ FPGA is presented below (details in the report):
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**Switch with 1GbE and no redundancy features (proposed_master)**
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![1g_noredundancy](uploads/92536a9a5dfceec2ae72f583d0e387db/1g_noredundancy.png)
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![1g_noredundancy](uploads/d2e02bcea55901199092fa93a5f53b37/1g_noredundancy.png)
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**Switch with 1GbE and redundancy features (data and timing)**
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![1g_redundancy_3](uploads/7abe2fb68cdda3f481fab61900d7531c/1g_redundancy_3.png)
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![1g_redundancy](uploads/61f08018938281f667b8afed062b2c59/1g_redundancy.png)
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**Switch with 10GbE and no redundancy features**
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![10g_noredundancy](uploads/594f892788fd26e124fe07ed7550561a/10g_noredundancy.png)
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![10g_noredundancy](uploads/db0e8f910b57abfbec3185e7cf15c0a5/10g_noredundancy.png)
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**Switch with 10GbE and redundancy features (data and timing)**
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![10g_redundancy_2](uploads/f4aaa773fee1474c8c340ef70d775138/10g_redundancy_2.png)
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![10g_redundancy](uploads/bc7be1c9c1044bf4140ed7bce51abf72/10g_redundancy.png)
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## General question about project
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