... | ... | @@ -10,21 +10,28 @@ Based on the code in this repository, a short report was prepared: [WRS resource |
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Result utilization for of switch HDL on Xilinx Ultrascale+ FPGA is presented below (details in the report):
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**Switch with 1GbE and no redundancy features (proposed_master)**
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**Switch with 1GbE and no redundancy features (proposed_master) - post-synthesis report**
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![1g_noredundancy](uploads/d2e02bcea55901199092fa93a5f53b37/1g_noredundancy.png)
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**Switch with 1GbE and redundancy features (data and timing)**
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**Switch with 1GbE and redundancy features (data and timing) - post-synthesis report**
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![1g_redundancy](uploads/61f08018938281f667b8afed062b2c59/1g_redundancy.png)
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**Switch with 10GbE and no redundancy features**
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**Switch with 10GbE and no redundancy features - post-synthesis report**
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![10g_noredundancy](uploads/db0e8f910b57abfbec3185e7cf15c0a5/10g_noredundancy.png)
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**Switch with 10GbE and redundancy features (data and timing)**
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![10g_redundancy](uploads/bc7be1c9c1044bf4140ed7bce51abf72/10g_redundancy.png)
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![10g_redundancy](uploads/bc7be1c9c1044bf4140ed7bce51abf72/10g_redundancy.png)<br />
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(post-synthesis report)
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(post-implementation report)<br />
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## General question about project
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