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Resource Evaluation of WR switch HDL for Ultrascale Plus
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Dec 10, 2019
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Maciej Lipinski
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## Project Description
## Project Description
The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA.
The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA
(MPSoC XCZU11EG-1FFVC1156E).
## Results
## Results
...
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