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## Project Description
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The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA.
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The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA
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(MPSoC XCZU11EG-1FFVC1156E).
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## Results
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... | ... | |