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White Rabbit Network Interface Card
Commit 069fb021 authored by Javier Díaz's avatar Javier Díaz
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fecthing sources from switch hdl project

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Manifest.py
View file @ 069fb021
fetchto = "ip_cores"
modules = {"local" :
[ "modules/wrsw_nic",
"modules/wrsw_txtsu",
"modules/wrsw_dio"
],
"git" : "git://ohwr.org/hdl-core-lib/wr-cores.git::wishbonized",
modules = { "local" : ["modules/wrsw_dio"],
"git" : ["git://ohwr.org/white-rabbit/wr-switch-hdl.git",
"git://ohwr.org/hdl-core-lib/general-cores.git::no_coregen"],
"svn" : "http://svn.ohwr.org/gn4124-core/trunk/hdl/gn4124core/rtl"
}
......
doc/readme.mkd
View file @ 069fb021
......@@ -18,7 +18,7 @@ pandoc --toc -o wr-nic.pdf wr-nic.mkd
Additional info
=====================
Find peripherals register map from wbgen2 tool on NIC_peripheral_registers compressed file.
Find peripherals register map from wbgen2 tool on file NIC_peripheral_registers.tar.gz.
Problems?
------------
......
doc/wr-nic.mkd
View file @ 069fb021
% White-Rabbit NIC Gateware
% Javier Díaz, UGR-7S
% 21 Jun. 2012
% 30 Jul. 2012
Introduction
=========================
......@@ -33,7 +33,7 @@ The `GN4124 core` is a bridge between the GN4124 PCIe interface chip and the int
* The `TxTSU module` collect timestamps with associated Ethernet frame identifiers and puts them in a shared FIFO (port identifier is also included although not required for the SPEC card because only one Ethernet port is available but it is include to provide a common descriptor with the switch data). A IRQ is triggered when FIFO is not empty so drivers could read TX timestamps and frame/port identifiers.
In the next sections we provide a little more information about `DIO core` and the `WRPC (White Rabbit PTP Core)` in order to understand better how the whole system works.
Finally, it is important to know that current HDL code contains commented code to activate on-chip logic analyzer circuitry for debugging based on Chipscope of Xilinx. Top file as well as different peripherals include the signals TRIG0 - TRIG3 to help on this purpose. Nevertheless, by default they are commented to avoid wasting unnecessary resources.
Finally, it is important to know that current HDL code contains commented code to activate on-chip logic analyzer circuitry for debugging based on Chipscope of Xilinx. Top file as well as different peripherals include the signals TRIG0 - TRIG3 to help on this purpose. Nevertheless, by default they are commented to avoid wasting unnecessary resources (in fact it could be required to reduce blockram utilization, for instance of NIC or wr_core module in order to use Chipscope on the project, otherwise design is overmapped).
WRPC (White Rabbit PTP Core)
----------------------------
......@@ -143,18 +143,18 @@ This project could be used as starting demo with White-Rabbit technology, illust
* Applications examples.
Both elements are described in the software manual of the WR-NIC project and it is out of the scope of current document to describe their functionalities. Please read that document in order to have a global understanding of the NIC project.
Both elements are described in the software manual of the WR-NIC project and it is out of the scope of current document to describe them with further details. Please read that document in order to have a complete understanding of the NIC project.
Finally, as working examples, current release already provide the following applications:
* Simple transmission of timing information from the master to the slave, with nothing hooked to the external inputs of the boards.
* The master host could be configured as grandmasters (if external PPS and 10 MHz signal is available from GPS or Cesium clock) or just work as simple master (free-running).
* Simple transmission of timing information from the master to the slave, with nothing necessarily hooked to the external inputs of the boards.
* The master host could be configured as grandmaster (if external PPS and 10 MHz signal is available from GPS or Cesium clock) or just work as simple master (free-running).
* The slave host schedule a pulse output each second. Looking at the outputs on a scope we should see them perfectly aligned.
* Network latency measurements. This is interesting if we connect a switch between the SPEC cards. By using the timestamps on Ethernet frames we could get the measurement of the network latency, verify it it is constant or how traffic affect this parameter.
Many other options are possible. For instance, we could transmit an external frequency and schedule a similar output with a fixed delay on both nodes. We should be able to see a constant time offset between the two pulses on the scope. New examples will be added on next releases.
Many other options are possible. For instance, we could transmit an external frequency and schedule a similar output with a fixed delay on other nodes. We should be able to see a constant time offset between the two pulses on the scope. Examples like this could be added on next releases.
Troubleshooting
......
modules/wrsw_dio/immed_pulse_counter.vhd
View file @ 069fb021
......@@ -62,7 +62,7 @@ architecture rtl of immed_pulse_counter is
-- Signal for synchronization (in fact they are not so necessary for current system...)
signal pulse_start_d0, pulse_start_d1, pulse_start_d2, pulse_start_d3 : std_logic;
signal nozerolength : boolean;
signal nozerolength, nozerolength_aux : boolean;
-- Aux
constant zeros : std_logic_vector(pulse_length_width-1 downto 0) := (others=>'0');
......@@ -83,8 +83,9 @@ begin -- architecture rtl
pulse_start_d1<=pulse_start_d0;
pulse_start_d2<=pulse_start_d1;
pulse_start_d3<=pulse_start_d2;
nozerolength_aux<=pulse_length_i/=zeros;
if (pulse_start_d2='1' and pulse_start_d1='0') then
nozerolength<=pulse_length_i/=zeros;
nozerolength<=nozerolength_aux;
end if;
end if;
end process;
......
modules/wrsw_nic/Manifest.py deleted 100644 → 0
View file @ a216d4a9
files = [ "nic_constants_pkg.vhd" ,
"nic_descriptors_pkg.vhd" ,
"nic_wishbone_slave.vhd" ,
"nic_descriptor_manager.vhd" ,
"nic_rx_fsm.vhd" ,
"nic_tx_fsm.vhd" ,
"nic_buffer.vhd" ,
"nic_elastic_buffer.vhd",
"nic_wbgen2_pkg.vhd",
"xwrsw_nic.vhd",
"wrsw_nic.vhd"];
modules/wrsw_nic/build_wb.sh deleted 100755 → 0
View file @ a216d4a9
#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/wrsw_nic.html -V nic_wishbone_slave.vhd --cstyle defines --lang vhdl -K ../../sim/regs/nic_regs.vh -p nic_wbgen2_pkg.vhd --hstyle record wr_nic.wb
modules/wrsw_nic/nic_buffer.vhd deleted 100644 → 0
View file @ a216d4a9
-------------------------------------------------------------------------------
-- Title : Mini Embedded DMA Network Interface Controller
-- Project : WhiteRabbit Core
-------------------------------------------------------------------------------
-- File : nic_buffer.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-07-26
-- Last update: 2011-03-15
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description: RAM-based packet buffer for the NIC
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-07-26 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.genram_pkg.all;
entity nic_buffer is
generic (
g_memsize_log2 : integer := 14);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
addr_i : in std_logic_vector(g_memsize_log2-1 downto 0);
data_i : in std_logic_vector(31 downto 0);
wr_i : in std_logic;
data_o : out std_logic_vector(31 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_addr_i : in std_logic_vector(g_memsize_log2-1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic
);
end nic_buffer;
architecture syn of nic_buffer is
signal host_we : std_logic;
signal host_ack : std_logic;
begin -- syn
ack_gen : process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
host_ack <= '0';
else
host_ack <= (wb_cyc_i and wb_stb_i) and (not host_ack);
end if;
end if;
end process;
wb_ack_o <= host_ack;
host_we <= wb_cyc_i and wb_stb_i and (wb_we_i and not host_ack);
RAM : generic_dpram
generic map (
g_data_width => 32,
g_size => 2**g_memsize_log2,
g_dual_clock => false)
port map (
-- host port
rst_n_i => rst_n_i,
clka_i => clk_sys_i,
clkb_i => clk_sys_i,
wea_i => host_we,
bwea_i => x"0",
aa_i => wb_addr_i,
da_i => wb_data_i,
qa_o => wb_data_o,
web_i => wr_i,
bweb_i => x"f",
ab_i => addr_i,
db_i => data_i,
qb_o => data_o);
end syn;
modules/wrsw_nic/nic_constants_pkg.vhd deleted 100644 → 0
View file @ a216d4a9
-------------------------------------------------------------------------------
-- Title : WR NIC - constants package
-- Project : WhiteRabbit Switch
-------------------------------------------------------------------------------
-- File : nic_constants_pkg.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-24
-- Last update: 2010-11-27
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description: Package with global NIC constants
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-24 1.0 twlostow Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package nic_constants_pkg is
-- number of TX descriptors. Must be a power of 2.
constant c_nic_num_tx_descriptors : integer := 8;
-- log2(c_nic_num_tx_descriptors)
constant c_nic_num_tx_descriptors_log2 : integer := 3;
-- number of RX descriptors. Must be a power of 2.
constant c_nic_num_rx_descriptors : integer := 8;
-- log2(c_nic_num_rx_descriptors)
constant c_nic_num_rx_descriptors_log2 : integer := 3;
-- endianess of the packet buffer
constant c_nic_buf_little_endian : boolean := true;
-- log2(size of the packet buffer)
constant c_nic_buf_size_log2 : integer := 15;
end package nic_constants_pkg;
modules/wrsw_nic/nic_descriptor_manager.vhd deleted 100644 → 0
View file @ a216d4a9
-------------------------------------------------------------------------------
-- Title : WR NIC - RX descriptor management unit
-- Project : WhiteRabbit Switch
-------------------------------------------------------------------------------
-- File : nic_descriptor_manager.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-24
-- Last update: 2012-01-13
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-24 1.0 twlostow Created
-- 2010-11-27 1.0 twlostow Unified RX and TX descriptor mgmt
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
library work;
use work.nic_constants_pkg.all;
use work.nic_descriptors_pkg.all;
entity nic_descriptor_manager is
generic (
g_desc_mode : string := "tx";
g_num_descriptors : integer;
g_num_descriptors_log2 : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
enable_i : in std_logic;
bna_o : out std_logic;
bna_clear_i : in std_logic;
cur_desc_idx_o : out std_logic_vector(g_num_descriptors_log2-1 downto 0);
-------------------------------------------------------------------------------
-- Descriptor RAM interface
-------------------------------------------------------------------------------
dtbl_addr_o : out std_logic_vector(g_num_descriptors_log2+1 downto 0);
dtbl_data_i : in std_logic_vector(31 downto 0);
dtbl_rd_o : out std_logic;
dtbl_data_o : out std_logic_vector(31 downto 0);
dtbl_wr_o : out std_logic;
-------------------------------------------------------------------------------
-- RX/TX FSM Interface
-------------------------------------------------------------------------------
desc_reload_current_i : in std_logic;
desc_request_next_i : in std_logic;
desc_grant_o : out std_logic;
rxdesc_current_o : out t_rx_descriptor;
rxdesc_new_i : in t_rx_descriptor;
txdesc_current_o : out t_tx_descriptor;
txdesc_new_i : in t_tx_descriptor;
desc_write_i : in std_logic;
desc_write_done_o : out std_logic
);
end nic_descriptor_manager;
architecture behavioral of nic_descriptor_manager is
type t_desc_arb_state is (ARB_DISABLED, ARB_START_SCAN, ARB_CHECK_EMPTY, ARB_FETCH, ARB_GRANT, ARB_UPDATE, ARB_WRITE_DESC);
signal state : t_desc_arb_state;
signal granted_desc_tx : t_tx_descriptor;
signal granted_desc_rx : t_rx_descriptor;
signal granted_desc_idx : unsigned(g_num_descriptors_log2-1 downto 0);
signal desc_idx_d0 : unsigned(g_num_descriptors_log2-1 downto 0);
signal desc_idx : unsigned(g_num_descriptors_log2-1 downto 0);
signal desc_subreg : unsigned(1 downto 0);
signal cntr : unsigned(1 downto 0);
signal check_count : unsigned(g_num_descriptors_log2 downto 0);
signal stupid_hack : std_logic;
impure function f_write_marshalling(index : integer)
return std_logic_vector is
begin
if(g_desc_mode = "rx") then
return f_marshall_rx_descriptor(granted_desc_rx, index);
elsif (g_desc_mode = "tx") then
return f_marshall_tx_descriptor(granted_desc_tx, index);
end if;
end function;
begin -- behavioral
dtbl_addr_o <= std_logic_vector(desc_idx & desc_subreg);
dtbl_rd_o <= '1';
cur_desc_idx_o <= std_logic_vector(desc_idx);
p_rxdesc_arbiter : process(clk_sys_i, rst_n_i)
variable tmp_desc_rx : t_rx_descriptor;
variable tmp_desc_tx : t_tx_descriptor;
-- variable l:line ;
begin
if rising_edge(clk_sys_i) then
if(rst_n_i = '0') then
desc_write_done_o <= '0';
desc_grant_o <= '0';
state <= ARB_DISABLED;
desc_idx <= (others => '0');
desc_subreg <= (others => '0');
dtbl_wr_o <= '0';
-- dtbl_rd_o <= '0';
dtbl_data_o <= (others => '0');
else
case state is
when ARB_DISABLED =>
desc_idx <= (others => '0');
desc_subreg <= (others => '0');
if(enable_i = '1') then
-- dtbl_rd_o <= '1';
state <= ARB_START_SCAN;
desc_idx <= (others => '0');
check_count <= (others => '0');
end if;
when ARB_START_SCAN =>
if(enable_i = '0') then
state <= ARB_DISABLED;
else
-- wait until the current descriptor is read from the memorry
state <= ARB_CHECK_EMPTY;
-- dtbl_rd_o <='1';
dtbl_wr_o <= '0';
end if;
when ARB_CHECK_EMPTY =>
p_unmarshall_rx_descriptor(dtbl_data_i, 1, tmp_desc_rx);
p_unmarshall_tx_descriptor(dtbl_data_i, 1, tmp_desc_tx);
if((tmp_desc_rx.empty = '1' and g_desc_mode = "rx") or (tmp_desc_tx.ready = '1' and g_desc_mode = "tx")) then
granted_desc_tx <= tmp_desc_tx;
granted_desc_rx <= tmp_desc_rx;
desc_subreg <= "01";
state <= ARB_FETCH;
bna_o <= '0';
else
bna_o <= '1';
end if;
when ARB_FETCH =>
case desc_subreg is
when "10" => -- ignore the timestamps for RX
-- descriptors (they're
-- write-only by the NIC)
p_unmarshall_tx_descriptor(dtbl_data_i, 2, tmp_desc_tx);
granted_desc_tx.len <= tmp_desc_tx.len;
granted_desc_tx.offset <= tmp_desc_tx.offset;
when "11" =>
p_unmarshall_tx_descriptor(dtbl_data_i, 3, tmp_desc_tx); -- TX
granted_desc_tx.dpm <= tmp_desc_tx.dpm;
p_unmarshall_rx_descriptor(dtbl_data_i, 3, tmp_desc_rx); -- RX
granted_desc_rx.len <= tmp_desc_rx.len;
granted_desc_rx.offset <= tmp_desc_rx.offset;
state <= ARB_GRANT;
when others => null;
end case;
desc_subreg <= desc_subreg + 1;
when ARB_GRANT =>
if(desc_request_next_i = '1') then
desc_grant_o <= '1';
if(g_desc_mode = "tx") then
txdesc_current_o <= granted_desc_tx;
elsif (g_desc_mode = "rx") then
rxdesc_current_o <= granted_desc_rx;
end if;
state <= ARB_UPDATE;
end if;
desc_write_done_o <= '0';
when ARB_UPDATE =>
desc_grant_o <= '0';
if(desc_write_i = '1') then
if(g_desc_mode = "rx") then
granted_desc_rx <= rxdesc_new_i;
elsif(g_desc_mode = "tx") then
granted_desc_tx <= txdesc_new_i;
end if;
desc_subreg <= (others => '0');
-- dtbl_rd_o <= '0';
state <= ARB_WRITE_DESC;
cntr <= "00";
end if;
when ARB_WRITE_DESC =>
cntr <= cntr + 1;
-- fprint(output,l, "WriteDesc %b %b\n",fo(cntr),fo(f_write_marshalling(1)));
case cntr is
when "00" =>
desc_subreg <= "00";
dtbl_data_o <= f_write_marshalling(1);
dtbl_wr_o <= '1';
when "01" =>
desc_subreg <= "01";
dtbl_data_o <= f_write_marshalling(2);
dtbl_wr_o <= '1';
when "10" =>
desc_subreg <= "10";
dtbl_data_o <= f_write_marshalling(3);
dtbl_wr_o <= '1';
when "11" =>
dtbl_wr_o <= '0';
desc_subreg <= (others => '0');
state <= ARB_START_SCAN;
if(desc_reload_current_i = '0') then
desc_idx <= desc_idx + 1;
end if;
desc_write_done_o <= '1';
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end process;
end behavioral;
modules/wrsw_nic/nic_descriptors_pkg.vhd deleted 100644 → 0
View file @ a216d4a9
-------------------------------------------------------------------------------
-- Title : WR NIC - descriptors package
-- Project : WhiteRabbit Switch
-------------------------------------------------------------------------------
-- File : nic_descriptors_pkg.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-24
-- Last update: 2012-03-16
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description: Package declares RX/TX descriptor data types and functions for
-- marshalling/unmarshalling the descriptors to/from SLVs
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-24 1.0 twlostow Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.nic_constants_pkg.all;
package nic_descriptors_pkg is
type t_tx_descriptor is record
ts_id : std_logic_vector(15 downto 0); -- OOB frame id (for TX timestamping)
pad_e : std_logic; -- padding enable
ts_e : std_logic; -- timestamp enable
error : std_logic; -- TX error indication
ready : std_logic; -- Descriptor ready for transmission flag
len : std_logic_vector(c_nic_buf_size_log2-1 downto 0); -- Length of the packet
offset : std_logic_vector(c_nic_buf_size_log2-1 downto 0); -- Offset of the packet in the buffer
dpm : std_logic_vector(31 downto 0); -- Destination port mask
end record;
type t_rx_descriptor is record
empty : std_logic; -- Descriptor empty (ready for
-- reception) flag
error : std_logic; -- RX error indication
port_id : std_logic_vector(5 downto 0); -- Packet source port ID
got_ts : std_logic; -- Got a timestamp?
ts_incorrect: std_logic; -- 1: Timestamp may be incorrect (generated
-- during time base adjustment)
ts_r : std_logic_vector(27 downto 0); -- Rising edge timestamp
ts_f : std_logic_vector(3 downto 0); -- Falling edge timestamp
len : std_logic_vector(c_nic_buf_size_log2-1 downto 0); -- Length of the allocated buffer
-- (or length of the received
-- packet when the desc is not empty)
offset : std_logic_vector(c_nic_buf_size_log2-1 downto 0); -- Address of the buffer;
end record;
function f_marshall_tx_descriptor(desc : t_tx_descriptor;
regnum : integer) return std_logic_vector;
function f_marshall_rx_descriptor(desc : t_rx_descriptor;
regnum : integer) return std_logic_vector;
procedure p_unmarshall_tx_descriptor(mem_input : in std_logic_vector(31 downto 0);
regnum : in integer;
desc : inout t_tx_descriptor);
procedure p_unmarshall_rx_descriptor(mem_input : in std_logic_vector(31 downto 0);
regnum : in integer;
desc : inout t_rx_descriptor);
function f_resize_slv(x : std_logic_vector;
newsize : integer) return std_logic_vector;
end NIC_descriptors_pkg;
package body NIC_descriptors_pkg is
function f_resize_slv(x : std_logic_vector; newsize : integer) return std_logic_vector is
variable tmp:std_logic_vector(newsize-1 downto 0);
begin
tmp(x'length-1 downto 0) := x;
tmp(newsize-1 downto x'length) := (others => '0');
return tmp;
end f_resize_slv;
function f_marshall_tx_descriptor(desc : t_tx_descriptor; regnum : integer) return std_logic_vector is
variable tmp : std_logic_vector(31 downto 0);
begin
case regnum is
when 1 => tmp := desc.ts_id & x"000" & desc.pad_e & desc.ts_e & desc.error & desc.ready;
when 2 => tmp := f_resize_slv(desc.len, 16) & f_resize_slv(desc.offset, 16);
when 3 => tmp := desc.dpm;
when others => null;
end case;
return tmp;
end f_marshall_tx_descriptor;
function f_marshall_rx_descriptor(desc : t_rx_descriptor; regnum : integer) return std_logic_vector is
variable tmp : std_logic_vector(31 downto 0);
begin
case regnum is
when 1 => tmp := "0000000000000000" & desc.ts_incorrect & desc.got_ts & desc.port_id & "000000" & desc.error & desc.empty;
when 2 => tmp := desc.ts_f & desc.ts_r;
when 3 => tmp := f_resize_slv(desc.len, 16) & f_resize_slv(desc.offset, 16);
when others => null;
end case;
return tmp;
end f_marshall_rx_descriptor;
procedure p_unmarshall_tx_descriptor(mem_input : in std_logic_vector(31 downto 0);
regnum : in integer;
desc : inout t_tx_descriptor) is
begin
case regnum is
when 1 =>
desc.ts_id := mem_input(31 downto 16);
desc.pad_e := mem_input(3);
desc.ts_e := mem_input(2);
desc.error := mem_input(1);
desc.ready := mem_input(0);
when 2 =>
desc.len := mem_input(16+c_nic_buf_size_log2-1 downto 16);
desc.offset := mem_input(c_nic_buf_size_log2-1 downto 0);
when 3 =>
desc.dpm := mem_input;
when others => null;
end case;
end p_unmarshall_tx_descriptor;
procedure p_unmarshall_rx_descriptor(mem_input : in std_logic_vector(31 downto 0);
regnum : in integer;
desc : inout t_rx_descriptor) is
begin
case regnum is
when 1 =>
desc.empty := mem_input(0);
desc.error := mem_input(1);
desc.port_id := mem_input(13 downto 8);
desc.got_ts := mem_input(14);
desc.ts_incorrect := mem_input(15);
when 2 =>
desc.ts_f := mem_input(31 downto 28);
desc.ts_r := mem_input(27 downto 0);
when 3 =>
desc.len := mem_input(16+c_nic_buf_size_log2-1 downto 16);
desc.offset := mem_input(c_nic_buf_size_log2-1 downto 0);
when others => null;
end case;
end p_unmarshall_rx_descriptor;
end package body;
modules/wrsw_nic/nic_elastic_buffer.vhd deleted 100644 → 0
View file @ a216d4a9
library ieee;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
library work;
use work.endpoint_private_pkg.all; -- dirty hack, again
use work.genram_pkg.all;
use work.wr_fabric_pkg.all;
entity nic_elastic_buffer is
generic (
g_depth : integer := 64);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
fab_o : out t_ep_internal_fabric;
dreq_i : in std_logic
);
end nic_elastic_buffer;
architecture rtl of nic_elastic_buffer is
function log2 (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 32 bits
if (2**I > A) then
return(I-1);
end if;
end loop;
return(63);
end function log2;
constant c_fifo_width : integer := 16 + 2 + 5;
signal fifo_write : std_logic;
signal fifo_read : std_logic;
signal fifo_in_ser : std_logic_vector(c_fifo_width-1 downto 0);
signal fifo_out_ser : std_logic_vector(c_fifo_width-1 downto 0);
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_usedw : std_logic_vector(log2(g_depth)-1 downto 0);
signal output_valid : std_logic;
signal got_empty : std_logic;
signal cyc_d0 : std_logic;
signal fifo_in : t_ep_internal_fabric;
signal fifo_out : t_ep_internal_fabric;
signal snk_out : t_wrf_sink_out;
signal stall_int : std_logic;
begin -- rtl
p_delay_cyc : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
cyc_d0 <= '0';
else
cyc_d0 <= snk_i.cyc;
end if;
end if;
end process;
snk_o <= snk_out;
snk_out.err <= fifo_full and snk_i.cyc and snk_i.stb;
snk_out.rty <= '0';
p_gen_ack : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
snk_out.ack <= '0';
else
snk_out.ack <= snk_i.cyc and snk_i.stb and not snk_out.stall;
end if;
end if;
end process;
fifo_in.sof <= not cyc_d0 and snk_i.cyc;
fifo_in.eof <= cyc_d0 and not snk_i.cyc;
fifo_in.data <= snk_i.dat;
fifo_in.dvalid <= snk_i.stb and snk_i.cyc and not snk_out.stall;
fifo_in.addr <= snk_i.adr;
fifo_in.error <= '1' when (fifo_in.dvalid = '1') and
snk_i.adr = c_WRF_STATUS and
(f_unmarshall_wrf_status(snk_i.dat).error = '1') else '0';
fifo_in.bytesel <= not snk_i.sel(0);
fifo_write <= fifo_in.sof or fifo_in.eof or fifo_in.dvalid or fifo_in.error;
fifo_in_ser <= fifo_in.bytesel & fifo_in.sof & fifo_in.eof & fifo_in.dvalid & fifo_in.error & fifo_in.addr & fifo_in.data;
p_gen_stall : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
stall_int <= '0';
else
if (unsigned(fifo_usedw) < g_depth/2) then
stall_int <= '0';
elsif (unsigned(fifo_usedw) > g_depth-5) then
stall_int <= '1';
end if;
end if;
end if;
end process;
snk_out.stall <= fifo_in.sof or stall_int;
fifo_read <= not fifo_empty and dreq_i;
p_gen_valid_flag : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
output_valid <= '0';
else
output_valid <= fifo_read;
end if;
end if;
end process;
U_fifo : generic_sync_fifo
generic map (
g_data_width => c_fifo_width,
g_size => g_depth,
g_with_count => true)
port map (
rst_n_i => rst_n_i,
clk_i => clk_sys_i,
we_i => fifo_write,
d_i => fifo_in_ser,
rd_i => fifo_read,
q_o => fifo_out_ser,
empty_o => fifo_empty,
full_o => fifo_full,
count_o => fifo_usedw
);
fab_o.data <= fifo_out_ser(15 downto 0);
fab_o.addr <= fifo_out_ser(17 downto 16);
fab_o.error <= fifo_out_ser(18) and output_valid;
fab_o.dvalid <= fifo_out_ser(19) and output_valid;
fab_o.eof <= fifo_out_ser(20) and output_valid;
fab_o.sof <= fifo_out_ser(21) and output_valid;
fab_o.bytesel <= fifo_out_ser(22);
end rtl;
modules/wrsw_nic/nic_rx_fsm.vhd deleted 100644 → 0
View file @ a216d4a9
-------------------------------------------------------------------------------
-- Title : WRF Interface reception logic for WR NIC
-- Project : WhiteRabbit Switch
-------------------------------------------------------------------------------
-- File : nic_rx_fsm.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-24
-- Last update: 2012-03-16
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description: The NIC receive path state machine. Takes the packets coming to
-- the WRF sink, requests RX descriptors from RX descriptor manager and writes
-- the packet data and OOB into at specified addresses in the buffer.
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-24 1.0 twlostow Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.nic_constants_pkg.all;
use work.nic_descriptors_pkg.all;
use work.wr_fabric_pkg.all;
use work.nic_wbgen2_pkg.all;
use work.endpoint_private_pkg.all;
entity nic_rx_fsm is
port (clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-------------------------------------------------------------------------------
-- WRF sink
-------------------------------------------------------------------------------
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
-------------------------------------------------------------------------------
-- Wishbone regs
-------------------------------------------------------------------------------
bna_i : in std_logic;
regs_i : in t_nic_out_registers;
regs_o : out t_nic_in_registers;
irq_rcomp_o : out std_logic;
irq_rcomp_ack_i : in std_logic;
-------------------------------------------------------------------------------
-- RX Descriptor Manager I/F
-------------------------------------------------------------------------------
-- 1 requests next available (empty) RX descriptor
rxdesc_request_next_o : out std_logic;
-- 1 indicates that an empty descriptor has been granted and it's available
-- on rxdesc_current_i
rxdesc_grant_i : in std_logic;
-- currently granted RX descriptor
rxdesc_current_i : in t_rx_descriptor;
-- updated RX descriptor (with new length, error flags, timestamp, etc.)
rxdesc_new_o : out t_rx_descriptor;
-- 1 requests an update of the current RX descriptor with the values
-- given on rxdesc_new_o output
rxdesc_write_o : out std_logic;
-- 1 indicates that the RX descriptor update is done
rxdesc_write_done_i : in std_logic;
-------------------------------------------------------------------------------
-- Packet buffer RAM
-------------------------------------------------------------------------------
-- 1 indicates that we'll have the memory access in the following clock
-- cycle
buf_grant_i : in std_logic;
-- buffer address, data and write enable lines.
buf_addr_o : out std_logic_vector(c_nic_buf_size_log2-3 downto 0);
buf_wr_o : out std_logic;
buf_data_o : out std_logic_vector(31 downto 0)
);
end nic_rx_fsm;
architecture behavioral of NIC_RX_FSM is
component nic_elastic_buffer
generic (
g_depth : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
fab_o : out t_ep_internal_fabric;
dreq_i : in std_logic);
end component;
type t_rx_fsm_state is (RX_DISABLED, RX_WAIT_SOF, RX_REQUEST_DESCRIPTOR, RX_DATA, RX_UPDATE_DESC, RX_MEM_RESYNC, RX_MEM_FLUSH);
signal cur_rx_desc : t_rx_descriptor;
signal state : t_rx_fsm_state;
signal rx_avail : unsigned(c_nic_buf_size_log2-1 downto 0);
signal rx_length : unsigned(c_nic_buf_size_log2-1 downto 0);
signal rx_dreq_mask : std_logic;
signal rx_rdreg_toggle : std_logic;
signal rx_buf_addr : unsigned(c_nic_buf_size_log2-3 downto 0);
signal rx_buf_data : std_logic_vector(31 downto 0);
signal rx_is_payload : std_logic;
signal rx_newpacket : std_logic;
signal rx_newpacket_d0 : std_logic;
signal wrf_is_payload : std_logic;
signal wrf_terminate : std_logic;
signal wrf_is_oob : std_logic;
signal oob_sreg : std_logic_vector(2 downto 0);
signal increase_addr : std_logic;
signal fab_in : t_ep_internal_fabric;
signal fab_dreq : std_logic;
begin
U_Buffer : nic_elastic_buffer
generic map (
g_depth => 64)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
snk_i => snk_i,
snk_o => snk_o,
fab_o => fab_in,
dreq_i => fab_dreq);
-- stupid VHDL type conversions
buf_addr_o <= std_logic_vector(rx_buf_addr);
buf_data_o <= rx_buf_data; -- so we can avoid "buffer" I/Os
rxdesc_new_o <= cur_rx_desc;
-- some combinatorial helpers to minimize conditions in IFs.
wrf_is_payload <= '1' when (fab_in.addr = c_WRF_DATA) else '0';
wrf_is_oob <= '1' when (fab_in.addr = c_WRF_OOB) else '0';
wrf_terminate <= '1' when (fab_in.eof = '1' or fab_in.error = '1') else '0';
-- process produces the RCOMP interrupt each time a packet has been received
p_handle_rx_interrupt : process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
irq_rcomp_o <= '0';
rx_newpacket_d0 <= '0';
else
rx_newpacket_d0 <= rx_newpacket;
-- we've got another packet? Trigger the IRQ
if (rx_newpacket_d0 = '0' and rx_newpacket = '1') then
irq_rcomp_o <= '1';
-- host acked the interrupt?
elsif (irq_rcomp_ack_i = '1') then
irq_rcomp_o <= '0';
end if;
end if;
end if;
end process;
-- process produces the REC field in SR register
p_handle_status_rec : process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
regs_o.sr_rec_i <= '0';
else
-- we've got a packet? Set REC to 1
if (rx_newpacket_d0 = '0' and rx_newpacket = '1') then
regs_o.sr_rec_i <= '1';
-- host wrote 1 to REC bit? Clear!
elsif (regs_i.sr_rec_o = '1' and regs_i.sr_rec_load_o = '1') then
regs_o.sr_rec_i <= '0';
end if;
end if;
end if;
end process;
-- the big beast
p_main_fsm : process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
state <= RX_DISABLED;
rxdesc_request_next_o <= '0';
rxdesc_write_o <= '0';
rx_newpacket <= '0';
rx_dreq_mask <= '0';
rx_buf_addr <= (others => '0');
rx_avail <= (others => '0');
buf_wr_o <= '0';
increase_addr <= '0';
else
case state is
-------------------------------------------------------------------------------
-- State DISABLED: packet reception is OFF, all incoming traffic is dropped
-------------------------------------------------------------------------------
when RX_DISABLED =>
rxdesc_request_next_o <= '0';
rx_rdreg_toggle <= '0';
if(regs_i.cr_rx_en_o = '1') then -- check if the user has re-enabled
-- the reception
state <= RX_REQUEST_DESCRIPTOR;
rx_dreq_mask <= '0';
else
rx_dreq_mask <= '1'; -- enable RX, but everything goes to
-- /dev/null
end if;
-------------------------------------------------------------------------------
-- State REQUEST_DESCRIPTOR: take a next empty RX descriptor and have it ready
-- for the incoming packet
-------------------------------------------------------------------------------
when RX_REQUEST_DESCRIPTOR =>
rxdesc_request_next_o <= '1'; -- tell the RX desc manager that we
-- need a descriptor
if(rxdesc_grant_i = '1') then -- RX manager assigned us a desc?
cur_rx_desc <= rxdesc_current_i; -- save a local copy
rxdesc_request_next_o <= '0';
rx_dreq_mask <= '1'; -- enable packet flow on WRF
state <= RX_WAIT_SOF; -- and start waiting for
-- incoming traffic
else
rx_dreq_mask <= bna_i; -- enable RX (but to /dev/null)
end if;
-------------------------------------------------------------------------------
-- State WAIT_SOF: Wait for incoming packets and initiate the reception
-------------------------------------------------------------------------------
when RX_WAIT_SOF =>
-- this guy controls the memory write order. As the fabric is 16-bit and
-- the memory is 32-bit wide, we have to write the data to the buffer
-- with every two received words. The data is committed to the mem
-- when rx_rdreg_toggle = 1, so if we initialize it to 1 before
-- receiving the frame, we'll get a 2-byte gap at the beginning of
-- the buffer (cheers, Alessandro :)
rx_rdreg_toggle <= '1';
-- rx_buf_addr is in 32-bit word, but the offsets and lengths in
-- the descriptors are in bytes to make driver developer's life
-- easier.
rx_buf_addr <= unsigned(cur_rx_desc.offset(c_nic_buf_size_log2-1 downto 2));
rx_avail <= unsigned(cur_rx_desc.len);
rx_length <= (others => '0');
oob_sreg <= "001";
rx_newpacket <= '0';
if(fab_in.sof = '1') then -- got a packet on WRF sink?
state <= RX_DATA; -- then start receiving it!
end if;
-------------------------------------------------------------------------------
-- State RX_DATA: enormously big, messy and complicated data reception logic.
-- Does everything needed to put the received packet into the right place in
-- the buffer
-------------------------------------------------------------------------------
when RX_DATA =>
-- increase the address 1 cycle after committing the data to the memory
if(increase_addr = '1') then
rx_buf_addr <= rx_buf_addr + 1;
increase_addr <= '0';
end if;
-- check if we still have enough space in the buffer
if(fab_in.dvalid = '1' and rx_avail(rx_avail'length-1 downto 1) = to_unsigned(0, rx_avail'length-1)) then
-- no space? drop an error
cur_rx_desc.error <= '1';
buf_wr_o <= '0';
state <= RX_UPDATE_DESC;
end if;
-- got an abort/error/end-of-frame?
if(wrf_terminate = '1') then
-- check if the ends with an error and eventually indicate it.
-- For the NIC, there's no difference between an abort and an RX
-- error.
cur_rx_desc.error <= fab_in.error;
-- make sure the remaining packet data is written into the buffer
state <= RX_MEM_FLUSH;
-- disable the WRF sink data flow, so we won't get another
-- packet before we are done with the memory flush and RX descriptor update
rx_dreq_mask <= '0';
end if;
-- got a valid payload word?
if(fab_in.dvalid = '1' and wrf_is_payload = '1') then
-- check if it's a byte or a word transfer and update the length
-- and buffer space counters accordingly
if(fab_in.bytesel = '1') then
rx_avail <= rx_avail - 1;
rx_length <= rx_length + 1;
else
rx_avail <= rx_avail - 2;
rx_length <= rx_length + 2;
end if;
-- pack two 16-bit words received from the fabric I/F into one
-- 32-bit buffer word
if(c_nic_buf_little_endian = false) then
-- CPU is big-endian
if(rx_rdreg_toggle = '0') then
-- 1st word
rx_buf_data(31 downto 16) <= fab_in.data;
else
-- 2nd word
rx_buf_data(15 downto 0) <= fab_in.data;
end if;
else
-- CPU is little endian
if(rx_rdreg_toggle = '0') then
-- 1st word
rx_buf_data(15 downto 8) <= fab_in.data(7 downto 0);
rx_buf_data(7 downto 0) <= fab_in.data(15 downto 8);
else
-- 2nd word
rx_buf_data(31 downto 24) <= fab_in.data(7 downto 0);
rx_buf_data(23 downto 16) <= fab_in.data(15 downto 8);
end if;
end if;
-- toggle the current word
rx_rdreg_toggle <= not rx_rdreg_toggle;
end if;
-- got a valid OOB word?
if(fab_in.dvalid = '1' and wrf_is_oob = '1') then
-- oob_sreg is a shift register, where each bit represents one of
-- 3 RX OOB words
oob_sreg <= oob_sreg(oob_sreg'length-2 downto 0) & '0';
-- check which word we've just received and put its contents into
-- the descriptor
if(oob_sreg (0) = '1') then -- 1st OOB word
cur_rx_desc.port_id <= '0' & fab_in.data(4 downto 0);
cur_rx_desc.ts_incorrect <= fab_in.data(11);
end if;
if(oob_sreg (1) = '1') then -- 2nd OOB word
cur_rx_desc.ts_f <= fab_in.data(15 downto 12);
cur_rx_desc.ts_r (27 downto 16) <= fab_in.data(11 downto 0);
end if;
if(oob_sreg (2) = '1') then -- 3rd OOB word
cur_rx_desc.ts_r(15 downto 0) <= fab_in.data;
cur_rx_desc.got_ts <= '1';
end if;
end if;
-- we've got 2 valid word of the payload in rx_buf_data, write them to the
-- memory
if(rx_rdreg_toggle = '1' and fab_in.dvalid = '1' and (wrf_is_oob = '1' or wrf_is_payload = '1') and wrf_terminate = '0') then
increase_addr <= '1';
buf_wr_o <= '1';
-- check if we are synchronized with the memory write arbiter,
-- which grants us the memory acces every 2 clock cycles.
-- If we're out of the "beat" (for example when the RX traffic
-- was throttled by the WRF source), we need to resynchronize ourselves.
if(buf_grant_i = '1') then
state <= RX_MEM_RESYNC;
end if;
else
-- nothing to write
buf_wr_o <= '0';
end if;
-------------------------------------------------------------------------------
-- State "Memory resync": a "wait state" entered when the NIC tries to write the RX
-- payload, but the memory access is given for the TX path at the moment.
-------------------------------------------------------------------------------
when RX_MEM_RESYNC =>
-- check for error/abort conditions, they may appear even when
-- the fabric is not accepting the data (tx_dreq_o = 0)
if(fab_in.error = '1') then
cur_rx_desc.error <= '1';
state <= RX_MEM_FLUSH;
rx_dreq_mask <= '0';
else
state <= RX_DATA;
end if;
-------------------------------------------------------------------------------
-- State "Memory flush": flushes the remaining contents of RX data register
-- into the packet buffer after end-of-packet/error/abort
-------------------------------------------------------------------------------
when RX_MEM_FLUSH =>
buf_wr_o <= '1';
-- make sure the data has been written
if(buf_grant_i = '0') then
state <= RX_UPDATE_DESC;
end if;
-------------------------------------------------------------------------------
-- State "Update Descriptor": writes new length, timestamps, port ID, flags and
-- marks the descriptor as non-empty.
-------------------------------------------------------------------------------
when RX_UPDATE_DESC =>
buf_wr_o <= '0';
cur_rx_desc.len <= std_logic_vector(rx_length);
cur_rx_desc.empty <= '0';
rxdesc_write_o <= '1'; -- request descriptor update
-- update done?
if(rxdesc_write_done_i = '1') then
rxdesc_write_o <= '0';
rx_newpacket <= '1';
-- check the RX_EN bit and eventually disable the reception.
-- we can do that only here (disabling RX in the middle of
-- received packet can corrupt the descriptor table).
if(regs_i.cr_rx_en_o = '0') then
state <= RX_DISABLED;
else
-- we're done - prepare another descriptor for the next
-- incoming packet
state <= RX_REQUEST_DESCRIPTOR;
end if;
end if;
when others => null;
end case;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- helper process for producing the RX fabric data request signal (combinatorial)
-------------------------------------------------------------------------------
gen_rx_dreq : process(rx_dreq_mask, buf_grant_i, rx_rdreg_toggle, fab_in, regs_i)
begin
-- make sure we don't have any incoming data when the reception is masked (e.g.
-- the NIC is updating the descriptors of finishing the memory write.
if(regs_i.cr_rx_en_o = '0' and state = RX_DISABLED) then
fab_dreq <= '1'; -- /dev/null
elsif(fab_in.eof = '1' or fab_in.sof = '1' or rx_dreq_mask = '0') then
fab_dreq <= '0';
-- the condition below forces the RX FSM to go into RX_MEM_RESYNC state. Don't
-- receive anything during the RESYNC cycle.
elsif(rx_rdreg_toggle = '1' and buf_grant_i = '1' and (state /= RX_WAIT_SOF) and (state /= RX_REQUEST_DESCRIPTOR)) then
fab_dreq <= '0';
else
fab_dreq <= '1';
end if;
end process;
end architecture;
modules/wrsw_nic/nic_tx_fsm.vhd deleted 100644 → 0
View file @ a216d4a9
-------------------------------------------------------------------------------
-- Title : WRF Interface transmission logic for WR NIC
-- Project : WhiteRabbit Switch
-------------------------------------------------------------------------------
-- File : nic_tx_fsm.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-24
-- Last update: 2012-01-24
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description: The NIC transmit FSM
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-24 1.0 twlostow Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.nic_constants_pkg.all;
use work.nic_descriptors_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_private_pkg.all; -- dirty hack
use work.nic_wbgen2_pkg.all;
entity nic_tx_fsm is
port (clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-------------------------------------------------------------------------------
-- WRF source
-------------------------------------------------------------------------------
src_o : out t_wrf_source_out;
src_i : in t_wrf_source_in;
-------------------------------------------------------------------------------
-- "Fake" RTU interface
-------------------------------------------------------------------------------
rtu_dst_port_mask_o : out std_logic_vector(31 downto 0);
rtu_prio_o : out std_logic_vector(2 downto 0);
rtu_drop_o : out std_logic;
rtu_rsp_valid_o : out std_logic;
rtu_rsp_ack_i : in std_logic;
-------------------------------------------------------------------------------
-- Wishbone regs & IRQs
-------------------------------------------------------------------------------
regs_i : in t_nic_out_registers;
regs_o : out t_nic_in_registers;
irq_tcomp_o : out std_logic;
irq_tcomp_ack_i : in std_logic;
irq_tcomp_mask_i : in std_logic;
irq_txerr_o : out std_logic;
irq_txerr_ack_i : in std_logic;
irq_txerr_mask_i : in std_logic;
-------------------------------------------------------------------------------
-- TX Descriptor Manager I/F
-------------------------------------------------------------------------------
txdesc_reload_current_o : out std_logic;
-- 1 requests next available (empty) TX descriptor
txdesc_request_next_o : out std_logic;
-- 1 indicates that an empty descriptor has been granted and it's available
-- on rxdesc_current_i
txdesc_grant_i : in std_logic;
-- currently granted TX descriptor
txdesc_current_i : in t_tx_descriptor;
-- updated RX descriptor (with new length, error flags, timestamp, etc.)
txdesc_new_o : out t_tx_descriptor;
-- 1 requests an update of the current TX descriptor with the values
-- given on rxdesc_new_o output
txdesc_write_o : out std_logic;
-- 1 indicates that the TX descriptor update is done
txdesc_write_done_i : in std_logic;
bna_i : in std_logic;
-------------------------------------------------------------------------------
-- Packet buffer RAM
-------------------------------------------------------------------------------
-- 1 indicates that we'll have the memory access in the following clock
-- cycle
buf_grant_i : in std_logic;
-- buffer address, data and write enable lines.
buf_addr_o : out std_logic_vector(c_nic_buf_size_log2-3 downto 0);
buf_data_i : in std_logic_vector(31 downto 0)
);
end nic_tx_fsm;
architecture behavioral of nic_tx_fsm is
type t_tx_fsm_state is (TX_DISABLED, TX_REQUEST_DESCRIPTOR, TX_MEM_FETCH, TX_START_PACKET, TX_HWORD, TX_LWORD, TX_END_PACKET, TX_OOB1, TX_OOB2, TX_PAD, TX_UPDATE_DESCRIPTOR, TX_ERROR, TX_STATUS);
signal cur_tx_desc : t_tx_descriptor;
component ep_rx_wb_master
generic (
g_ignore_ack : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
snk_fab_i : in t_ep_internal_fabric;
snk_dreq_o : out std_logic;
src_wb_i : in t_wrf_source_in;
src_wb_o : out t_wrf_source_out);
end component;
function f_buf_swap_endian_32
(
data : std_logic_vector(31 downto 0)
) return std_logic_vector is
begin
if(c_nic_buf_little_endian = true) then
return data(7 downto 0) & data(15 downto 8) & data(23 downto 16) & data(31 downto 24);
else
return data;
end if;
end function f_buf_swap_endian_32;
signal state : t_tx_fsm_state;
signal tx_remaining : unsigned(c_nic_buf_size_log2-2 downto 0);
signal odd_length : std_logic;
signal tx_buf_addr : unsigned(c_nic_buf_size_log2-3 downto 0);
signal tx_start_delayed : std_logic;
signal tx_data_reg : std_logic_vector(31 downto 0);
signal tx_done : std_logic;
signal ignore_first_hword : std_logic;
signal tx_cntr_expired : std_logic;
signal is_runt_frame : std_logic;
signal needs_padding : std_logic;
signal padding_size : unsigned(7 downto 0);
signal rtu_valid_int : std_logic;
signal rtu_valid_int_d0 : std_logic;
signal fab_dreq : std_logic;
signal fab_out : t_ep_internal_fabric;
signal tx_err : std_logic;
signal default_status_reg : t_wrf_status_reg;
begin -- behavioral
default_status_reg.has_smac <= '1';
default_status_reg.has_crc <= '0';
default_status_reg.error <= '0';
default_status_reg.is_hp <= '0';
tx_err <= src_i.err or src_i.rty;
buf_addr_o <= std_logic_vector(tx_buf_addr);
is_runt_frame <= '1' when (to_integer(unsigned(cur_tx_desc.len)) < 60) else '0';
tx_cntr_expired <= '1' when (tx_remaining = 0) else '0';
txdesc_new_o <= cur_tx_desc;
U_WB_Master : ep_rx_wb_master
generic map(
g_ignore_ack => true)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
snk_fab_i => fab_out,
snk_dreq_o => fab_dreq,
src_wb_i => src_i,
src_wb_o => src_o);
p_gen_tcomp_irq : process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
irq_tcomp_o <= '0';
else
if(irq_tcomp_ack_i = '1') then
irq_tcomp_o <= '0';
else
if(tx_done = '1' and irq_tcomp_mask_i = '1') then
irq_tcomp_o <= '1';
end if;
end if;
end if;
end if;
end process;
p_gen_sr_tx_done : process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
regs_o.sr_tx_done_i <= '0';
else
if(regs_i.sr_tx_done_load_o = '1' and regs_i.sr_tx_done_o = '1') then
regs_o.sr_tx_done_i <= '0';
else
if(tx_done = '1' and bna_i = '1') then
regs_o.sr_tx_done_i <= '1';
end if;
end if;
end if;
end if;
end process;
p_fsm : process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
state <= TX_DISABLED;
irq_txerr_o <= '0';
txdesc_request_next_o <= '0';
txdesc_write_o <= '0';
txdesc_reload_current_o <= '0';
fab_out.sof <= '0';
fab_out.eof <= '0';
fab_out.dvalid <= '0';
fab_out.bytesel <= '0';
fab_out.data <= (others => '0');
fab_out.addr <= (others => '0');
fab_out.error <= '0';
tx_done <= '0';
rtu_valid_int <= '0';
irq_txerr_o <= '0';
regs_o.sr_tx_error_i <= '0';
rtu_dst_port_mask_o <= (others => '0');
rtu_drop_o <= '0';
else
case state is
when TX_DISABLED =>
regs_o.sr_tx_error_i <= '0';
irq_txerr_o <= '0';
txdesc_request_next_o <= '0';
if(regs_i.cr_tx_en_o = '1') then
state <= TX_REQUEST_DESCRIPTOR;
end if;
when TX_REQUEST_DESCRIPTOR =>
tx_done <= '0';
txdesc_request_next_o <= '1';
if(txdesc_grant_i = '1') then
cur_tx_desc <= txdesc_current_i;
txdesc_request_next_o <= '0';
state <= TX_START_PACKET;
tx_buf_addr <= resize(unsigned(txdesc_current_i.offset(tx_buf_addr'length+1 downto 2)), tx_buf_addr'length);
tx_remaining <= unsigned(txdesc_current_i.len(tx_remaining'length downto 1));
state <= TX_MEM_FETCH;
end if;
-- 1 wait cycle to make sure the 1st TX word has been successfully
-- read from the buffer
when TX_MEM_FETCH =>
if(txdesc_current_i.len(0) = '1') then
tx_remaining <= tx_remaining + 1;
end if;
state <= TX_START_PACKET;
when TX_START_PACKET =>
regs_o.sr_tx_error_i <= '0';
rtu_prio_o <= (others => '0');
rtu_dst_port_mask_o <= cur_tx_desc.dpm;
rtu_drop_o <= '0';
rtu_valid_int <= '1';
-- check if the memory is ready, read the 1st word of the payload
if(fab_dreq = '1' and buf_grant_i = '0') then
tx_data_reg <= buf_data_i;
fab_out.sof <= '1';
tx_buf_addr <= tx_buf_addr + 1;
ignore_first_hword <= '1';
state <= TX_STATUS;
if(is_runt_frame = '1' and cur_tx_desc.pad_e = '1') then
odd_length <= '0';
needs_padding <= '1';
if(cur_tx_desc.len(0) = '1') then
padding_size <= 29 - unsigned(cur_tx_desc.len(padding_size'length downto 1));
else
padding_size <= 30 - unsigned(cur_tx_desc.len(padding_size'length downto 1));
end if;
else
odd_length <= cur_tx_desc.len(0);
needs_padding <= '0';
end if;
tx_data_reg <= f_buf_swap_endian_32(buf_data_i);
end if;
when TX_STATUS =>
fab_out.sof <= '0';
if(fab_dreq = '1' and buf_grant_i = '0') then
fab_out.dvalid <= '1';
fab_out.addr <= c_WRF_STATUS;
fab_out.data <= f_marshall_wrf_status(default_status_reg);
state <= TX_HWORD;
else
fab_out.dvalid <= '0';
end if;
when TX_HWORD =>
rtu_valid_int <= '0';
-- generate the control value depending on the packet type, OOB and the current
-- transmission offset.
fab_out.addr <= c_WRF_DATA;
fab_out.data <= tx_data_reg(31 downto 16);
if(tx_err = '1') then
state <= TX_UPDATE_DESCRIPTOR;
cur_tx_desc.error <= '1';
elsif(fab_dreq = '1') then
if(tx_cntr_expired = '1') then
fab_out.bytesel <= odd_length and (not needs_padding);
if(needs_padding = '1' and padding_size /= 0) then
state <= TX_PAD;
elsif(cur_tx_desc.ts_e = '1') then
state <= TX_OOB1;
else
state <= TX_END_PACKET;
end if;
fab_out.dvalid <= '1';
else
if(ignore_first_hword = '1') then
ignore_first_hword <= '0';
fab_out.dvalid <= '0';
tx_remaining <= tx_remaining - 1;
else
fab_out.dvalid <= '1';
tx_remaining <= tx_remaining - 1;
end if;
state <= TX_LWORD;
end if;
else
fab_out.dvalid <= '0';
end if;
fab_out.sof <= '0';
-- check for errors
when TX_LWORD =>
fab_out.addr <= c_WRF_DATA;
fab_out.data <= tx_data_reg (15 downto 0);
-- the TX fabric is ready, the memory is ready and we haven't reached the end
-- of the packet yet:
if(tx_err = '1') then
state <= TX_UPDATE_DESCRIPTOR;
cur_tx_desc.error <= '1';
elsif(fab_dreq = '1' and buf_grant_i = '0') then
if(tx_cntr_expired = '0') then
fab_out.dvalid <= '1';
tx_data_reg <= f_buf_swap_endian_32(buf_data_i);
tx_remaining <= tx_remaining - 1;
tx_buf_addr <= tx_buf_addr + 1;
state <= TX_HWORD;
-- We're at the end of the packet. Generate an end-of-packet condition on the
-- fabric I/F
else
fab_out.bytesel <= odd_length and (not needs_padding);
fab_out.dvalid <= '1';
if(needs_padding = '1' and padding_size /= 0) then
state <= TX_PAD;
elsif(cur_tx_desc.ts_e = '1') then
state <= TX_OOB1;
else
state <= TX_END_PACKET;
fab_out.eof <= '0';
end if;
end if;
else
-- the fabric is not ready, don't send anything
fab_out.dvalid <= '0';
end if;
when TX_PAD =>
if(tx_err = '1') then
state <= TX_UPDATE_DESCRIPTOR;
cur_tx_desc.error <= '1';
elsif(fab_dreq = '1') then
fab_out.data <= x"0000";
fab_out.addr <= c_WRF_DATA;
fab_out.dvalid <= '1';
padding_size <= padding_size - 1;
if(padding_size = 0) then
fab_out.dvalid <= '0';
if(cur_tx_desc.ts_e = '1')then
state <= TX_OOB1;
else
fab_out.eof <= '0';
state <= TX_END_PACKET;
end if;
end if;
else
fab_out.dvalid <= '0';
end if;
when TX_OOB1 =>
fab_out.bytesel <= '0';
if(fab_dreq = '1') then
fab_out.data <= c_WRF_OOB_TYPE_TX & x"000";
fab_out.addr <= c_WRF_OOB;
fab_out.dvalid <= '1';
fab_out.eof <= '0';
state <= TX_OOB2;
end if;
when TX_OOB2 =>
fab_out.bytesel <= '0';
if(fab_dreq = '1') then
fab_out.data <= cur_tx_desc.ts_id;
fab_out.addr <= c_WRF_OOB;
fab_out.dvalid <= '1';
fab_out.eof <= '0';
state <= TX_END_PACKET;
end if;
when TX_END_PACKET =>
fab_out.dvalid <= '0';
fab_out.bytesel <= '0';
if(fab_dreq = '1') then
fab_out.eof <= '1';
state <= TX_UPDATE_DESCRIPTOR;
end if;
when TX_UPDATE_DESCRIPTOR =>
fab_out.eof <= '0';
txdesc_write_o <= '1';
txdesc_reload_current_o <= cur_tx_desc.error;
cur_tx_desc.ready <= '0';
if(txdesc_write_done_i = '1') then
txdesc_write_o <= '0';
if(cur_tx_desc.error = '1') then
state <= TX_ERROR;
else
tx_done <= '1';
state <= TX_REQUEST_DESCRIPTOR;
end if;
end if;
when TX_ERROR =>
if(irq_txerr_mask_i = '1') then -- clear the error status in
-- interrupt-driver mode
irq_txerr_o <= '1';
if(irq_txerr_ack_i = '1') then
irq_txerr_o <= '0';
state <= TX_REQUEST_DESCRIPTOR;
end if;
end if;
regs_o.sr_tx_error_i <= '1';
if(regs_i.sr_tx_error_o = '1' and regs_i.sr_tx_error_load_o = '1') then --
-- or in status register mode
irq_txerr_o <= '0';
state <= TX_REQUEST_DESCRIPTOR;
end if;
end case;
end if;
end if;
end process;
gen_rtu_valid : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
rtu_rsp_valid_o <= '0';
rtu_valid_int_d0 <= '0';
else
rtu_valid_int_d0 <= rtu_valid_int;
if(rtu_rsp_ack_i = '1') then
rtu_rsp_valid_o <= '0';
elsif(rtu_valid_int = '1' and rtu_valid_int_d0 = '0') then
rtu_rsp_valid_o <= '1';
end if;
end if;
end if;
end process;
end behavioral;
modules/wrsw_nic/nic_wbgen2_pkg.vhd deleted 100644 → 0
View file @ a216d4a9
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for White Rabbit Switch NIC's spec
---------------------------------------------------------------------------------------
-- File : nic_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_nic.wb
-- Created : Fri Jul 27 17:22:06 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
package nic_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_nic_in_registers is record
sr_bna_i : std_logic;
sr_rec_i : std_logic;
sr_tx_done_i : std_logic;
sr_tx_error_i : std_logic;
sr_cur_tx_desc_i : std_logic_vector(2 downto 0);
sr_cur_rx_desc_i : std_logic_vector(2 downto 0);
end record;
constant c_nic_in_registers_init_value: t_nic_in_registers := (
sr_bna_i => '0',
sr_rec_i => '0',
sr_tx_done_i => '0',
sr_tx_error_i => '0',
sr_cur_tx_desc_i => (others => '0'),
sr_cur_rx_desc_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_nic_out_registers is record
cr_rx_en_o : std_logic;
cr_tx_en_o : std_logic;
sr_rec_o : std_logic;
sr_rec_load_o : std_logic;
sr_tx_done_o : std_logic;
sr_tx_done_load_o : std_logic;
sr_tx_error_o : std_logic;
sr_tx_error_load_o : std_logic;
reset_o : std_logic_vector(31 downto 0);
reset_wr_o : std_logic;
end record;
constant c_nic_out_registers_init_value: t_nic_out_registers := (
cr_rx_en_o => '0',
cr_tx_en_o => '0',
sr_rec_o => '0',
sr_rec_load_o => '0',
sr_tx_done_o => '0',
sr_tx_done_load_o => '0',
sr_tx_error_o => '0',
sr_tx_error_load_o => '0',
reset_o => (others => '0'),
reset_wr_o => '0'
);
function "or" (left, right: t_nic_in_registers) return t_nic_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body nic_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_nic_in_registers) return t_nic_in_registers is
variable tmp: t_nic_in_registers;
begin
tmp.sr_bna_i := f_x_to_zero(left.sr_bna_i) or f_x_to_zero(right.sr_bna_i);
tmp.sr_rec_i := f_x_to_zero(left.sr_rec_i) or f_x_to_zero(right.sr_rec_i);
tmp.sr_tx_done_i := f_x_to_zero(left.sr_tx_done_i) or f_x_to_zero(right.sr_tx_done_i);
tmp.sr_tx_error_i := f_x_to_zero(left.sr_tx_error_i) or f_x_to_zero(right.sr_tx_error_i);
tmp.sr_cur_tx_desc_i := f_x_to_zero(left.sr_cur_tx_desc_i) or f_x_to_zero(right.sr_cur_tx_desc_i);
tmp.sr_cur_rx_desc_i := f_x_to_zero(left.sr_cur_rx_desc_i) or f_x_to_zero(right.sr_cur_rx_desc_i);
return tmp;
end function;
end package body;
modules/wrsw_nic/nic_wishbone_slave.vhd deleted 100644 → 0
View file @ a216d4a9
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for White Rabbit Switch NIC's spec
---------------------------------------------------------------------------------------
-- File : nic_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from wr_nic.wb
-- Created : Fri Jul 27 17:22:06 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
use work.nic_wbgen2_pkg.all;
entity nic_wishbone_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(6 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
irq_rcomp_i : in std_logic;
irq_rcomp_ack_o : out std_logic;
irq_tcomp_i : in std_logic;
irq_tcomp_ack_o : out std_logic;
irq_tcomp_mask_o : out std_logic;
irq_txerr_i : in std_logic;
irq_txerr_ack_o : out std_logic;
irq_txerr_mask_o : out std_logic;
-- Ports for RAM: TX descriptors mem
nic_dtx_addr_i : in std_logic_vector(4 downto 0);
-- Read data output
nic_dtx_data_o : out std_logic_vector(31 downto 0);
-- Read strobe input (active high)
nic_dtx_rd_i : in std_logic;
-- Write data input
nic_dtx_data_i : in std_logic_vector(31 downto 0);
-- Write strobe (active high)
nic_dtx_wr_i : in std_logic;
-- Ports for RAM: RX descriptors mem
nic_drx_addr_i : in std_logic_vector(4 downto 0);
-- Read data output
nic_drx_data_o : out std_logic_vector(31 downto 0);
-- Read strobe input (active high)
nic_drx_rd_i : in std_logic;
-- Write data input
nic_drx_data_i : in std_logic_vector(31 downto 0);
-- Write strobe (active high)
nic_drx_wr_i : in std_logic;
regs_i : in t_nic_in_registers;
regs_o : out t_nic_out_registers
);
end nic_wishbone_slave;
architecture syn of nic_wishbone_slave is
signal nic_cr_rx_en_int : std_logic ;
signal nic_cr_tx_en_int : std_logic ;
signal nic_dtx_rddata_int : std_logic_vector(31 downto 0);
signal nic_dtx_rd_int : std_logic ;
signal nic_dtx_wr_int : std_logic ;
signal nic_drx_rddata_int : std_logic_vector(31 downto 0);
signal nic_drx_rd_int : std_logic ;
signal nic_drx_wr_int : std_logic ;
signal eic_idr_int : std_logic_vector(2 downto 0);
signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(2 downto 0);
signal eic_ier_write_int : std_logic ;
signal eic_imr_int : std_logic_vector(2 downto 0);
signal eic_isr_clear_int : std_logic_vector(2 downto 0);
signal eic_isr_status_int : std_logic_vector(2 downto 0);
signal eic_irq_ack_int : std_logic_vector(2 downto 0);
signal eic_isr_write_int : std_logic ;
signal irq_inputs_vector_int : std_logic_vector(2 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(6 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
nic_cr_rx_en_int <= '0';
nic_cr_tx_en_int <= '0';
regs_o.sr_rec_load_o <= '0';
regs_o.sr_tx_done_load_o <= '0';
regs_o.sr_tx_error_load_o <= '0';
regs_o.reset_wr_o <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
regs_o.sr_rec_load_o <= '0';
regs_o.sr_tx_done_load_o <= '0';
regs_o.sr_tx_error_load_o <= '0';
regs_o.reset_wr_o <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
ack_in_progress <= '0';
else
regs_o.sr_rec_load_o <= '0';
regs_o.sr_tx_done_load_o <= '0';
regs_o.sr_tx_error_load_o <= '0';
regs_o.reset_wr_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(6 downto 5) is
when "00" =>
case rwaddr_reg(3 downto 0) is
when "0000" =>
if (wb_we_i = '1') then
nic_cr_rx_en_int <= wrdata_reg(0);
nic_cr_tx_en_int <= wrdata_reg(1);
end if;
rddata_reg(0) <= nic_cr_rx_en_int;
rddata_reg(1) <= nic_cr_tx_en_int;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001" =>
if (wb_we_i = '1') then
regs_o.sr_rec_load_o <= '1';
regs_o.sr_tx_done_load_o <= '1';
regs_o.sr_tx_error_load_o <= '1';
end if;
rddata_reg(0) <= regs_i.sr_bna_i;
rddata_reg(1) <= regs_i.sr_rec_i;
rddata_reg(2) <= regs_i.sr_tx_done_i;
rddata_reg(3) <= regs_i.sr_tx_error_i;
rddata_reg(10 downto 8) <= regs_i.sr_cur_tx_desc_i;
rddata_reg(18 downto 16) <= regs_i.sr_cur_rx_desc_i;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010" =>
if (wb_we_i = '1') then
regs_o.reset_wr_o <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
if (wb_we_i = '1') then
eic_ier_write_int <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(2 downto 0) <= eic_imr_int(2 downto 0);
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1011" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
end if;
rddata_reg(2 downto 0) <= eic_isr_status_int(2 downto 0);
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
when "01" =>
if (rd_int = '1') then
ack_sreg(0) <= '1';
else
ack_sreg(0) <= '1';
end if;
ack_in_progress <= '1';
when "10" =>
if (rd_int = '1') then
ack_sreg(0) <= '1';
else
ack_sreg(0) <= '1';
end if;
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Data output multiplexer process
process (rddata_reg, rwaddr_reg, nic_dtx_rddata_int, nic_drx_rddata_int, wb_adr_i )
begin
case rwaddr_reg(6 downto 5) is
when "01" =>
wb_dat_o(31 downto 0) <= nic_dtx_rddata_int;
when "10" =>
wb_dat_o(31 downto 0) <= nic_drx_rddata_int;
when others =>
wb_dat_o <= rddata_reg;
end case;
end process;
-- Read & write lines decoder for RAMs
process (wb_adr_i, rd_int, wr_int )
begin
if (wb_adr_i(6 downto 5) = "01") then
nic_dtx_rd_int <= rd_int;
nic_dtx_wr_int <= wr_int;
else
nic_dtx_wr_int <= '0';
nic_dtx_rd_int <= '0';
end if;
if (wb_adr_i(6 downto 5) = "10") then
nic_drx_rd_int <= rd_int;
nic_drx_wr_int <= wr_int;
else
nic_drx_wr_int <= '0';
nic_drx_rd_int <= '0';
end if;
end process;
-- Receive enable
regs_o.cr_rx_en_o <= nic_cr_rx_en_int;
-- Transmit enable
regs_o.cr_tx_en_o <= nic_cr_tx_en_int;
-- Buffer Not Available
-- Frame Received
regs_o.sr_rec_o <= wrdata_reg(1);
-- Transmission done
regs_o.sr_tx_done_o <= wrdata_reg(2);
-- Transmission error
regs_o.sr_tx_error_o <= wrdata_reg(3);
-- Current TX descriptor
-- Current RX descriptor
-- Software reset
-- pass-through field: Software reset in register: SW_Reset
regs_o.reset_o <= wrdata_reg(31 downto 0);
-- extra code for reg/fifo/mem: TX descriptors mem
-- RAM block instantiation for memory: TX descriptors mem
nic_dtx_raminst : wbgen2_dpssram
generic map (
g_data_width => 32,
g_size => 32,
g_addr_width => 5,
g_dual_clock => false,
g_use_bwsel => false
)
port map (
clk_a_i => clk_sys_i,
clk_b_i => clk_sys_i,
addr_b_i => nic_dtx_addr_i,
addr_a_i => rwaddr_reg(4 downto 0),
data_b_o => nic_dtx_data_o,
rd_b_i => nic_dtx_rd_i,
data_b_i => nic_dtx_data_i,
wr_b_i => nic_dtx_wr_i,
bwsel_b_i => allones(3 downto 0),
data_a_o => nic_dtx_rddata_int(31 downto 0),
rd_a_i => nic_dtx_rd_int,
data_a_i => wrdata_reg(31 downto 0),
wr_a_i => nic_dtx_wr_int,
bwsel_a_i => allones(3 downto 0)
);
-- extra code for reg/fifo/mem: RX descriptors mem
-- RAM block instantiation for memory: RX descriptors mem
nic_drx_raminst : wbgen2_dpssram
generic map (
g_data_width => 32,
g_size => 32,
g_addr_width => 5,
g_dual_clock => false,
g_use_bwsel => false
)
port map (
clk_a_i => clk_sys_i,
clk_b_i => clk_sys_i,
addr_b_i => nic_drx_addr_i,
addr_a_i => rwaddr_reg(4 downto 0),
data_b_o => nic_drx_data_o,
rd_b_i => nic_drx_rd_i,
data_b_i => nic_drx_data_i,
wr_b_i => nic_drx_wr_i,
bwsel_b_i => allones(3 downto 0),
data_a_o => nic_drx_rddata_int(31 downto 0),
rd_a_i => nic_drx_rd_int,
data_a_i => wrdata_reg(31 downto 0),
wr_a_i => nic_drx_wr_int,
bwsel_a_i => allones(3 downto 0)
);
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(2 downto 0) <= wrdata_reg(2 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register
eic_ier_int(2 downto 0) <= wrdata_reg(2 downto 0);
-- extra code for reg/fifo/mem: Interrupt status register
eic_isr_clear_int(2 downto 0) <= wrdata_reg(2 downto 0);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
eic_irq_controller_inst : wbgen2_eic
generic map (
g_num_interrupts => 3,
g_irq00_mode => 3,
g_irq01_mode => 3,
g_irq02_mode => 3,
g_irq03_mode => 0,
g_irq04_mode => 0,
g_irq05_mode => 0,
g_irq06_mode => 0,
g_irq07_mode => 0,
g_irq08_mode => 0,
g_irq09_mode => 0,
g_irq0a_mode => 0,
g_irq0b_mode => 0,
g_irq0c_mode => 0,
g_irq0d_mode => 0,
g_irq0e_mode => 0,
g_irq0f_mode => 0,
g_irq10_mode => 0,
g_irq11_mode => 0,
g_irq12_mode => 0,
g_irq13_mode => 0,
g_irq14_mode => 0,
g_irq15_mode => 0,
g_irq16_mode => 0,
g_irq17_mode => 0,
g_irq18_mode => 0,
g_irq19_mode => 0,
g_irq1a_mode => 0,
g_irq1b_mode => 0,
g_irq1c_mode => 0,
g_irq1d_mode => 0,
g_irq1e_mode => 0,
g_irq1f_mode => 0
)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
irq_i => irq_inputs_vector_int,
irq_ack_o => eic_irq_ack_int,
reg_imr_o => eic_imr_int,
reg_ier_i => eic_ier_int,
reg_ier_wr_stb_i => eic_ier_write_int,
reg_idr_i => eic_idr_int,
reg_idr_wr_stb_i => eic_idr_write_int,
reg_isr_o => eic_isr_status_int,
reg_isr_i => eic_isr_clear_int,
reg_isr_wr_stb_i => eic_isr_write_int,
wb_irq_o => wb_int_o
);
irq_inputs_vector_int(0) <= irq_rcomp_i;
irq_rcomp_ack_o <= eic_irq_ack_int(0);
irq_inputs_vector_int(1) <= irq_tcomp_i;
irq_tcomp_ack_o <= eic_irq_ack_int(1);
irq_tcomp_mask_o <= eic_imr_int(1);
irq_inputs_vector_int(2) <= irq_txerr_i;
irq_txerr_ack_o <= eic_irq_ack_int(2);
irq_txerr_mask_o <= eic_imr_int(2);
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
modules/wrsw_nic/wr_nic.wb deleted 100644 → 0
View file @ a216d4a9
-- -*- Mode: LUA; tab-width: 2 -*-
-- White-Rabbit NIC spec
-- author: Emilio G. Cota <cota@braap.org>
-- updated by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
--
-- Use wbgen2 to generate code, documentation and more.
-- wbgen2 is available at:
-- http://www.ohwr.org/projects/wishbone-gen
--
top = peripheral {
name = "White Rabbit Switch NIC's spec",
description = "This NIC is in between the endpoints and the on-board Linux CPU of the White Rabbit Switch.\
\
Operation \
~~~~~~~ \
* There's a pool of n TX descriptors and a pool of n RX descriptors. \
* In fact, we should have n for TX and m for RX since 32K / 1536 = 21.3. Anyway, to make things simple, first let's do n and n; we can fine-tune later on. \
* Software keeps track of which buffers are marked to be used with the READY/EMPTY flags. \
* Interrupts are useed by software to update the state, e.g. when frames are received or when a frame has been sent. \
* Endianness: all multi-byte registers are Little Endian \
\
Frame transmission \
~~~~~~~~~~~~~~~ \
* Enable Transmission in the Control Register \
* Store the frame in memory \
* Fill in the corresponding descriptor from the TX pool \
* Set READY bit to 1 \
* Interrupt arrives--if enabled-- and software updates stats reading the descriptor (READY has been set to 0 by the NIC). \
\
Frame reception \
~~~~~~~~~~~~~ \
* Enable Reception in the Control Register \
* Initialize a descriptor from the RX descriptors pool. Mark it as EMPTY \
* A frame is received and, if enabled, the NIC raises an interrupt \
* With EMPTY set to 0, the frame can now be copied from the NIC's memory and stats can be updated \
* Set READY bit to 1 \
\
Todo \
~~~~ \
* Descriptors in RAM, not as registers. wbgen2 doesn't support this yet. Working on it. \
Known issues \
~~~~~~~~~~~ \
* Only 32-bit aligned addresses are supported";
hdl_entity = "nic_wishbone_slave";
prefix = "nic";
reg {
name = "NIC Control Register";
prefix = "CR";
field {
name = "Receive enable";
description = "Enables the NIC to receive data";
prefix = "rx_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Transmit enable";
description = "Enables the NIC to transmit data. When reset, the internal transmit pointer points to the first entry in the TX descriptor pool";
prefix = "tx_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "NIC Status Register";
prefix = "SR";
field {
name = "Buffer Not Available";
prefix = "bna";
description = "No buffers were available when receiving a packet.";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
load = LOAD_EXT;
};
field {
name = "Frame Received";
prefix = "rec";
description = "One or more frames have been received.\
Cleared by writing a one to this bit";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Transmission done";
prefix = "tx_done";
description = "read 1: All non-empty TX descriptors have been transmitted\
read 0: Transmission in progress\
write 1: Clears the flag\
write 0: No effect";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Transmission error";
prefix = "tx_error";
description = "read 1: A TX error occured and the transmission was stopped. CUR_TX_DESC is pointing the TX descriptor for which the error occured\
read 0: No TX error\
write 1: Clears the flag\
write 0: No effect";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
align = 8;
name = "Current TX descriptor";
size = 3;
prefix = "cur_TX_Desc";
description = "Index of the currently handled TX descriptor";
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
align = 8;
name = "Current RX descriptor";
size = 3;
prefix = "cur_RX_DESC";
description = "Index of the currently handled RX descriptor";
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "SW_Reset";
description = "Writing to this register resets the NIC, zeroing all registers and resetting the state of the module";
prefix = "reset";
field {
name = "Software reset";
type = PASS_THROUGH;
size = 32;
};
};
irq {
name = "Receive Complete";
prefix = "rcomp";
ack_line = true;
description = "A frame has been stored in memory.";
trigger = LEVEL_1;
};
irq {
name = "Transmit Complete";
prefix = "tcomp";
ack_line = true;
mask_line = true;
description = "Frame successfully transmitted";
trigger = LEVEL_1;
};
irq {
name = "Transmit Error";
prefix = "txerr";
ack_line = true;
mask_line = true;
trigger = LEVEL_1;
};
ram {
name = "TX descriptors mem";
prefix = "dtx";
size = 32;
width = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
ram {
name = "RX descriptors mem";
prefix = "drx";
size = 32;
width = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
-- ram {
-- name = "TX/RX Buffers";
-- prefix = "mem";
-- -- 8192 * 32 = 32Kb
-- size = 8192;
-- width = 32;
-- access_bus = READ_WRITE;
-- access_dev = READ_WRITE;
-- };
};
TX_desc_template =
{
reg {
name = "TX Descriptor %d register 1";
description = "1st part of TX descriptor header. ";
prefix = "tx%d_d1";
align = 4;
field {
name = "Ready";
prefix = "ready";
description = "0 - The descriptor and buffer can be manipulated. \
1 - The device owns the descriptor and will set the bit to 0 after transmission";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Error";
prefix = "error";
description = "1 - an error occured during transmission of this descriptor.\
0 - transmission was successful";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Timestamp Enable";
description = "Set to 1 if the frame has to be timestamped by the endpoint. The NIC will then generate a TX OOB block on its WRF source, containing the value of TS_ID from the descriptor. ";
prefix = "ts_e";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
},
field {
name = "Pad Enable";
prefix = "pad_e";
description = "When set, short frames (< 60 bytes) are padded with zeros to 60 bytes. This doesn't include the CRC field (so the final frame length will be 64 bytes)";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
},
-- todo: Errors: add some more, e.g. Retry Count, Retry Limit exceeded...
field {
name = "Timestamp Frame Identifier";
prefix = "ts_id";
description = "Frame Identifier - a 16-bit value which must be unique in reasonably long time period. It's used to match the TX timestamps coming from different physical ports with the timestamped packets.";
type = SLV;
size = 16;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TX Descriptor %d register 2";
prefix = "tx%d_d2";
field {
name = "offset in RAM--in bytes, must be aligned to 32-bit boundary";
prefix = "offset";
type = SLV;
size = 13;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2)";
prefix = "len";
type = SLV;
size = 13;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TX Descriptor %d register 3";
prefix = "tx%d_d3";
field {
prefix = "DPM";
name = "Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet.";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
RX_desc_template = {
reg {
align=4;
name = "RX Descriptor %d register 1";
description = "Descriptor of an RX frame buffer";
prefix = "rx%d_d1";
field {
name = "Empty";
prefix = "empty";
description = "0 - Reception (or failure) has occurred on this buffer. The NIC cannot operate on the until this bit is set to 1. \
1 - The buffer is ready to be filled in with data by the NIC";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Error";
prefix = "error";
description = "Set when the the received frame contains an error (an error was indicated by the remote WRF source)";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block.";
prefix = "port";
type = SLV;
size = 6;
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Got RX Timestamp";
prefix = "GOT_TS";
description = "1 - there is a valid RX timestamp present in the TS field,\
0 - no RX timestamp";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "RX Descriptor %d register 2";
prefix = "rx%d_d2";
field {
name = "RX_TS_R";
description = "Value of the RX timestamp (rising edge bits)";
size = 28;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX_TS_F";
description = "Value of the RX timestamp (falling edge bits)";
size = 4;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "RX Descriptor %d register 3";
prefix = "rx%d_d3";
field {
name = "Offset in packet RAM (in bytes, 32-bit aligned)";
prefix = "offset";
type = SLV;
size = 13;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
},
field {
name = "Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet.";
prefix = "len";
type = SLV;
size = 13;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
};
function generate_descriptors(n)
local i;
for i=1,n do
local T=deepcopy(TX_desc_template);
foreach_reg({TYPE_REG}, function(r)
r.name = string.format(r.name, i);
r.prefix = string.format(r.prefix, i);
print(r.name)
end, T);
table_join(periph, T);
end
for i=1,n do
local T=deepcopy(RX_desc_template);
foreach_reg({TYPE_REG}, function(r)
r.name = string.format(r.name, i);
r.prefix = string.format(r.prefix, i);
end, T);
table_join(periph, T);
end
end
--generate_descriptors(8);
modules/wrsw_nic/wrsw_nic.vhd deleted 100644 → 0
View file @ a216d4a9
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
entity wrsw_nic is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-------------------------------------------------------------------------------
-- Pipelined Wishbone interface
-------------------------------------------------------------------------------
-- WBP Master (TX)
src_dat_o : out std_logic_vector(15 downto 0);
src_adr_o : out std_logic_vector(1 downto 0);
src_sel_o : out std_logic_vector(1 downto 0);
src_cyc_o : out std_logic;
src_stb_o : out std_logic;
src_we_o : out std_logic;
src_stall_i : in std_logic;
src_err_i : in std_logic;
src_ack_i : in std_logic;
-- WBP Slave (RX)
snk_dat_i : in std_logic_vector(15 downto 0);
snk_adr_i : in std_logic_vector(1 downto 0);
snk_sel_i : in std_logic_vector(1 downto 0);
snk_cyc_i : in std_logic;
snk_stb_i : in std_logic;
snk_we_i : in std_logic;
snk_stall_o : out std_logic;
snk_err_o : out std_logic;
snk_ack_o : out std_logic;
-------------------------------------------------------------------------------
-- "Fake" RTU interface
-------------------------------------------------------------------------------
rtu_dst_port_mask_o : out std_logic_vector(31 downto 0);
rtu_prio_o : out std_logic_vector(2 downto 0);
rtu_drop_o : out std_logic;
rtu_rsp_valid_o : out std_logic;
rtu_rsp_ack_i : in std_logic;
-------------------------------------------------------------------------------
-- Wishbone bus
-------------------------------------------------------------------------------
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic
);
end wrsw_nic;
architecture rtl of wrsw_nic is
component xwrsw_nic
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
rtu_dst_port_mask_o : out std_logic_vector(31 downto 0);
rtu_prio_o : out std_logic_vector(2 downto 0);
rtu_drop_o : out std_logic;
rtu_rsp_valid_o : out std_logic;
rtu_rsp_ack_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
end component;
signal snk_out : t_wrf_sink_out;
signal snk_in : t_wrf_sink_in;
signal src_out : t_wrf_source_out;
signal src_in : t_wrf_source_in;
signal wb_out : t_wishbone_slave_out;
signal wb_in : t_wishbone_slave_in;
begin
U_Wrapped_NIC : xwrsw_nic
generic map (
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
snk_i => snk_in,
snk_o => snk_out,
src_i => src_in,
src_o => src_out,
rtu_dst_port_mask_o => rtu_dst_port_mask_o,
rtu_prio_o => rtu_prio_o,
rtu_drop_o => rtu_drop_o,
rtu_rsp_valid_o => rtu_rsp_valid_o,
rtu_rsp_ack_i => rtu_rsp_ack_i,
wb_i => wb_in,
wb_o => wb_out);
-- WBP Master (TX)
src_dat_o <= src_out.dat;
src_adr_o <= src_out.adr;
src_sel_o <= src_out.sel;
src_cyc_o <= src_out.cyc;
src_stb_o <= src_out.stb;
src_we_o <= src_out.we;
src_in.stall <= src_stall_i;
src_in.err <= src_err_i;
src_in.ack <= src_ack_i;
-- WBP Slave (RX)
snk_in.dat <= snk_dat_i;
snk_in.adr <= snk_adr_i;
snk_in.sel <= snk_sel_i;
snk_in.cyc <= snk_cyc_i;
snk_in.stb <= snk_stb_i;
snk_in.we <= snk_we_i;
snk_stall_o <= snk_out.stall;
snk_err_o <= snk_out.err;
snk_ack_o <= snk_out.ack;
wb_in.cyc <= wb_cyc_i;
wb_in.stb <= wb_stb_i;
wb_in.we <= wb_we_i;
wb_in.sel <= wb_sel_i;
wb_in.adr <= wb_adr_i;
wb_in.dat <= wb_dat_i;
wb_dat_o <= wb_out.dat;
wb_ack_o <= wb_out.ack;
wb_stall_o <= wb_out.stall;
wb_irq_o <= wb_out.int;
end rtl;
modules/wrsw_nic/xwrsw_nic.vhd deleted 100644 → 0
View file @ a216d4a9
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.nic_constants_pkg.all;
use work.nic_descriptors_pkg.all;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.nic_wbgen2_pkg.all;
entity xwrsw_nic is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-------------------------------------------------------------------------------
-- WRF sink
-------------------------------------------------------------------------------
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
-------------------------------------------------------------------------------
-- "Fake" RTU interface
-------------------------------------------------------------------------------
rtu_dst_port_mask_o : out std_logic_vector(31 downto 0);
rtu_prio_o : out std_logic_vector(2 downto 0);
rtu_drop_o : out std_logic;
rtu_rsp_valid_o : out std_logic;
rtu_rsp_ack_i : in std_logic;
-------------------------------------------------------------------------------
-- Wishbone bus
-------------------------------------------------------------------------------
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out
);
end xwrsw_nic;
architecture rtl of xwrsw_nic is
component nic_descriptor_manager
generic (
g_desc_mode : string;
g_num_descriptors : integer;
g_num_descriptors_log2 : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
enable_i : in std_logic;
bna_o : out std_logic;
bna_clear_i : in std_logic;
cur_desc_idx_o : out std_logic_vector(g_num_descriptors_log2-1 downto 0);
dtbl_addr_o : out std_logic_vector(g_num_descriptors_log2+1 downto 0);
dtbl_data_i : in std_logic_vector(31 downto 0);
dtbl_rd_o : out std_logic;
dtbl_data_o : out std_logic_vector(31 downto 0);
dtbl_wr_o : out std_logic;
desc_reload_current_i : in std_logic;
desc_request_next_i : in std_logic;
desc_grant_o : out std_logic;
rxdesc_current_o : out t_rx_descriptor;
rxdesc_new_i : in t_rx_descriptor;
txdesc_current_o : out t_tx_descriptor;
txdesc_new_i : in t_tx_descriptor;
desc_write_i : in std_logic;
desc_write_done_o : out std_logic);
end component;
component nic_rx_fsm
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
regs_i : in t_nic_out_registers;
regs_o : out t_nic_in_registers;
bna_i : in std_logic;
irq_rcomp_o : out std_logic;
irq_rcomp_ack_i : in std_logic;
rxdesc_request_next_o : out std_logic;
rxdesc_grant_i : in std_logic;
rxdesc_current_i : in t_rx_descriptor;
rxdesc_new_o : out t_rx_descriptor;
rxdesc_write_o : out std_logic;
rxdesc_write_done_i : in std_logic;
buf_grant_i : in std_logic;
buf_addr_o : out std_logic_vector(c_nic_buf_size_log2-3 downto 0);
buf_wr_o : out std_logic;
buf_data_o : out std_logic_vector(31 downto 0));
end component;
component nic_buffer
generic (
g_memsize_log2 : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
addr_i : in std_logic_vector(g_memsize_log2-1 downto 0);
data_i : in std_logic_vector(31 downto 0);
wr_i : in std_logic;
data_o : out std_logic_vector(31 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_addr_i : in std_logic_vector(g_memsize_log2-1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic);
end component;
component nic_wishbone_slave
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(6 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
irq_rcomp_i : in std_logic;
irq_rcomp_ack_o : out std_logic;
irq_tcomp_i : in std_logic;
irq_tcomp_ack_o : out std_logic;
irq_tcomp_mask_o : out std_logic;
irq_txerr_i : in std_logic;
irq_txerr_ack_o : out std_logic;
irq_txerr_mask_o : out std_logic;
nic_dtx_addr_i : in std_logic_vector(4 downto 0);
nic_dtx_data_o : out std_logic_vector(31 downto 0);
nic_dtx_rd_i : in std_logic;
nic_dtx_data_i : in std_logic_vector(31 downto 0);
nic_dtx_wr_i : in std_logic;
nic_drx_addr_i : in std_logic_vector(4 downto 0);
nic_drx_data_o : out std_logic_vector(31 downto 0);
nic_drx_rd_i : in std_logic;
nic_drx_data_i : in std_logic_vector(31 downto 0);
nic_drx_wr_i : in std_logic;
regs_i : in t_nic_in_registers;
regs_o : out t_nic_out_registers);
end component;
component nic_tx_fsm
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
src_o : out t_wrf_source_out;
src_i : in t_wrf_source_in;
rtu_dst_port_mask_o : out std_logic_vector(31 downto 0);
rtu_prio_o : out std_logic_vector(2 downto 0);
rtu_drop_o : out std_logic;
rtu_rsp_valid_o : out std_logic;
rtu_rsp_ack_i : in std_logic;
regs_i : in t_nic_out_registers;
regs_o : out t_nic_in_registers;
irq_tcomp_o : out std_logic;
irq_tcomp_ack_i : in std_logic;
irq_tcomp_mask_i : in std_logic;
irq_txerr_o : out std_logic;
irq_txerr_ack_i : in std_logic;
irq_txerr_mask_i : in std_logic;
txdesc_reload_current_o : out std_logic;
txdesc_request_next_o : out std_logic;
txdesc_grant_i : in std_logic;
txdesc_current_i : in t_tx_descriptor;
txdesc_new_o : out t_tx_descriptor;
txdesc_write_o : out std_logic;
txdesc_write_done_i : in std_logic;
bna_i : in std_logic;
buf_grant_i : in std_logic;
buf_addr_o : out std_logic_vector(c_nic_buf_size_log2-3 downto 0);
buf_data_i : in std_logic_vector(31 downto 0));
end component;
signal rxdesc_request_next : std_logic;
signal rxdesc_grant : std_logic;
signal rxdesc_current : t_rx_descriptor;
signal rxdesc_new : t_rx_descriptor;
signal rxdesc_write : std_logic;
signal rxdesc_write_done : std_logic;
signal txdesc_reload_current : std_logic;
signal txdesc_request_next : std_logic;
signal txdesc_grant : std_logic;
signal txdesc_current : t_tx_descriptor;
signal txdesc_new : t_tx_descriptor;
signal txdesc_write : std_logic;
signal txdesc_write_done : std_logic;
signal regs_fromwb : t_nic_out_registers;
signal regs_towb_main, regs_towb_rx, regs_towb_tx, regs_towb : t_nic_in_registers;
signal irq_rcomp : std_logic;
signal irq_rcomp_ack : std_logic;
signal irq_tcomp : std_logic;
signal irq_tcomp_ack : std_logic;
signal irq_tcomp_mask : std_logic;
signal irq_txerr : std_logic;
signal irq_txerr_ack : std_logic;
signal irq_txerr_mask : std_logic;
signal nic_dtx_addr : std_logic_vector(4 downto 0);
signal nic_dtx_wr_data : std_logic_vector(31 downto 0);
signal nic_dtx_rd : std_logic;
signal nic_dtx_rd_data : std_logic_vector(31 downto 0);
signal nic_dtx_wr : std_logic;
signal nic_drx_addr : std_logic_vector(4 downto 0);
signal nic_drx_wr_data : std_logic_vector(31 downto 0);
signal nic_drx_rd : std_logic;
signal nic_drx_rd_data : std_logic_vector(31 downto 0);
signal nic_drx_wr : std_logic;
signal nic_mem_addr : std_logic_vector(12 downto 0);
signal nic_mem_wr_data : std_logic_vector(31 downto 0);
signal nic_mem_rd : std_logic;
signal nic_mem_rd_data : std_logic_vector(31 downto 0);
signal nic_mem_wr : std_logic;
signal mem_grant_rx : std_logic;
signal mem_grant_tx : std_logic;
signal mem_addr_tx : std_logic_vector(c_nic_buf_size_log2-3 downto 0);
signal mem_addr_rx : std_logic_vector(c_nic_buf_size_log2-3 downto 0);
signal mem_wr_rx : std_logic;
signal mem_wr_data_rx : std_logic_vector(31 downto 0);
signal tx_bna : std_logic;
signal nic_reset_n : std_logic;
signal dummy_rx_desc : t_rx_descriptor; -- stupid VHDL
signal dummy_tx_desc : t_tx_descriptor;
signal wb_cyc_slave : std_logic;
signal wb_cyc_buf : std_logic;
signal wb_ack_slave : std_logic;
signal wb_ack_buf : std_logic;
signal wb_rdata_slave : std_logic_vector(31 downto 0);
signal wb_rdata_buf : std_logic_vector(31 downto 0);
signal wb_in : t_wishbone_master_out;
signal wb_out : t_wishbone_master_in;
begin -- rtl
U_Adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => PIPELINED,
g_master_granularity => WORD,
g_slave_use_struct => true,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => wb_i,
slave_o => wb_o,
master_i => wb_out,
master_o => wb_in);
wb_out.err <= '0';
wb_out.rty <= '0';
nic_reset_n <= rst_n_i and (not regs_fromwb.reset_wr_o);
regs_towb <= regs_towb_tx or regs_towb_rx or regs_towb_main;
-- SUPPORTING PIPELINE WBGEN2 SLAVES
U_WB_SLAVE : nic_wishbone_slave
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_in.adr(6 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_rdata_slave,
wb_cyc_i => wb_cyc_slave,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_ack_slave,
wb_stall_o=> wb_out.stall,
wb_int_o => wb_out.int,
regs_o => regs_fromwb,
regs_i => regs_towb,
irq_rcomp_i => irq_rcomp,
irq_rcomp_ack_o => irq_rcomp_ack,
irq_tcomp_i => irq_tcomp,
irq_tcomp_ack_o => irq_tcomp_ack,
irq_tcomp_mask_o => irq_tcomp_mask,
irq_txerr_i => irq_txerr,
irq_txerr_ack_o => irq_txerr_ack,
irq_txerr_mask_o => irq_txerr_mask,
nic_dtx_addr_i => nic_dtx_addr,
nic_dtx_data_o => nic_dtx_rd_data,
nic_dtx_rd_i => nic_dtx_rd,
nic_dtx_data_i => nic_dtx_wr_data,
nic_dtx_wr_i => nic_dtx_wr,
nic_drx_addr_i => nic_drx_addr,
nic_drx_data_o => nic_drx_rd_data,
nic_drx_rd_i => nic_drx_rd,
nic_drx_data_i => nic_drx_wr_data,
nic_drx_wr_i => nic_drx_wr);
U_BUFFER : nic_buffer
generic map (
g_memsize_log2 => c_nic_buf_size_log2 - 2)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => nic_reset_n,
addr_i => nic_mem_addr,
data_i => nic_mem_wr_data,
wr_i => nic_mem_wr,
data_o => nic_mem_rd_data,
wb_data_i => wb_in.dat,
wb_data_o => wb_rdata_buf,
wb_addr_i => wb_in.adr(c_nic_buf_size_log2 - 3 downto 0),
wb_cyc_i => wb_cyc_buf,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_ack_buf);
wb_cyc_slave <= wb_in.cyc when wb_in.adr(13) = '0' else '0';
wb_cyc_buf <= wb_in.cyc when wb_in.adr(13) = '1' else '0';
wb_out.ack <= wb_ack_buf or wb_ack_slave;
wb_out.dat <= wb_rdata_slave when (wb_in.adr(13) = '0')
else wb_rdata_buf;
p_buffer_arb : process(clk_sys_i, nic_reset_n)
begin
if rising_edge(clk_sys_i) then
if(nic_reset_n = '0') then
mem_grant_rx <= '0';
else
mem_grant_rx <= not mem_grant_rx; -- round-robin
end if;
end if;
end process;
mem_grant_tx <= not mem_grant_rx;
p_mux_buffer_addr : process(mem_grant_rx, mem_addr_tx, mem_addr_rx)
begin
if(mem_grant_rx = '0') then
nic_mem_addr <= mem_addr_tx;
else
nic_mem_addr <= mem_addr_rx;
end if;
end process;
nic_mem_wr_data <= mem_wr_data_rx;
nic_mem_wr <= mem_wr_rx when mem_grant_rx = '1' else '0';
--mem_addr_tx <= (others => '0');
nic_mem_rd <= '1';
-- bna_clear_rx <= nic_sr_bna_out and nic_sr_bna_load;
-------------------------------------------------------------------------------
-- RX Path
-------------------------------------------------------------------------------
U_RX_DESC_MANAGER : nic_descriptor_manager
generic map (
g_desc_mode => "rx",
g_num_descriptors => c_nic_num_rx_descriptors,
g_num_descriptors_log2 => c_nic_num_rx_descriptors_log2)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => nic_reset_n,
enable_i => regs_fromwb.cr_rx_en_o,
bna_o => regs_towb_main.sr_bna_i,
bna_clear_i => '1',
cur_desc_idx_o => regs_towb_main.sr_cur_rx_desc_i,
dtbl_addr_o => nic_drx_addr,
dtbl_data_i => nic_drx_rd_data,
dtbl_rd_o => nic_drx_rd,
dtbl_data_o => nic_drx_wr_data,
dtbl_wr_o => nic_drx_wr,
desc_reload_current_i => '0',
desc_request_next_i => rxdesc_request_next,
desc_grant_o => rxdesc_grant,
desc_write_i => rxdesc_write,
desc_write_done_o => rxdesc_write_done,
rxdesc_current_o => rxdesc_current,
rxdesc_new_i => rxdesc_new,
txdesc_current_o => open,
txdesc_new_i => dummy_tx_desc
);
U_RX_FSM : nic_rx_fsm
port map (
clk_sys_i => clk_sys_i,
rst_n_i => nic_reset_n,
snk_i => snk_i,
snk_o => snk_o,
bna_i => regs_towb_main.sr_bna_i,
regs_i => regs_fromwb,
regs_o => regs_towb_rx,
irq_rcomp_o => irq_rcomp,
irq_rcomp_ack_i => irq_rcomp_ack,
rxdesc_request_next_o => rxdesc_request_next,
rxdesc_grant_i => rxdesc_grant,
rxdesc_current_i => rxdesc_current,
rxdesc_new_o => rxdesc_new,
rxdesc_write_o => rxdesc_write,
rxdesc_write_done_i => rxdesc_write_done,
buf_grant_i => mem_grant_rx,
buf_addr_o => mem_addr_rx,
buf_wr_o => mem_wr_rx,
buf_data_o => mem_wr_data_rx);
-------------------------------------------------------------------------------
-- TX Path
-------------------------------------------------------------------------------
U_TX_DESC_MANAGER : nic_descriptor_manager
generic map (
g_desc_mode => "tx",
g_num_descriptors => c_nic_num_tx_descriptors,
g_num_descriptors_log2 => c_nic_num_tx_descriptors_log2)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => nic_reset_n,
enable_i => regs_fromwb.cr_tx_en_o,
bna_o => tx_bna,
bna_clear_i => '0',
cur_desc_idx_o => regs_towb_main.sr_cur_tx_desc_i,
dtbl_addr_o => nic_dtx_addr,
dtbl_data_i => nic_dtx_rd_data,
dtbl_rd_o => nic_dtx_rd,
dtbl_data_o => nic_dtx_wr_data,
dtbl_wr_o => nic_dtx_wr,
desc_reload_current_i => txdesc_reload_current,
desc_request_next_i => txdesc_request_next,
desc_grant_o => txdesc_grant,
rxdesc_current_o => open,
rxdesc_new_i => dummy_rx_desc,
txdesc_current_o => txdesc_current,
txdesc_new_i => txdesc_new,
desc_write_i => txdesc_write,
desc_write_done_o => txdesc_write_done);
U_TX_FSM : nic_tx_fsm
port map (
clk_sys_i => clk_sys_i,
rst_n_i => nic_reset_n,
src_o => src_o,
src_i => src_i,
rtu_dst_port_mask_o => rtu_dst_port_mask_o,
rtu_prio_o => rtu_prio_o,
rtu_drop_o => rtu_drop_o,
rtu_rsp_valid_o => rtu_rsp_valid_o,
rtu_rsp_ack_i => rtu_rsp_ack_i,
regs_i => regs_fromwb,
regs_o => regs_towb_tx,
irq_tcomp_o => irq_tcomp,
irq_tcomp_ack_i => irq_tcomp_ack,
irq_tcomp_mask_i => irq_tcomp_mask,
irq_txerr_o => irq_txerr,
irq_txerr_ack_i => irq_txerr_ack,
irq_txerr_mask_i => irq_txerr_mask,
txdesc_reload_current_o => txdesc_reload_current,
txdesc_request_next_o => txdesc_request_next,
txdesc_grant_i => txdesc_grant,
txdesc_current_i => txdesc_current,
txdesc_new_o => txdesc_new,
txdesc_write_o => txdesc_write,
txdesc_write_done_i => txdesc_write_done,
bna_i => tx_bna,
buf_grant_i => mem_grant_tx,
buf_addr_o => mem_addr_tx,
buf_data_i => nic_mem_rd_data);
end rtl;
modules/wrsw_txtsu/Manifest.py deleted 100644 → 0
View file @ a216d4a9
files = ["xwrsw_txtsu.vhd",
"wrsw_txtsu_wb.vhd",
"wrsw_txtsu_pkg.vhd"]
modules/wrsw_txtsu/build_wb.sh deleted 100644 → 0
View file @ a216d4a9
#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/txtsu.htm -V wrsw_txtsu_wb.vhd --cstyle defines --lang vhdl -K ../../sim/tx_tstsu_regs.vh wrsw_txtsu.wb
modules/wrsw_txtsu/wrsw_txtsu.wb deleted 100644 → 0
View file @ a216d4a9
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "Shared TX Timestamping Unit (TXTSU)";
prefix="txtsu";
hdl_entity="wrsw_txtsu_wb";
-- TXTSU shared FIFO
fifo_reg {
size = 256; -- or more. We'll see :)
direction = CORE_TO_BUS;
prefix = "tsf";
name = "Timestamp FIFO";
description = "This FIFO holds the TX packet timestamps gathered from all switch endpoints. Each entry contains a single timestamp value consisting of 2 numbers:\
- VAL_R - the timestamp taken at rising clock edge. This is the main timestamp value\
- VAL_F - few LSBs of timestamp taken at falling clock edge. It's used in conjunction with VAL_R to determine if the timestamp has been taken\
properly (there was no metastability/setup/hold violation)\
Entries also contain information required to identify the endpoint and frame for which the timestamp was taken:\
- FID - Frame identifier assigned by the NIC\
- PID - TXTSU port ID to which came the timestamp. Used to distinguish the timestamps for broadcast/multicast frames;\
- INCORRECT - timestamp may be incorrect, it has been generated during timebase adjustment";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
field {
name = "Rising edge timestamp";
descritpion = "Timestamp value taken on rising clock edge (full word)";
prefix = "val_r";
type = SLV;
size = 28;
};
field {
name = "Falling edge timestamp";
description = "Timestamp value taken on falling clock edge (few LSBs)";
prefix = "val_f";
type = SLV;
size = 4;
};
field {
name ="Physical port ID";
description = "Identifier of the TXTSU port to which came the timestamp. There may be multiple timestamps sharing the same FID value for broadcast/multicast packets.";
prefix = "pid";
type = SLV;
size = 5;
align= 16;
};
field {
name = "Frame ID";
description = "OOB Frame Identifier. Used to associate the timestamp value with transmitted packet.";
prefix = "fid";
type = SLV;
size = 16;
align = 16;
};
field {
name = "Timestamp (possibly) incorrect";
description = "1: This timestamp may be incorrect (generated during PPS adjustment)\
0: Timestamp is correct.";
prefix = "incorrect";
type = BIT;
};
};
-- TXTSU interrupts
irq {
name = "TXTSU fifo not-empty";
description = "Interrupt active when TXTSU shared FIFO contains any timestamps.";
prefix = "nempty";
trigger = LEVEL_1;
};
};
\ No newline at end of file
modules/wrsw_txtsu/wrsw_txtsu_pkg.vhd deleted 100644 → 0
View file @ a216d4a9
library ieee;
use ieee.std_logic_1164.all;
package wrsw_txtsu_pkg is
type t_txtsu_timestamp is record
stb : std_logic;
tsval : std_logic_vector(31 downto 0);
port_id : std_logic_vector(5 downto 0);
frame_id : std_logic_vector(15 downto 0);
incorrect : std_logic;
end record;
type t_txtsu_timestamp_array is array(integer range <>) of t_txtsu_timestamp;
end wrsw_txtsu_pkg;
modules/wrsw_txtsu/wrsw_txtsu_wb.vhd deleted 100644 → 0
View file @ a216d4a9
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Shared TX Timestamping Unit (TXTSU)
---------------------------------------------------------------------------------------
-- File : wrsw_txtsu_wb.vhd
-- Author : auto-generated by wbgen2 from wrsw_txtsu.wb
-- Created : Fri Jul 27 18:10:33 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_txtsu.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
entity wrsw_txtsu_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
-- FIFO write request
txtsu_tsf_wr_req_i : in std_logic;
-- FIFO full flag
txtsu_tsf_wr_full_o : out std_logic;
-- FIFO empty flag
txtsu_tsf_wr_empty_o : out std_logic;
txtsu_tsf_val_r_i : in std_logic_vector(27 downto 0);
txtsu_tsf_val_f_i : in std_logic_vector(3 downto 0);
txtsu_tsf_pid_i : in std_logic_vector(4 downto 0);
txtsu_tsf_fid_i : in std_logic_vector(15 downto 0);
txtsu_tsf_incorrect_i : in std_logic;
irq_nempty_i : in std_logic
);
end wrsw_txtsu_wb;
architecture syn of wrsw_txtsu_wb is
signal txtsu_tsf_rst_n : std_logic ;
signal txtsu_tsf_in_int : std_logic_vector(53 downto 0);
signal txtsu_tsf_out_int : std_logic_vector(53 downto 0);
signal txtsu_tsf_rdreq_int : std_logic ;
signal txtsu_tsf_rdreq_int_d0 : std_logic ;
signal eic_idr_int : std_logic_vector(0 downto 0);
signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(0 downto 0);
signal eic_ier_write_int : std_logic ;
signal eic_imr_int : std_logic_vector(0 downto 0);
signal eic_isr_clear_int : std_logic_vector(0 downto 0);
signal eic_isr_status_int : std_logic_vector(0 downto 0);
signal eic_irq_ack_int : std_logic_vector(0 downto 0);
signal eic_isr_write_int : std_logic ;
signal txtsu_tsf_full_int : std_logic ;
signal txtsu_tsf_empty_int : std_logic ;
signal txtsu_tsf_usedw_int : std_logic_vector(7 downto 0);
signal irq_inputs_vector_int : std_logic_vector(0 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
txtsu_tsf_rdreq_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001" =>
if (wb_we_i = '1') then
eic_ier_write_int <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= eic_imr_int(0);
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
end if;
rddata_reg(0) <= eic_isr_status_int(0);
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
if (wb_we_i = '1') then
end if;
if (txtsu_tsf_rdreq_int_d0 = '0') then
txtsu_tsf_rdreq_int <= not txtsu_tsf_rdreq_int;
else
rddata_reg(27 downto 0) <= txtsu_tsf_out_int(27 downto 0);
rddata_reg(31 downto 28) <= txtsu_tsf_out_int(31 downto 28);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(4 downto 0) <= txtsu_tsf_out_int(36 downto 32);
rddata_reg(31 downto 16) <= txtsu_tsf_out_int(52 downto 37);
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= txtsu_tsf_out_int(53);
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= txtsu_tsf_full_int;
rddata_reg(17) <= txtsu_tsf_empty_int;
rddata_reg(7 downto 0) <= txtsu_tsf_usedw_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- extra code for reg/fifo/mem: Timestamp FIFO
txtsu_tsf_in_int(27 downto 0) <= txtsu_tsf_val_r_i;
txtsu_tsf_in_int(31 downto 28) <= txtsu_tsf_val_f_i;
txtsu_tsf_in_int(36 downto 32) <= txtsu_tsf_pid_i;
txtsu_tsf_in_int(52 downto 37) <= txtsu_tsf_fid_i;
txtsu_tsf_in_int(53) <= txtsu_tsf_incorrect_i;
txtsu_tsf_rst_n <= rst_n_i;
txtsu_tsf_INST : wbgen2_fifo_sync
generic map (
g_size => 256,
g_width => 54,
g_usedw_size => 8
)
port map (
wr_req_i => txtsu_tsf_wr_req_i,
wr_full_o => txtsu_tsf_wr_full_o,
wr_empty_o => txtsu_tsf_wr_empty_o,
rd_full_o => txtsu_tsf_full_int,
rd_empty_o => txtsu_tsf_empty_int,
rd_usedw_o => txtsu_tsf_usedw_int,
rd_req_i => txtsu_tsf_rdreq_int,
rst_n_i => txtsu_tsf_rst_n,
clk_i => clk_sys_i,
wr_data_i => txtsu_tsf_in_int,
rd_data_o => txtsu_tsf_out_int
);
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(0) <= wrdata_reg(0);
-- extra code for reg/fifo/mem: Interrupt enable register
eic_ier_int(0) <= wrdata_reg(0);
-- extra code for reg/fifo/mem: Interrupt status register
eic_isr_clear_int(0) <= wrdata_reg(0);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
eic_irq_controller_inst : wbgen2_eic
generic map (
g_num_interrupts => 1,
g_irq00_mode => 3,
g_irq01_mode => 0,
g_irq02_mode => 0,
g_irq03_mode => 0,
g_irq04_mode => 0,
g_irq05_mode => 0,
g_irq06_mode => 0,
g_irq07_mode => 0,
g_irq08_mode => 0,
g_irq09_mode => 0,
g_irq0a_mode => 0,
g_irq0b_mode => 0,
g_irq0c_mode => 0,
g_irq0d_mode => 0,
g_irq0e_mode => 0,
g_irq0f_mode => 0,
g_irq10_mode => 0,
g_irq11_mode => 0,
g_irq12_mode => 0,
g_irq13_mode => 0,
g_irq14_mode => 0,
g_irq15_mode => 0,
g_irq16_mode => 0,
g_irq17_mode => 0,
g_irq18_mode => 0,
g_irq19_mode => 0,
g_irq1a_mode => 0,
g_irq1b_mode => 0,
g_irq1c_mode => 0,
g_irq1d_mode => 0,
g_irq1e_mode => 0,
g_irq1f_mode => 0
)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
irq_i => irq_inputs_vector_int,
irq_ack_o => eic_irq_ack_int,
reg_imr_o => eic_imr_int,
reg_ier_i => eic_ier_int,
reg_ier_wr_stb_i => eic_ier_write_int,
reg_idr_i => eic_idr_int,
reg_idr_wr_stb_i => eic_idr_write_int,
reg_isr_o => eic_isr_status_int,
reg_isr_i => eic_isr_clear_int,
reg_isr_wr_stb_i => eic_isr_write_int,
wb_irq_o => wb_int_o
);
irq_inputs_vector_int(0) <= irq_nempty_i;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 0
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
txtsu_tsf_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then
txtsu_tsf_rdreq_int_d0 <= txtsu_tsf_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 2
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
modules/wrsw_txtsu/xwrsw_txtsu.vhd deleted 100644 → 0
View file @ a216d4a9
-------------------------------------------------------------------------------
-- Title : TX Timestamping Unit
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : xwrsw_txtsu.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-26
-- Last update: 2012-03-16
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description: Shared timestamping unit for all switch endpoints. It collects
-- TX timestamps with associated frame identifiers and puts them (along
-- with the identifier of requesting port) in a shared FIFO. Each FIFO entry
-- contains:
-- - Frame ID value (from OOB field of transmitted frame)
-- - Timestamp value (from the endpoint)
-- - Port ID value (ID of the TXTSU port to which the timstamp+frame id came).
-- FIFO is accessible from the Wishbone bus. An IRQ (level-active) is triggered
-- when the FIFO is not empty. The driver reads TX timestamps (with associated
-- port and frame identifiers) and passes them to PTP daemon.
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-04-26 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
use work.wrsw_txtsu_pkg.all;
entity xwrsw_tx_tsu is
generic (
g_num_ports : integer := 10;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
-- reference clock / 2 (62.5 MHz). All signals below are synchronous to this clock
clk_sys_i : in std_logic;
-- sync reset, active LO
rst_n_i : in std_logic;
-------------------------------------------------------------------------------
-- TX timestamp interface (from endpoints)
-------------------------------------------------------------------------------
-- frame identifier inputs (separate for each port)
timestamps_i : in t_txtsu_timestamp_array(g_num_ports-1 downto 0);
timestamps_ack_o : out std_logic_vector(g_num_ports -1 downto 0);
-------------------------------------------------------------------------------
-- Wishbone bus
-------------------------------------------------------------------------------
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out
);
end xwrsw_tx_tsu;
architecture syn of xwrsw_tx_tsu is
component wrsw_txtsu_wb
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
txtsu_tsf_wr_req_i : in std_logic;
txtsu_tsf_wr_full_o : out std_logic;
txtsu_tsf_wr_empty_o : out std_logic;
txtsu_tsf_val_r_i : in std_logic_vector(27 downto 0);
txtsu_tsf_val_f_i : in std_logic_vector(3 downto 0);
txtsu_tsf_pid_i : in std_logic_vector(4 downto 0);
txtsu_tsf_fid_i : in std_logic_vector(15 downto 0);
txtsu_tsf_incorrect_i : in std_logic;
irq_nempty_i : in std_logic);
end component;
signal txtsu_tsf_wr_req : std_logic;
signal txtsu_tsf_wr_full : std_logic;
signal txtsu_tsf_wr_empty : std_logic;
signal txtsu_tsf_val_r : std_logic_vector(27 downto 0);
signal txtsu_tsf_val_f : std_logic_vector(3 downto 0);
signal txtsu_tsf_pid : std_logic_vector(4 downto 0);
signal txtsu_tsf_fid : std_logic_vector(15 downto 0);
signal txtsu_tsf_incorrect : std_logic;
signal irq_nempty : std_logic;
signal scan_cntr : unsigned(4 downto 0);
type t_txtsu_state is (TSU_SCAN, TSU_ACK);
signal state : t_txtsu_state;
signal cur_ep : integer;
signal wb_out : t_wishbone_slave_out;
signal wb_in : t_wishbone_slave_in;
begin -- syn
U_Adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => PIPELINED,
g_master_granularity => WORD,
g_slave_use_struct => true,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
master_i => wb_out,
master_o => wb_in,
slave_i => wb_i,
slave_o => wb_o);
cur_ep <= to_integer(scan_cntr);
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
state <= TSU_SCAN;
scan_cntr <= (others => '0');
txtsu_tsf_wr_req <= '0';
timestamps_ack_o <= (others => '0');
else
case state is
when TSU_SCAN =>
if(timestamps_i(cur_ep).stb = '1') then
timestamps_ack_o(cur_ep) <= '1';
state <= TSU_ACK;
if(txtsu_tsf_wr_full = '0') then
txtsu_tsf_pid <= timestamps_i(cur_ep).port_id(4 downto 0);
txtsu_tsf_fid <= timestamps_i(cur_ep).frame_id;
txtsu_tsf_val_f <= timestamps_i(cur_ep).tsval(31 downto 28);
txtsu_tsf_val_r <= timestamps_i(cur_ep).tsval(27 downto 0);
txtsu_tsf_incorrect <= timestamps_i(cur_ep).incorrect;
txtsu_tsf_wr_req <= '1';
end if;
else
if(scan_cntr = g_num_ports-1)then
scan_cntr <= (others => '0');
else
scan_cntr <= scan_cntr + 1;
end if;
end if;
when TSU_ACK =>
timestamps_ack_o(cur_ep) <= '0';
txtsu_tsf_wr_req <= '0';
state <= TSU_SCAN;
if(scan_cntr = g_num_ports-1)then
scan_cntr <= (others => '0');
else
scan_cntr <= scan_cntr + 1;
end if;
when others => null;
end case;
end if;
end if;
end process;
U_WB_SLAVE : wrsw_txtsu_wb
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_in.adr(2 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_stall_o => wb_out.stall,
wb_int_o => wb_out.int,
txtsu_tsf_wr_req_i => txtsu_tsf_wr_req,
txtsu_tsf_wr_full_o => txtsu_tsf_wr_full,
txtsu_tsf_wr_empty_o => txtsu_tsf_wr_empty,
txtsu_tsf_val_r_i => txtsu_tsf_val_r,
txtsu_tsf_val_f_i => txtsu_tsf_val_f,
txtsu_tsf_pid_i => txtsu_tsf_pid,
txtsu_tsf_fid_i => txtsu_tsf_fid,
txtsu_tsf_incorrect_i => txtsu_tsf_incorrect,
irq_nempty_i => irq_nempty);
irq_nempty <= not txtsu_tsf_wr_empty;
end syn;
platform/xilinx/Manifest.py 0 → 100644
View file @ 069fb021
files = [ "wr_xilinx_pkg.vhd" ]
modules = {"local" : ["wr_gtp_phy", "chipscope"]}
platform/xilinx/wr_gtp_phy/Manifest.py 0 → 100644
View file @ 069fb021
files = [ "gtp_bitslide.vhd",
"gtp_phase_align.vhd",
"gtp_phase_align_virtex6.vhd",
"gtx_reset.vhd",
"whiterabbitgtx_wrapper_gtx.vhd",
# "whiterabbitgtp_wrapper.vhd",
"whiterabbitgtp_wrapper_tile.vhd",
"wr_gtp_phy_spartan6.vhd",
"wr_gtx_phy_virtex6.vhd"];
platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd 0 → 100644
View file @ 069fb021
-------------------------------------------------------------------------------
-- Title : Deterministic Xilinx GTP wrapper - bitslide state machine
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : gtp_bitslide.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-09-12
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Module implements a manual bitslide alignment state machine and
-- provides the obtained bitslide value to the MAC.
-------------------------------------------------------------------------------
--
-- Original EASE design (c) 2010 NIKHEF / Peter Jansweijer and Henk Peek
-- VHDL port (c) 2010 CERN / Tomasz Wlostowski
--
-- <license>
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-18 0.4 twlostow Ported EASE design to VHDL
-- 2011-02-07 0.5 twlostow Verified on Spartan6 GTP
-- 2011-09-12 0.6 twlostow Virtex6 port
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gtp_bitslide is
generic (
-- set to non-zero value to enable some simulation speedups (reduce delays)
g_simulation : integer;
g_target : string := "spartan6");
port (
gtp_rst_i : in std_logic;
-- GTP
gtp_rx_clk_i : in std_logic;
-- '1' indicates that the GTP has detected a comma in the incoming serial stream
gtp_rx_comma_det_i : in std_logic;
gtp_rx_byte_is_aligned_i : in std_logic;
-- GTP ready flag (PLL locked and RX signal present)
serdes_ready_i : in std_logic;
-- GTP manual bitslip control line
gtp_rx_slide_o : out std_logic;
-- GTP CDR reset, asserted when the link is lost to set the bitslide to a known
-- value
gtp_rx_cdr_rst_o : out std_logic;
-- Current bitslide, in UIs
bitslide_o : out std_logic_vector(4 downto 0);
-- '1' when the bitsliding has been completed and the link is up
synced_o : out std_logic
);
end gtp_bitslide;
architecture behavioral of gtp_bitslide is
function f_eval_sync_detect_threshold
return integer is
begin
if(g_simulation /= 0) then
return 256;
elsif(g_target = "spartan6") then
return 8192;
else
return 16384;
end if;
end f_eval_sync_detect_threshold;
function f_eval_pause_tics return integer is
begin
if(g_target = "spartan6") then
return 31;
else
return 63;
end if;
end f_eval_pause_tics;
constant c_pause_tics : integer := f_eval_pause_tics;
constant c_sync_detect_threshold : integer := f_eval_sync_detect_threshold;
type t_bitslide_fsm_state is (S_SYNC_LOST, S_STABILIZE, S_SLIDE, S_PAUSE, S_GOT_SYNC, S_RESET_CDR);
signal cur_slide : unsigned(4 downto 0);
signal state : t_bitslide_fsm_state;
signal counter : unsigned(15 downto 0);
signal commas_missed : unsigned(1 downto 0);
begin -- behavioral
p_do_slide : process(gtp_rx_clk_i, gtp_rst_i)
begin
if gtp_rst_i = '1' then
state <= S_SYNC_LOST;
gtp_rx_slide_o <= '0';
counter <= (others => '0');
synced_o <= '0';
gtp_rx_cdr_rst_o <= '0';
elsif rising_edge(gtp_rx_clk_i) then
if(serdes_ready_i = '0') then
state <= S_SYNC_LOST;
end if;
case state is
-- State: synchronization lost. Waits until a comma pattern is detected
when S_SYNC_LOST =>
cur_slide <= (others => '0');
counter <= (others => '0');
gtp_rx_slide_o <= '0';
synced_o <= '0';
gtp_rx_cdr_rst_o <= '0';
commas_missed <= (others => '0');
if(gtp_rx_comma_det_i = '1') then
state <= S_STABILIZE;
end if;
-- State: stabilize:
when S_STABILIZE =>
if(gtp_rx_comma_det_i = '1') then
counter <= counter + 1;
commas_missed <= (others => '0');
else
commas_missed <= commas_missed + 1;
if(commas_missed(1) = '1') then
state <= S_SYNC_LOST;
end if;
end if;
if(counter = to_unsigned(c_sync_detect_threshold, counter'length)) then
counter <= (others => '0');
state <= S_PAUSE;
end if;
if(serdes_ready_i = '0') then
state <= S_SYNC_LOST;
end if;
when S_SLIDE =>
cur_slide <= cur_slide + 1;
gtp_rx_slide_o <= '1';
counter <= (others => '0');
state <= S_PAUSE;
if(serdes_ready_i = '0') then
state <= S_SYNC_LOST;
end if;
when S_PAUSE =>
counter <= counter + 1;
gtp_rx_slide_o <= '0';
if(counter = to_unsigned(c_pause_tics, counter'length)) then
if(gtp_rx_byte_is_aligned_i = '0') then
state <= S_SLIDE;
else
state <= S_GOT_SYNC;
end if;
end if;
when S_GOT_SYNC =>
gtp_rx_slide_o <= '0';
bitslide_o <= std_logic_vector(cur_slide);
synced_o <= '1';
if(gtp_rx_byte_is_aligned_i = '0' or serdes_ready_i = '0') then
gtp_rx_cdr_rst_o <= '1';
state <= S_SYNC_LOST;
end if;
when others => null;
end case;
end if;
end process;
end behavioral;
platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd 0 → 100644
View file @ 069fb021
------------------------------------------------------------------------------
-- Title : Deterministic Xilinx GTP wrapper - TX phase alignment
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : gtp_phase_align.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-09-12
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: TX phase alignment state machine, as recommended by Xilinx.
-------------------------------------------------------------------------------
--
-- Original EASE design (c) 2010 NIKHEF / Peter Jansweijer and Henk Peek
-- VHDL port (c) 2010 CERN / Tomasz Wlostowski
--
-- <license>
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-18 0.4 twlostow Ported EASE design to VHDL
-- 2011-02-07 0.5 twlostow Verified on Spartan6 GTP
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gtp_phase_align is
generic
(g_simulation : integer);
port (
gtp_rst_i : in std_logic;
gtp_tx_clk_i : in std_logic;
gtp_tx_en_pma_phase_align_o : out std_logic;
gtp_tx_pma_set_phase_o : out std_logic;
align_en_i : in std_logic;
align_done_o : out std_logic
);
end gtp_phase_align;
architecture behavioral of gtp_phase_align is
constant c_wait_en_phase_align : integer := 32;
constant c_wait_set_phase_align : integer := 512;
constant c_phase_align_duration : integer := 8192;
type t_align_state is (S_ALIGN_IDLE, S_ALIGN_PAUSE, S_ALIGN_WAIT, S_ALIGN_SET_PHASE, S_ALIGN_DONE);
signal counter : unsigned(13 downto 0);
signal state : t_align_state;
begin -- behavioral
p_align : process(gtp_tx_clk_i, gtp_rst_i)
begin
if rising_edge(gtp_tx_clk_i) then
if gtp_rst_i = '1' then
gtp_tx_en_pma_phase_align_o <= '0';
gtp_tx_pma_set_phase_o <= '0';
counter <= (others => '0');
align_done_o <= '0';
state <= S_ALIGN_IDLE;
else
if(align_en_i = '0') then
state <= S_ALIGN_IDLE;
else
case (state) is
when S_ALIGN_IDLE =>
gtp_tx_en_pma_phase_align_o <= '0';
gtp_tx_pma_set_phase_o <= '0';
counter <= (others => '0');
align_done_o <= '0';
if(align_en_i = '1') then
state <= S_ALIGN_PAUSE;
end if;
when S_ALIGN_PAUSE =>
counter <= counter + 1;
if(counter = to_unsigned(c_wait_en_phase_align, counter'length)) then
state <= S_ALIGN_WAIT;
end if;
when S_ALIGN_WAIT =>
gtp_tx_en_pma_phase_align_o <= '1';
counter <= counter + 1;
if(counter = to_unsigned(c_wait_en_phase_align + c_wait_set_phase_align, counter'length)) then
state <= S_ALIGN_SET_PHASE;
end if;
when S_ALIGN_SET_PHASE =>
counter <= counter +1;
gtp_tx_pma_set_phase_o <= '1';
if(counter = to_unsigned(c_wait_en_phase_align + c_wait_set_phase_align + c_phase_align_duration, counter'length)) then
state <= S_ALIGN_DONE;
end if;
when S_ALIGN_DONE =>
gtp_tx_pma_set_phase_o <= '0';
counter <= (others => '0');
align_done_o <= '1';
when others => null;
end case;
end if;
end if;
end if;
end process;
end behavioral;
platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd 0 → 100644
View file @ 069fb021
------------------------------------------------------------------------------
-- Title : Deterministic Xilinx GTP wrapper - TX phase alignment
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : gtp_phase_align.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-09-12
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: TX phase alignment state machine, as recommended by Xilinx.
-------------------------------------------------------------------------------
--
-- Original EASE design (c) 2010 NIKHEF / Peter Jansweijer and Henk Peek
-- VHDL port (c) 2010 CERN / Tomasz Wlostowski
--
-- <license>
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-18 0.4 twlostow Ported EASE design to VHDL
-- 2011-02-07 0.5 twlostow Verified on Spartan6 GTP
-- 2011-09-12 0.6 twlostow Virtex6 port
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gtp_phase_align_virtex6 is
generic
(g_simulation : integer);
port (
gtp_rst_i : in std_logic;
gtp_tx_clk_i : in std_logic;
gtp_tx_en_pma_phase_align_o : out std_logic;
gtp_tx_pma_set_phase_o : out std_logic;
gtp_tx_dly_align_disable_o : out std_logic;
gtp_tx_dly_align_reset_o : out std_logic;
align_en_i : in std_logic;
align_done_o : out std_logic
);
end gtp_phase_align_virtex6;
architecture behavioral of gtp_phase_align_virtex6 is
constant c_dly_align_reset_time : integer := 16;
constant c_wait_set_phase_align : integer := 32;
constant c_phase_align_duration : integer := 8192;
type t_align_state is (S_ALIGN_IDLE, S_DLY_ALIGN_RESET, S_ALIGN_WAIT, S_ALIGN_SET_PHASE, S_ALIGN_DONE);
signal counter : unsigned(13 downto 0);
signal state : t_align_state;
begin -- behavioral
p_align : process(gtp_tx_clk_i, gtp_rst_i)
begin
if rising_edge(gtp_tx_clk_i) then
if gtp_rst_i = '1' then
gtp_tx_en_pma_phase_align_o <= '0';
gtp_tx_pma_set_phase_o <= '0';
gtp_tx_dly_align_reset_o <= '0';
gtp_tx_dly_align_disable_o <= '1';
counter <= (others => '0');
align_done_o <= '0';
state <= S_ALIGN_IDLE;
else
if(align_en_i = '0') then
state <= S_ALIGN_IDLE;
else
case (state) is
when S_ALIGN_IDLE =>
gtp_tx_en_pma_phase_align_o <= '0';
gtp_tx_pma_set_phase_o <= '0';
gtp_tx_dly_align_reset_o <= '0';
gtp_tx_dly_align_disable_o <= '1';
counter <= (others => '0');
align_done_o <= '0';
if(align_en_i = '1') then
state <= S_DLY_ALIGN_RESET;
end if;
when S_DLY_ALIGN_RESET =>
counter <= counter + 1;
gtp_tx_dly_align_reset_o <= '1';
gtp_tx_dly_align_disable_o <= '1';
if(counter = to_unsigned(c_dly_align_reset_time, counter'length)) then
state <= S_ALIGN_WAIT;
end if;
when S_ALIGN_WAIT =>
gtp_tx_dly_align_reset_o <= '0';
gtp_tx_dly_align_disable_o <= '1';
gtp_tx_en_pma_phase_align_o <= '1';
counter <= counter + 1;
if(counter = to_unsigned(c_dly_align_reset_time + c_wait_set_phase_align, counter'length)) then
state <= S_ALIGN_SET_PHASE;
end if;
when S_ALIGN_SET_PHASE =>
counter <= counter +1;
gtp_tx_pma_set_phase_o <= '1';
if(counter = to_unsigned(c_dly_align_reset_time + c_wait_set_phase_align + c_phase_align_duration, counter'length)) then
state <= S_ALIGN_DONE;
end if;
when S_ALIGN_DONE =>
gtp_tx_pma_set_phase_o <= '0';
gtp_tx_dly_align_disable_o <= '0';
counter <= (others => '0');
align_done_o <= '1';
when others => null;
end case;
end if;
end if;
end if;
end process;
end behavioral;
platform/xilinx/wr_gtp_phy/gtx_reset.vhd 0 → 100644
View file @ 069fb021
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gtx_reset is
port (
clk_tx_i : in std_logic;
rst_i : in std_logic;
txpll_lockdet_i : in std_logic;
gtx_test_o : out std_logic_vector(12 downto 0)
);
end gtx_reset;
architecture behavioral of gtx_reset is
type t_state is (IDLE, PAUSE, FIRST_RST, PAUSE2, SECOND_RST, DONE);
signal state : t_state;
signal counter : unsigned(15 downto 0);
begin -- behavioral
process(clk_tx_i)
begin
if rising_edge(clk_tx_i) then
if rst_i = '1' then
state <= IDLE;
counter <= (others => '0');
else
if(txpll_lockdet_i = '0') then
state <= IDLE;
else
case state is
when IDLE =>
counter <= (others => '0');
gtx_test_o <= "1000000000000";
if(txpll_lockdet_i = '1') then
state <= PAUSE;
end if;
when PAUSE =>
counter <= counter + 1;
gtx_test_o <= "1000000000000";
if(counter = 1024) then
state <= FIRST_RST;
end if;
when FIRST_RST =>
counter <= counter + 1;
gtx_test_o <= "1000000000010";
if(counter = 1024 + 256) then
state <= PAUSE2;
end if;
when PAUSE2=>
counter <= counter + 1;
gtx_test_o <= "1000000000000";
if(counter = 1024 + 2*256) then
state <= SECOND_RST;
end if;
when SECOND_RST =>
counter <= counter + 1;
gtx_test_o <= "1000000000010";
if(counter = 1024 + 3*256) then
state <= DONE;
end if;
when DONE =>
gtx_test_o <= "1000000000000";
end case;
end if;
end if;
end if;
end process;
end behavioral;
platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper.vhd 0 → 100644
View file @ 069fb021
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.4
-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
-- / / Filename : whiterabbitgtp_wrapper.vhd
-- /___/ /\ Timestamp :
-- \ \ / \
-- \___\/\___\
--
--
-- Module WHITERABBITGTP_WRAPPER (a GTP Wrapper)
-- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
--
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of,
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
--***************************** Entity Declaration ****************************
entity WHITERABBITGTP_WRAPPER is
generic
(
-- Simulation attributes
WRAPPER_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
WRAPPER_CLK25_DIVIDER_0 : integer := 5;
WRAPPER_CLK25_DIVIDER_1 : integer := 5;
WRAPPER_PLL_DIVSEL_FB_0 : integer := 2;
WRAPPER_PLL_DIVSEL_FB_1 : integer := 2;
WRAPPER_PLL_DIVSEL_REF_0 : integer := 1;
WRAPPER_PLL_DIVSEL_REF_1 : integer := 1;
WRAPPER_SIMULATION : integer := 0 -- Set to 1 for simulation
);
port
(
--_________________________________________________________________________
--_________________________________________________________________________
--TILE0 (X1_Y0)
------------------------ Loopback and Powerdown Ports ----------------------
TILE0_LOOPBACK0_IN : in std_logic_vector(2 downto 0);
TILE0_LOOPBACK1_IN : in std_logic_vector(2 downto 0);
--------------------------------- PLL Ports --------------------------------
TILE0_CLK00_IN : in std_logic;
TILE0_CLK01_IN : in std_logic;
TILE0_GTPRESET0_IN : in std_logic;
TILE0_GTPRESET1_IN : in std_logic;
TILE0_PLLLKDET0_OUT : out std_logic;
TILE0_RESETDONE0_OUT : out std_logic;
TILE0_RESETDONE1_OUT : out std_logic;
TILE0_REFCLKOUT0_OUT : out std_logic;
TILE0_REFCLKOUT1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
TILE0_RXCHARISK0_OUT : out std_logic;
TILE0_RXCHARISK1_OUT : out std_logic;
TILE0_RXDISPERR0_OUT : out std_logic;
TILE0_RXDISPERR1_OUT : out std_logic;
TILE0_RXNOTINTABLE0_OUT : out std_logic;
TILE0_RXNOTINTABLE1_OUT : out std_logic;
--------------- Receive Ports - Comma Detection and Alignment --------------
TILE0_RXBYTEISALIGNED0_OUT : out std_logic;
TILE0_RXBYTEISALIGNED1_OUT : out std_logic;
TILE0_RXCOMMADET0_OUT : out std_logic;
TILE0_RXCOMMADET1_OUT : out std_logic;
TILE0_RXSLIDE0_IN : in std_logic;
TILE0_RXSLIDE1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
TILE0_RXDATA0_OUT : out std_logic_vector(7 downto 0);
TILE0_RXDATA1_OUT : out std_logic_vector(7 downto 0);
TILE0_RXUSRCLK0_IN : in std_logic;
TILE0_RXUSRCLK1_IN : in std_logic;
TILE0_RXUSRCLK20_IN : in std_logic;
TILE0_RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
TILE0_RXCDRRESET0_IN : in std_logic;
TILE0_RXCDRRESET1_IN : in std_logic;
TILE0_RXN0_IN : in std_logic;
TILE0_RXN1_IN : in std_logic;
TILE0_RXP0_IN : in std_logic;
TILE0_RXP1_IN : in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
TILE0_GTPCLKFBEAST_OUT : out std_logic_vector(1 downto 0);
TILE0_GTPCLKFBWEST_OUT : out std_logic_vector(1 downto 0);
TILE0_GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
TILE0_GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TILE0_TXCHARISK0_IN : in std_logic;
TILE0_TXCHARISK1_IN : in std_logic;
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TILE0_TXENPMAPHASEALIGN0_IN : in std_logic;
TILE0_TXENPMAPHASEALIGN1_IN : in std_logic;
TILE0_TXPMASETPHASE0_IN : in std_logic;
TILE0_TXPMASETPHASE1_IN : in std_logic;
------------------ Transmit Ports - TX Data Path interface -----------------
TILE0_TXDATA0_IN : in std_logic_vector(7 downto 0);
TILE0_TXDATA1_IN : in std_logic_vector(7 downto 0);
TILE0_TXUSRCLK0_IN : in std_logic;
TILE0_TXUSRCLK1_IN : in std_logic;
TILE0_TXUSRCLK20_IN : in std_logic;
TILE0_TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TILE0_TXN0_OUT : out std_logic;
TILE0_TXN1_OUT : out std_logic;
TILE0_TXP0_OUT : out std_logic;
TILE0_TXP1_OUT : out std_logic
);
end WHITERABBITGTP_WRAPPER;
architecture RTL of WHITERABBITGTP_WRAPPER is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of RTL : architecture is "WHITERABBITGTP_WRAPPER,s6_gtpwizard_v1_4,{gtp0_protocol_file=Start_from_scratch,gtp1_protocol_file=Use_GTP0_settings}";
--***************************** Signal Declarations *****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
signal tile0_plllkdet0_i : std_logic;
signal tile0_plllkdet1_i : std_logic;
signal tile0_plllkdet0_i2 : std_logic;
--*************************** Component Declarations **************************
component WHITERABBITGTP_WRAPPER_TILE
generic
(
-- Simulation attributes
TILE_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
TILE_CLK25_DIVIDER_0 : integer := 4;
TILE_CLK25_DIVIDER_1 : integer := 4;
TILE_PLL_DIVSEL_FB_0 : integer := 5;
TILE_PLL_DIVSEL_FB_1 : integer := 5;
TILE_PLL_DIVSEL_REF_0 : integer := 2;
TILE_PLL_DIVSEL_REF_1 : integer := 2;
--
TILE_PLL_SOURCE_0 : string := "PLL0";
TILE_PLL_SOURCE_1 : string := "PLL1"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0_IN : in std_logic_vector(2 downto 0);
LOOPBACK1_IN : in std_logic_vector(2 downto 0);
REFCLKOUT0_OUT : out std_logic;
REFCLKOUT1_OUT : out std_logic;
--------------------------------- PLL Ports --------------------------------
CLK00_IN : in std_logic;
CLK01_IN : in std_logic;
GTPRESET0_IN : in std_logic;
GTPRESET1_IN : in std_logic;
PLLLKDET0_OUT : out std_logic;
PLLLKDET1_OUT : out std_logic;
RESETDONE0_OUT : out std_logic;
RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT : out std_logic;
RXCHARISK1_OUT : out std_logic;
RXDISPERR0_OUT : out std_logic;
RXDISPERR1_OUT : out std_logic;
RXNOTINTABLE0_OUT : out std_logic;
RXNOTINTABLE1_OUT : out std_logic;
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0_OUT : out std_logic;
RXBYTEISALIGNED1_OUT : out std_logic;
RXCOMMADET0_OUT : out std_logic;
RXCOMMADET1_OUT : out std_logic;
RXSLIDE0_IN : in std_logic;
RXSLIDE1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT : out std_logic_vector(7 downto 0);
RXDATA1_OUT : out std_logic_vector(7 downto 0);
RXUSRCLK0_IN : in std_logic;
RXUSRCLK1_IN : in std_logic;
RXUSRCLK20_IN : in std_logic;
RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXCDRRESET0_IN : in std_logic;
RXCDRRESET1_IN : in std_logic;
RXN0_IN : in std_logic;
RXN1_IN : in std_logic;
RXP0_IN : in std_logic;
RXP1_IN : in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST_OUT : out std_logic_vector(1 downto 0);
GTPCLKFBWEST_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARISK0_IN : in std_logic;
TXCHARISK1_IN : in std_logic;
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXENPMAPHASEALIGN0_IN : in std_logic;
TXENPMAPHASEALIGN1_IN : in std_logic;
TXPMASETPHASE0_IN : in std_logic;
TXPMASETPHASE1_IN : in std_logic;
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN : in std_logic_vector(7 downto 0);
TXDATA1_IN : in std_logic_vector(7 downto 0);
TXUSRCLK0_IN : in std_logic;
TXUSRCLK1_IN : in std_logic;
TXUSRCLK20_IN : in std_logic;
TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT : out std_logic;
TXN1_OUT : out std_logic;
TXP0_OUT : out std_logic;
TXP1_OUT : out std_logic
);
end component;
--********************************* Main Body of Code**************************
begin
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
simulation : if WRAPPER_SIMULATION = 1 generate
TILE0_PLLLKDET0_OUT <= tile0_plllkdet0_i2;
process
begin
wait until tile0_plllkdet0_i'event;
if(tile0_plllkdet0_i = '1') then
tile0_plllkdet0_i2 <= '1' after 100 ns;
else
tile0_plllkdet0_i2 <= tile0_plllkdet0_i;
end if;
end process;
end generate simulation;
implementation : if WRAPPER_SIMULATION = 0 generate
TILE0_PLLLKDET0_OUT <= tile0_plllkdet0_i;
end generate implementation;
--------------------------- Tile Instances -------------------------------
--_________________________________________________________________________
--_________________________________________________________________________
--TILE0 (X1_Y0)
tile0_whiterabbitgtp_wrapper_i : WHITERABBITGTP_WRAPPER_TILE
generic map
(
-- Simulation attributes
TILE_SIM_GTPRESET_SPEEDUP => WRAPPER_SIM_GTPRESET_SPEEDUP,
TILE_CLK25_DIVIDER_0 => WRAPPER_CLK25_DIVIDER_0,
TILE_CLK25_DIVIDER_1 => WRAPPER_CLK25_DIVIDER_1,
TILE_PLL_DIVSEL_FB_0 => WRAPPER_PLL_DIVSEL_FB_0,
TILE_PLL_DIVSEL_FB_1 => WRAPPER_PLL_DIVSEL_FB_1,
TILE_PLL_DIVSEL_REF_0 => WRAPPER_PLL_DIVSEL_REF_0,
TILE_PLL_DIVSEL_REF_1 => WRAPPER_PLL_DIVSEL_REF_1,
--
TILE_PLL_SOURCE_0 => "PLL0",
TILE_PLL_SOURCE_1 => "PLL0"
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0_IN => TILE0_LOOPBACK0_IN,
LOOPBACK1_IN => TILE0_LOOPBACK1_IN,
--------------------------------- PLL Ports --------------------------------
REFCLKOUT1_OUT => REFCLKOUT1_OUT,
REFCLKOUT0_OUT => REFCLKOUT0_OUT,
CLK00_IN => TILE0_CLK00_IN,
CLK01_IN => TILE0_CLK01_IN,
GTPRESET0_IN => TILE0_GTPRESET0_IN,
GTPRESET1_IN => TILE0_GTPRESET1_IN,
PLLLKDET0_OUT => tile0_plllkdet0_i,
PLLLKDET1_OUT => tile0_plllkdet1_i,
RESETDONE0_OUT => TILE0_RESETDONE0_OUT,
RESETDONE1_OUT => TILE0_RESETDONE1_OUT,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT => TILE0_RXCHARISK0_OUT,
RXCHARISK1_OUT => TILE0_RXCHARISK1_OUT,
RXDISPERR0_OUT => TILE0_RXDISPERR0_OUT,
RXDISPERR1_OUT => TILE0_RXDISPERR1_OUT,
RXNOTINTABLE0_OUT => TILE0_RXNOTINTABLE0_OUT,
RXNOTINTABLE1_OUT => TILE0_RXNOTINTABLE1_OUT,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0_OUT => TILE0_RXBYTEISALIGNED0_OUT,
RXBYTEISALIGNED1_OUT => TILE0_RXBYTEISALIGNED1_OUT,
RXCOMMADET0_OUT => TILE0_RXCOMMADET0_OUT,
RXCOMMADET1_OUT => TILE0_RXCOMMADET1_OUT,
RXSLIDE0_IN => TILE0_RXSLIDE0_IN,
RXSLIDE1_IN => TILE0_RXSLIDE1_IN,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT => TILE0_RXDATA0_OUT,
RXDATA1_OUT => TILE0_RXDATA1_OUT,
RXUSRCLK0_IN => TILE0_RXUSRCLK0_IN,
RXUSRCLK1_IN => TILE0_RXUSRCLK1_IN,
RXUSRCLK20_IN => TILE0_RXUSRCLK20_IN,
RXUSRCLK21_IN => TILE0_RXUSRCLK21_IN,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXCDRRESET0_IN => TILE0_RXCDRRESET0_IN,
RXCDRRESET1_IN => TILE0_RXCDRRESET1_IN,
RXN0_IN => TILE0_RXN0_IN,
RXN1_IN => TILE0_RXN1_IN,
RXP0_IN => TILE0_RXP0_IN,
RXP1_IN => TILE0_RXP1_IN,
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST_OUT => TILE0_GTPCLKFBEAST_OUT,
GTPCLKFBWEST_OUT => TILE0_GTPCLKFBWEST_OUT,
GTPCLKOUT0_OUT => TILE0_GTPCLKOUT0_OUT,
GTPCLKOUT1_OUT => TILE0_GTPCLKOUT1_OUT,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARISK0_IN => TILE0_TXCHARISK0_IN,
TXCHARISK1_IN => TILE0_TXCHARISK1_IN,
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXENPMAPHASEALIGN0_IN => TILE0_TXENPMAPHASEALIGN0_IN,
TXENPMAPHASEALIGN1_IN => TILE0_TXENPMAPHASEALIGN1_IN,
TXPMASETPHASE0_IN => TILE0_TXPMASETPHASE0_IN,
TXPMASETPHASE1_IN => TILE0_TXPMASETPHASE1_IN,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN => TILE0_TXDATA0_IN,
TXDATA1_IN => TILE0_TXDATA1_IN,
TXUSRCLK0_IN => TILE0_TXUSRCLK0_IN,
TXUSRCLK1_IN => TILE0_TXUSRCLK1_IN,
TXUSRCLK20_IN => TILE0_TXUSRCLK20_IN,
TXUSRCLK21_IN => TILE0_TXUSRCLK21_IN,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT => TILE0_TXN0_OUT,
TXN1_OUT => TILE0_TXN1_OUT,
TXP0_OUT => TILE0_TXP0_OUT,
TXP1_OUT => TILE0_TXP1_OUT
);
end RTL;
platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd 0 → 100644
View file @ 069fb021
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
--***************************** Entity Declaration ****************************
entity WHITERABBITGTP_WRAPPER_TILE_SPARTAN6 is
generic
(
TILE_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
TILE_CLK25_DIVIDER_0 : integer := 4;
TILE_CLK25_DIVIDER_1 : integer := 4;
TILE_PLL_DIVSEL_FB_0 : integer := 5;
TILE_PLL_DIVSEL_FB_1 : integer := 5;
TILE_PLL_DIVSEL_REF_0 : integer := 2;
TILE_PLL_DIVSEL_REF_1 : integer := 2;
TILE_PLL_SOURCE_0 : string := "PLL0";
TILE_PLL_SOURCE_1 : string := "PLL1"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0_IN : in std_logic_vector(2 downto 0);
LOOPBACK1_IN : in std_logic_vector(2 downto 0);
REFCLKOUT0_OUT : out std_logic;
REFCLKOUT1_OUT : out std_logic;
--------------------------------- PLL Ports --------------------------------
CLK00_IN : in std_logic;
CLK01_IN : in std_logic;
CLK10_IN : in std_logic;
CLK11_IN : in std_logic;
GTPRESET0_IN : in std_logic;
GTPRESET1_IN : in std_logic;
PLLLKDET0_OUT : out std_logic;
PLLLKDET1_OUT : out std_logic;
RESETDONE0_OUT : out std_logic;
RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT : out std_logic;
RXCHARISK1_OUT : out std_logic;
RXDISPERR0_OUT : out std_logic;
RXDISPERR1_OUT : out std_logic;
RXNOTINTABLE0_OUT : out std_logic;
RXNOTINTABLE1_OUT : out std_logic;
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0_OUT : out std_logic;
RXBYTEISALIGNED1_OUT : out std_logic;
RXCOMMADET0_OUT : out std_logic;
RXCOMMADET1_OUT : out std_logic;
RXSLIDE0_IN : in std_logic;
RXSLIDE1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT : out std_logic_vector(7 downto 0);
RXDATA1_OUT : out std_logic_vector(7 downto 0);
RXUSRCLK0_IN : in std_logic;
RXUSRCLK1_IN : in std_logic;
RXUSRCLK20_IN : in std_logic;
RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXCDRRESET0_IN : in std_logic;
RXCDRRESET1_IN : in std_logic;
RXN0_IN : in std_logic;
RXN1_IN : in std_logic;
RXP0_IN : in std_logic;
RXP1_IN : in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST_OUT : out std_logic_vector(1 downto 0);
GTPCLKFBWEST_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARISK0_IN : in std_logic;
TXCHARISK1_IN : in std_logic;
TXCHARDISPMODE0_IN: in std_logic;
TXCHARDISPMODE1_IN: in std_logic;
TXCHARDISPVAL0_IN: in std_logic;
TXCHARDISPVAL1_IN: in std_logic;
TXRUNDISP0_OUT : out std_logic_vector(3 downto 0);
TXRUNDISP1_OUT : out std_logic_vector(3 downto 0);
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXENPMAPHASEALIGN0_IN : in std_logic;
TXENPMAPHASEALIGN1_IN : in std_logic;
TXPMASETPHASE0_IN : in std_logic;
TXPMASETPHASE1_IN : in std_logic;
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN : in std_logic_vector(7 downto 0);
TXDATA1_IN : in std_logic_vector(7 downto 0);
TXUSRCLK0_IN : in std_logic;
TXUSRCLK1_IN : in std_logic;
TXUSRCLK20_IN : in std_logic;
TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT : out std_logic;
TXN1_OUT : out std_logic;
TXP0_OUT : out std_logic;
TXP1_OUT : out std_logic
);
end WHITERABBITGTP_WRAPPER_TILE_SPARTAN6;
architecture RTL of WHITERABBITGTP_WRAPPER_TILE_SPARTAN6 is
--**************************** Signal Declarations ****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
-- RX Datapath signals
signal rxdata0_i : std_logic_vector(31 downto 0);
signal rxchariscomma0_float_i : std_logic_vector(2 downto 0);
signal rxcharisk0_float_i : std_logic_vector(2 downto 0);
signal rxdisperr0_float_i : std_logic_vector(2 downto 0);
signal rxnotintable0_float_i : std_logic_vector(2 downto 0);
signal rxrundisp0_float_i : std_logic_vector(2 downto 0);
-- TX Datapath signals
signal txdata0_i : std_logic_vector(31 downto 0);
signal txkerr0_float_i : std_logic_vector(2 downto 0);
signal txrundisp0_float_i : std_logic_vector(2 downto 0);
-- RX Datapath signals
signal rxdata1_i : std_logic_vector(31 downto 0);
signal rxchariscomma1_float_i : std_logic_vector(2 downto 0);
signal rxcharisk1_float_i : std_logic_vector(2 downto 0);
signal rxdisperr1_float_i : std_logic_vector(2 downto 0);
signal rxnotintable1_float_i : std_logic_vector(2 downto 0);
signal rxrundisp1_float_i : std_logic_vector(2 downto 0);
-- TX Datapath signals
signal txdata1_i : std_logic_vector(31 downto 0);
signal txkerr1_float_i : std_logic_vector(2 downto 0);
signal txrundisp1_float_i : std_logic_vector(2 downto 0);
--******************************** Main Body of Code***************************
begin
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
tied_to_vcc_vec_i(63 downto 0) <= (others => '1');
------------------- GTP Datapath byte mapping -----------------
RXDATA0_OUT <= rxdata0_i(7 downto 0);
txdata0_i <= (tied_to_ground_vec_i(23 downto 0) & TXDATA0_IN);
RXDATA1_OUT <= rxdata1_i(7 downto 0);
txdata1_i <= (tied_to_ground_vec_i(23 downto 0) & TXDATA1_IN);
----------------------------- GTPA1_DUAL Instance --------------------------
gtpa1_dual_i : GTPA1_DUAL
generic map
(
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS => (true),
SIM_TX_ELEC_IDLE_LEVEL => ("X"),
SIM_VERSION => ("2.0"),
SIM_REFCLK0_SOURCE => ("000"),
SIM_REFCLK1_SOURCE => ("000"),
SIM_GTPRESET_SPEEDUP => (TILE_SIM_GTPRESET_SPEEDUP),
CLK25_DIVIDER_0 => (TILE_CLK25_DIVIDER_0),
CLK25_DIVIDER_1 => (TILE_CLK25_DIVIDER_1),
PLL_DIVSEL_FB_0 => (TILE_PLL_DIVSEL_FB_0),
PLL_DIVSEL_FB_1 => (TILE_PLL_DIVSEL_FB_1),
PLL_DIVSEL_REF_0 => (TILE_PLL_DIVSEL_REF_0),
PLL_DIVSEL_REF_1 => (TILE_PLL_DIVSEL_REF_1),
--PLL Attributes
CLKINDC_B_0 => (true),
CLKRCV_TRST_0 => (true),
OOB_CLK_DIVIDER_0 => (4),
PLL_COM_CFG_0 => (x"21680a"),
PLL_CP_CFG_0 => (x"00"),
PLL_RXDIVSEL_OUT_0 => (2),
PLL_SATA_0 => (false),
PLL_SOURCE_0 => (TILE_PLL_SOURCE_0),
PLL_TXDIVSEL_OUT_0 => (2),
PLLLKDET_CFG_0 => ("111"),
--
CLKINDC_B_1 => (true),
CLKRCV_TRST_1 => (true),
OOB_CLK_DIVIDER_1 => (4),
PLL_COM_CFG_1 => (x"21680a"),
PLL_CP_CFG_1 => (x"00"),
PLL_RXDIVSEL_OUT_1 => (2),
PLL_SATA_1 => (false),
PLL_SOURCE_1 => (TILE_PLL_SOURCE_1),
PLL_TXDIVSEL_OUT_1 => (2),
PLLLKDET_CFG_1 => ("111"),
PMA_COM_CFG_EAST => (x"000008000"),
PMA_COM_CFG_WEST => (x"000008000"),
TST_ATTR_0 => (x"00000000"),
TST_ATTR_1 => (x"00000000"),
--TX Interface Attributes
CLK_OUT_GTP_SEL_0 => ("REFCLKPLL0"),
TX_TDCC_CFG_0 => ("00"),
CLK_OUT_GTP_SEL_1 => ("REFCLKPLL1"),
TX_TDCC_CFG_1 => ("00"),
--TX Buffer and Phase Alignment Attributes
PMA_TX_CFG_0 => (x"80082"),
TX_BUFFER_USE_0 => (false),
TX_XCLK_SEL_0 => ("TXUSR"),
TXRX_INVERT_0 => ("111"),
PMA_TX_CFG_1 => (x"80082"),
TX_BUFFER_USE_1 => (false),
TX_XCLK_SEL_1 => ("TXUSR"),
TXRX_INVERT_1 => ("111"),
--TX Driver and OOB signalling Attributes
CM_TRIM_0 => ("00"),
TX_IDLE_DELAY_0 => ("011"),
CM_TRIM_1 => ("00"),
TX_IDLE_DELAY_1 => ("011"),
--TX PIPE/SATA Attributes
COM_BURST_VAL_0 => ("1111"),
COM_BURST_VAL_1 => ("1111"),
--RX Driver,OOB signalling,Coupling and Eq,CDR Attributes
AC_CAP_DIS_0 => (true),
OOBDETECT_THRESHOLD_0 => ("110"),
PMA_CDR_SCAN_0 => (x"6404040"),
PMA_RX_CFG_0 => (x"05ce048"),
PMA_RXSYNC_CFG_0 => (x"00"),
RCV_TERM_GND_0 => (false),
RCV_TERM_VTTRX_0 => (true),
RXEQ_CFG_0 => ("01111011"),
TERMINATION_CTRL_0 => ("10100"),
TERMINATION_OVRD_0 => (false),
TX_DETECT_RX_CFG_0 => (x"1832"),
AC_CAP_DIS_1 => (true),
OOBDETECT_THRESHOLD_1 => ("110"),
PMA_CDR_SCAN_1 => (x"6404040"),
PMA_RX_CFG_1 => (x"05ce048"),
PMA_RXSYNC_CFG_1 => (x"00"),
RCV_TERM_GND_1 => (false),
RCV_TERM_VTTRX_1 => (true),
RXEQ_CFG_1 => ("01111011"),
TERMINATION_CTRL_1 => ("10100"),
TERMINATION_OVRD_1 => (false),
TX_DETECT_RX_CFG_1 => (x"1832"),
--PRBS Detection Attributes
RXPRBSERR_LOOPBACK_0 => ('0'),
RXPRBSERR_LOOPBACK_1 => ('0'),
--Comma Detection and Alignment Attributes
ALIGN_COMMA_WORD_0 => (1),
COMMA_10B_ENABLE_0 => ("1111111111"),
DEC_MCOMMA_DETECT_0 => (false),
DEC_PCOMMA_DETECT_0 => (false),
DEC_VALID_COMMA_ONLY_0 => (true),
MCOMMA_10B_VALUE_0 => ("1010000011"),
MCOMMA_DETECT_0 => (true),
PCOMMA_10B_VALUE_0 => ("0101111100"),
PCOMMA_DETECT_0 => (true),
RX_SLIDE_MODE_0 => ("PCS"),
ALIGN_COMMA_WORD_1 => (1),
COMMA_10B_ENABLE_1 => ("1111111111"),
DEC_MCOMMA_DETECT_1 => (false),
DEC_PCOMMA_DETECT_1 => (false),
DEC_VALID_COMMA_ONLY_1 => (true),
MCOMMA_10B_VALUE_1 => ("1010000011"),
MCOMMA_DETECT_1 => (true),
PCOMMA_10B_VALUE_1 => ("0101111100"),
PCOMMA_DETECT_1 => (true),
RX_SLIDE_MODE_1 => ("PCS"),
--RX Loss-of-sync State Machine Attributes
RX_LOS_INVALID_INCR_0 => (8),
RX_LOS_THRESHOLD_0 => (128),
RX_LOSS_OF_SYNC_FSM_0 => (false),
RX_LOS_INVALID_INCR_1 => (8),
RX_LOS_THRESHOLD_1 => (128),
RX_LOSS_OF_SYNC_FSM_1 => (false),
--RX Elastic Buffer and Phase alignment Attributes
RX_BUFFER_USE_0 => (true),
RX_EN_IDLE_RESET_BUF_0 => (true),
RX_IDLE_HI_CNT_0 => ("1000"),
RX_IDLE_LO_CNT_0 => ("0000"),
RX_XCLK_SEL_0 => ("RXREC"),
RX_BUFFER_USE_1 => (true),
RX_EN_IDLE_RESET_BUF_1 => (true),
RX_IDLE_HI_CNT_1 => ("1000"),
RX_IDLE_LO_CNT_1 => ("0000"),
RX_XCLK_SEL_1 => ("RXREC"),
--Clock Correction Attributes
CLK_COR_ADJ_LEN_0 => (1),
CLK_COR_DET_LEN_0 => (1),
CLK_COR_INSERT_IDLE_FLAG_0 => (false),
CLK_COR_KEEP_IDLE_0 => (false),
CLK_COR_MAX_LAT_0 => (18),
CLK_COR_MIN_LAT_0 => (16),
CLK_COR_PRECEDENCE_0 => (true),
CLK_COR_REPEAT_WAIT_0 => (0),
CLK_COR_SEQ_1_1_0 => ("0100000000"),
CLK_COR_SEQ_1_2_0 => ("0000000000"),
CLK_COR_SEQ_1_3_0 => ("0000000000"),
CLK_COR_SEQ_1_4_0 => ("0000000000"),
CLK_COR_SEQ_1_ENABLE_0 => ("0000"),
CLK_COR_SEQ_2_1_0 => ("0100000000"),
CLK_COR_SEQ_2_2_0 => ("0000000000"),
CLK_COR_SEQ_2_3_0 => ("0000000000"),
CLK_COR_SEQ_2_4_0 => ("0000000000"),
CLK_COR_SEQ_2_ENABLE_0 => ("0000"),
CLK_COR_SEQ_2_USE_0 => (false),
CLK_CORRECT_USE_0 => (false),
RX_DECODE_SEQ_MATCH_0 => (true),
CLK_COR_ADJ_LEN_1 => (1),
CLK_COR_DET_LEN_1 => (1),
CLK_COR_INSERT_IDLE_FLAG_1 => (false),
CLK_COR_KEEP_IDLE_1 => (false),
CLK_COR_MAX_LAT_1 => (18),
CLK_COR_MIN_LAT_1 => (16),
CLK_COR_PRECEDENCE_1 => (true),
CLK_COR_REPEAT_WAIT_1 => (0),
CLK_COR_SEQ_1_1_1 => ("0100000000"),
CLK_COR_SEQ_1_2_1 => ("0000000000"),
CLK_COR_SEQ_1_3_1 => ("0000000000"),
CLK_COR_SEQ_1_4_1 => ("0000000000"),
CLK_COR_SEQ_1_ENABLE_1 => ("0000"),
CLK_COR_SEQ_2_1_1 => ("0100000000"),
CLK_COR_SEQ_2_2_1 => ("0000000000"),
CLK_COR_SEQ_2_3_1 => ("0000000000"),
CLK_COR_SEQ_2_4_1 => ("0000000000"),
CLK_COR_SEQ_2_ENABLE_1 => ("0000"),
CLK_COR_SEQ_2_USE_1 => (false),
CLK_CORRECT_USE_1 => (false),
RX_DECODE_SEQ_MATCH_1 => (true),
--Channel Bonding Attributes
CHAN_BOND_1_MAX_SKEW_0 => (1),
CHAN_BOND_2_MAX_SKEW_0 => (1),
CHAN_BOND_KEEP_ALIGN_0 => (false),
CHAN_BOND_SEQ_1_1_0 => ("0000000000"),
CHAN_BOND_SEQ_1_2_0 => ("0000000000"),
CHAN_BOND_SEQ_1_3_0 => ("0000000000"),
CHAN_BOND_SEQ_1_4_0 => ("0000000000"),
CHAN_BOND_SEQ_1_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_1_0 => ("0000000000"),
CHAN_BOND_SEQ_2_2_0 => ("0000000000"),
CHAN_BOND_SEQ_2_3_0 => ("0000000000"),
CHAN_BOND_SEQ_2_4_0 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_USE_0 => (false),
CHAN_BOND_SEQ_LEN_0 => (1),
RX_EN_MODE_RESET_BUF_0 => (true),
CHAN_BOND_1_MAX_SKEW_1 => (1),
CHAN_BOND_2_MAX_SKEW_1 => (1),
CHAN_BOND_KEEP_ALIGN_1 => (false),
CHAN_BOND_SEQ_1_1_1 => ("0000000000"),
CHAN_BOND_SEQ_1_2_1 => ("0000000000"),
CHAN_BOND_SEQ_1_3_1 => ("0000000000"),
CHAN_BOND_SEQ_1_4_1 => ("0000000000"),
CHAN_BOND_SEQ_1_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_1_1 => ("0000000000"),
CHAN_BOND_SEQ_2_2_1 => ("0000000000"),
CHAN_BOND_SEQ_2_3_1 => ("0000000000"),
CHAN_BOND_SEQ_2_4_1 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_USE_1 => (false),
CHAN_BOND_SEQ_LEN_1 => (1),
RX_EN_MODE_RESET_BUF_1 => (true),
--RX PCI Express Attributes
CB2_INH_CC_PERIOD_0 => (8),
CDR_PH_ADJ_TIME_0 => ("01010"),
PCI_EXPRESS_MODE_0 => (false),
RX_EN_IDLE_HOLD_CDR_0 => (false),
RX_EN_IDLE_RESET_FR_0 => (true),
RX_EN_IDLE_RESET_PH_0 => (true),
RX_STATUS_FMT_0 => ("PCIE"),
TRANS_TIME_FROM_P2_0 => (x"03c"),
TRANS_TIME_NON_P2_0 => (x"19"),
TRANS_TIME_TO_P2_0 => (x"064"),
CB2_INH_CC_PERIOD_1 => (8),
CDR_PH_ADJ_TIME_1 => ("01010"),
PCI_EXPRESS_MODE_1 => (false),
RX_EN_IDLE_HOLD_CDR_1 => (false),
RX_EN_IDLE_RESET_FR_1 => (true),
RX_EN_IDLE_RESET_PH_1 => (true),
RX_STATUS_FMT_1 => ("PCIE"),
TRANS_TIME_FROM_P2_1 => (x"03c"),
TRANS_TIME_NON_P2_1 => (x"19"),
TRANS_TIME_TO_P2_1 => (x"064"),
--RX SATA Attributes
SATA_BURST_VAL_0 => ("100"),
SATA_IDLE_VAL_0 => ("100"),
SATA_MAX_BURST_0 => (9),
SATA_MAX_INIT_0 => (27),
SATA_MAX_WAKE_0 => (9),
SATA_MIN_BURST_0 => (5),
SATA_MIN_INIT_0 => (15),
SATA_MIN_WAKE_0 => (5),
SATA_BURST_VAL_1 => ("100"),
SATA_IDLE_VAL_1 => ("100"),
SATA_MAX_BURST_1 => (9),
SATA_MAX_INIT_1 => (27),
SATA_MAX_WAKE_1 => (9),
SATA_MIN_BURST_1 => (5),
SATA_MIN_INIT_1 => (15),
SATA_MIN_WAKE_1 => (5)
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0 => LOOPBACK0_IN,
LOOPBACK1 => LOOPBACK1_IN,
RXPOWERDOWN0 => tied_to_ground_vec_i(1 downto 0),
RXPOWERDOWN1 => tied_to_ground_vec_i(1 downto 0),
TXPOWERDOWN0 => tied_to_ground_vec_i(1 downto 0),
TXPOWERDOWN1 => tied_to_ground_vec_i(1 downto 0),
--------------------------------- PLL Ports --------------------------------
CLK00 => CLK00_IN,
CLK01 => CLK01_IN,
CLK10 => CLK10_IN,
CLK11 => CLK11_IN,
CLKINEAST0 => tied_to_ground_i,
CLKINEAST1 => tied_to_ground_i,
CLKINWEST0 => tied_to_ground_i,
CLKINWEST1 => tied_to_ground_i,
GCLK00 => tied_to_ground_i,
GCLK01 => tied_to_ground_i,
GCLK10 => tied_to_ground_i,
GCLK11 => tied_to_ground_i,
GTPRESET0 => GTPRESET0_IN,
GTPRESET1 => GTPRESET1_IN,
GTPTEST0 => "00010000",
GTPTEST1 => "00010000",
INTDATAWIDTH0 => tied_to_vcc_i,
INTDATAWIDTH1 => tied_to_vcc_i,
PLLCLK00 => tied_to_ground_i,
PLLCLK01 => tied_to_ground_i,
PLLCLK10 => tied_to_ground_i,
PLLCLK11 => tied_to_ground_i,
PLLLKDET0 => PLLLKDET0_OUT,
PLLLKDET1 => PLLLKDET1_OUT,
PLLLKDETEN0 => tied_to_vcc_i,
PLLLKDETEN1 => tied_to_vcc_i,
PLLPOWERDOWN0 => tied_to_ground_i,
PLLPOWERDOWN1 => tied_to_ground_i,
REFCLKOUT0 => REFCLKOUT0_OUT,
REFCLKOUT1 => REFCLKOUT1_OUT,
REFCLKPLL0 => open,
REFCLKPLL1 => open,
REFCLKPWRDNB0 => tied_to_vcc_i,
REFCLKPWRDNB1 => tied_to_vcc_i,
REFSELDYPLL0 => tied_to_ground_vec_i(2 downto 0),
REFSELDYPLL1 => tied_to_ground_vec_i(2 downto 0),
RESETDONE0 => RESETDONE0_OUT,
RESETDONE1 => RESETDONE1_OUT,
TSTCLK0 => tied_to_ground_i,
TSTCLK1 => tied_to_ground_i,
TSTIN0 => tied_to_ground_vec_i(11 downto 0),
TSTIN1 => tied_to_ground_vec_i(11 downto 0),
TSTOUT0 => open,
TSTOUT1 => open,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA0 => open,
RXCHARISCOMMA1 => open,
RXCHARISK0(3 downto 1) => rxcharisk0_float_i,
RXCHARISK0(0) => RXCHARISK0_OUT,
RXCHARISK1(3 downto 1) => rxcharisk1_float_i,
RXCHARISK1(0) => RXCHARISK1_OUT,
RXDEC8B10BUSE0 => tied_to_vcc_i,
RXDEC8B10BUSE1 => tied_to_vcc_i,
RXDISPERR0(3 downto 1) => rxdisperr0_float_i,
RXDISPERR0(0) => RXDISPERR0_OUT,
RXDISPERR1(3 downto 1) => rxdisperr1_float_i,
RXDISPERR1(0) => RXDISPERR1_OUT,
RXNOTINTABLE0(3 downto 1) => rxnotintable0_float_i,
RXNOTINTABLE0(0) => RXNOTINTABLE0_OUT,
RXNOTINTABLE1(3 downto 1) => rxnotintable1_float_i,
RXNOTINTABLE1(0) => RXNOTINTABLE1_OUT,
RXRUNDISP0 => open,
RXRUNDISP1 => open,
USRCODEERR0 => tied_to_ground_i,
USRCODEERR1 => tied_to_ground_i,
---------------------- Receive Ports - Channel Bonding ---------------------
RXCHANBONDSEQ0 => open,
RXCHANBONDSEQ1 => open,
RXCHANISALIGNED0 => open,
RXCHANISALIGNED1 => open,
RXCHANREALIGN0 => open,
RXCHANREALIGN1 => open,
RXCHBONDI => tied_to_ground_vec_i(2 downto 0),
RXCHBONDMASTER0 => tied_to_ground_i,
RXCHBONDMASTER1 => tied_to_ground_i,
RXCHBONDO => open,
RXCHBONDSLAVE0 => tied_to_ground_i,
RXCHBONDSLAVE1 => tied_to_ground_i,
RXENCHANSYNC0 => tied_to_ground_i,
RXENCHANSYNC1 => tied_to_ground_i,
---------------------- Receive Ports - Clock Correction --------------------
RXCLKCORCNT0 => open,
RXCLKCORCNT1 => open,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0 => RXBYTEISALIGNED0_OUT,
RXBYTEISALIGNED1 => RXBYTEISALIGNED1_OUT,
RXBYTEREALIGN0 => open,
RXBYTEREALIGN1 => open,
RXCOMMADET0 => RXCOMMADET0_OUT,
RXCOMMADET1 => RXCOMMADET1_OUT,
RXCOMMADETUSE0 => tied_to_vcc_i,
RXCOMMADETUSE1 => tied_to_vcc_i,
RXENMCOMMAALIGN0 => tied_to_ground_i,
RXENMCOMMAALIGN1 => tied_to_ground_i,
RXENPCOMMAALIGN0 => tied_to_ground_i,
RXENPCOMMAALIGN1 => tied_to_ground_i,
RXSLIDE0 => RXSLIDE0_IN,
RXSLIDE1 => RXSLIDE1_IN,
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET0 => tied_to_ground_i,
PRBSCNTRESET1 => tied_to_ground_i,
RXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
RXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
RXPRBSERR0 => open,
RXPRBSERR1 => open,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0 => rxdata0_i,
RXDATA1 => rxdata1_i,
RXDATAWIDTH0 => "00",
RXDATAWIDTH1 => "00",
RXRECCLK0 => open,
RXRECCLK1 => open,
RXRESET0 => tied_to_ground_i,
RXRESET1 => tied_to_ground_i,
RXUSRCLK0 => RXUSRCLK0_IN,
RXUSRCLK1 => RXUSRCLK1_IN,
RXUSRCLK20 => RXUSRCLK20_IN,
RXUSRCLK21 => RXUSRCLK21_IN,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE0 => tied_to_ground_i,
GATERXELECIDLE1 => tied_to_ground_i,
IGNORESIGDET0 => tied_to_ground_i,
IGNORESIGDET1 => tied_to_ground_i,
RCALINEAST => tied_to_ground_vec_i(4 downto 0),
RCALINWEST => tied_to_ground_vec_i(4 downto 0),
RCALOUTEAST => open,
RCALOUTWEST => open,
RXCDRRESET0 => RXCDRRESET0_IN,
RXCDRRESET1 => RXCDRRESET1_IN,
RXELECIDLE0 => open,
RXELECIDLE1 => open,
RXEQMIX0 => "00",
RXEQMIX1 => "00",
RXN0 => RXN0_IN,
RXN1 => RXN1_IN,
RXP0 => RXP0_IN,
RXP1 => RXP1_IN,
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
RXBUFRESET0 => tied_to_ground_i,
RXBUFRESET1 => tied_to_ground_i,
RXBUFSTATUS0 => open,
RXBUFSTATUS1 => open,
RXENPMAPHASEALIGN0 => tied_to_ground_i,
RXENPMAPHASEALIGN1 => tied_to_ground_i,
RXPMASETPHASE0 => tied_to_ground_i,
RXPMASETPHASE1 => tied_to_ground_i,
RXSTATUS0 => open,
RXSTATUS1 => open,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC0 => open,
RXLOSSOFSYNC1 => open,
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0 => open,
PHYSTATUS1 => open,
RXVALID0 => open,
RXVALID1 => open,
-------------------- Receive Ports - RX Polarity Control -------------------
RXPOLARITY0 => tied_to_ground_i,
RXPOLARITY1 => tied_to_ground_i,
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR => tied_to_ground_vec_i(7 downto 0),
DCLK => tied_to_ground_i,
DEN => tied_to_ground_i,
DI => tied_to_ground_vec_i(15 downto 0),
DRDY => open,
DRPDO => open,
DWE => tied_to_ground_i,
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST => GTPCLKFBEAST_OUT,
GTPCLKFBSEL0EAST => "10",
GTPCLKFBSEL0WEST => "00",
GTPCLKFBSEL1EAST => "11",
GTPCLKFBSEL1WEST => "01",
GTPCLKFBWEST => GTPCLKFBWEST_OUT,
GTPCLKOUT0 => GTPCLKOUT0_OUT,
GTPCLKOUT1 => GTPCLKOUT1_OUT,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXBYPASS8B10B0 => tied_to_ground_vec_i(3 downto 0),
TXBYPASS8B10B1 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPMODE0(0) => TXCHARDISPMODE0_IN,
TXCHARDISPMODE0(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARDISPMODE1(0) => TXCHARDISPMODE1_IN,
TXCHARDISPMODE1(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARDISPVAL0(0) => TXCHARDISPVAL0_IN,
TXCHARDISPVAL0(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARDISPVAL1(0) => TXCHARDISPVAL1_IN,
TXCHARDISPVAL1(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARISK0(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARISK0(0) => TXCHARISK0_IN,
TXCHARISK1(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARISK1(0) => TXCHARISK1_IN,
TXENC8B10BUSE0 => tied_to_vcc_i,
TXENC8B10BUSE1 => tied_to_vcc_i,
TXKERR0 => open,
TXKERR1 => open,
TXRUNDISP0 => TXRUNDISP0_OUT,
TXRUNDISP1 => TXRUNDISP1_OUT,
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXBUFSTATUS0 => open,
TXBUFSTATUS1 => open,
TXENPMAPHASEALIGN0 => TXENPMAPHASEALIGN0_IN,
TXENPMAPHASEALIGN1 => TXENPMAPHASEALIGN1_IN,
TXPMASETPHASE0 => TXPMASETPHASE0_IN,
TXPMASETPHASE1 => TXPMASETPHASE1_IN,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0 => txdata0_i,
TXDATA1 => txdata1_i,
TXDATAWIDTH0 => "00",
TXDATAWIDTH1 => "00",
TXOUTCLK0 => open,
TXOUTCLK1 => open,
TXRESET0 => tied_to_ground_i,
TXRESET1 => tied_to_ground_i,
TXUSRCLK0 => TXUSRCLK0_IN,
TXUSRCLK1 => TXUSRCLK1_IN,
TXUSRCLK20 => TXUSRCLK20_IN,
TXUSRCLK21 => TXUSRCLK21_IN,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXBUFDIFFCTRL0 => "101",
TXBUFDIFFCTRL1 => "101",
TXDIFFCTRL0 => "0110",
TXDIFFCTRL1 => "0110",
TXINHIBIT0 => tied_to_ground_i,
TXINHIBIT1 => tied_to_ground_i,
TXN0 => TXN0_OUT,
TXN1 => TXN1_OUT,
TXP0 => TXP0_OUT,
TXP1 => TXP1_OUT,
TXPREEMPHASIS0 => "000",
TXPREEMPHASIS1 => "000",
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
TXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
TXPRBSFORCEERR0 => tied_to_ground_i,
TXPRBSFORCEERR1 => tied_to_ground_i,
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY0 => tied_to_ground_i,
TXPOLARITY1 => tied_to_ground_i,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0 => tied_to_ground_i,
TXDETECTRX1 => tied_to_ground_i,
TXELECIDLE0 => tied_to_ground_i,
TXELECIDLE1 => tied_to_ground_i,
TXPDOWNASYNCH0 => tied_to_ground_i,
TXPDOWNASYNCH1 => tied_to_ground_i,
--------------------- Transmit Ports - TX Ports for SATA -------------------
TXCOMSTART0 => tied_to_ground_i,
TXCOMSTART1 => tied_to_ground_i,
TXCOMTYPE0 => tied_to_ground_i,
TXCOMTYPE1 => tied_to_ground_i
);
end RTL;
platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile_spartan6.vhd 0 → 100644
View file @ 069fb021
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***************************** Entity Declaration ****************************
entity WHITERABBITGTP_WRAPPER_TILE is
generic
(
TILE_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
TILE_CLK25_DIVIDER_0 : integer := 4;
TILE_CLK25_DIVIDER_1 : integer := 4;
TILE_PLL_DIVSEL_FB_0 : integer := 5;
TILE_PLL_DIVSEL_FB_1 : integer := 5;
TILE_PLL_DIVSEL_REF_0 : integer := 2;
TILE_PLL_DIVSEL_REF_1 : integer := 2;
TILE_PLL_SOURCE_0 : string := "PLL0";
TILE_PLL_SOURCE_1 : string := "PLL1"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0_IN : in std_logic_vector(2 downto 0);
LOOPBACK1_IN : in std_logic_vector(2 downto 0);
--------------------------------- PLL Ports --------------------------------
CLK00_IN : in std_logic;
CLK01_IN : in std_logic;
CLK10_IN : in std_logic;
CLK11_IN : in std_logic;
GTPRESET0_IN : in std_logic;
GTPRESET1_IN : in std_logic;
PLLLKDET0_OUT : out std_logic;
PLLLKDET1_OUT : out std_logic;
RESETDONE0_OUT : out std_logic;
RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT : out std_logic;
RXCHARISK1_OUT : out std_logic;
RXDISPERR0_OUT : out std_logic;
RXDISPERR1_OUT : out std_logic;
RXNOTINTABLE0_OUT : out std_logic;
RXNOTINTABLE1_OUT : out std_logic;
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0_OUT : out std_logic;
RXBYTEISALIGNED1_OUT : out std_logic;
RXCOMMADET0_OUT : out std_logic;
RXCOMMADET1_OUT : out std_logic;
RXSLIDE0_IN : in std_logic;
RXSLIDE1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT : out std_logic_vector(7 downto 0);
RXDATA1_OUT : out std_logic_vector(7 downto 0);
RXUSRCLK0_IN : in std_logic;
RXUSRCLK1_IN : in std_logic;
RXUSRCLK20_IN : in std_logic;
RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXCDRRESET0_IN : in std_logic;
RXCDRRESET1_IN : in std_logic;
RXN0_IN : in std_logic;
RXN1_IN : in std_logic;
RXP0_IN : in std_logic;
RXP1_IN : in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST_OUT : out std_logic_vector(1 downto 0);
GTPCLKFBWEST_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARISK0_IN : in std_logic;
TXCHARISK1_IN : in std_logic;
TXRUNDISP0_OUT : out std_logic_vector(3 downto 0);
TXRUNDISP1_OUT : out std_logic_vector(3 downto 0);
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXENPMAPHASEALIGN0_IN : in std_logic;
TXENPMAPHASEALIGN1_IN : in std_logic;
TXPMASETPHASE0_IN : in std_logic;
TXPMASETPHASE1_IN : in std_logic;
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN : in std_logic_vector(7 downto 0);
TXDATA1_IN : in std_logic_vector(7 downto 0);
TXUSRCLK0_IN : in std_logic;
TXUSRCLK1_IN : in std_logic;
TXUSRCLK20_IN : in std_logic;
TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT : out std_logic;
TXN1_OUT : out std_logic;
TXP0_OUT : out std_logic;
TXP1_OUT : out std_logic
);
end WHITERABBITGTP_WRAPPER_TILE;
architecture RTL of WHITERABBITGTP_WRAPPER_TILE is
--**************************** Signal Declarations ****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
-- RX Datapath signals
signal rxdata0_i : std_logic_vector(31 downto 0);
signal rxchariscomma0_float_i : std_logic_vector(2 downto 0);
signal rxcharisk0_float_i : std_logic_vector(2 downto 0);
signal rxdisperr0_float_i : std_logic_vector(2 downto 0);
signal rxnotintable0_float_i : std_logic_vector(2 downto 0);
signal rxrundisp0_float_i : std_logic_vector(2 downto 0);
-- TX Datapath signals
signal txdata0_i : std_logic_vector(31 downto 0);
signal txkerr0_float_i : std_logic_vector(2 downto 0);
signal txrundisp0_float_i : std_logic_vector(2 downto 0);
-- RX Datapath signals
signal rxdata1_i : std_logic_vector(31 downto 0);
signal rxchariscomma1_float_i : std_logic_vector(2 downto 0);
signal rxcharisk1_float_i : std_logic_vector(2 downto 0);
signal rxdisperr1_float_i : std_logic_vector(2 downto 0);
signal rxnotintable1_float_i : std_logic_vector(2 downto 0);
signal rxrundisp1_float_i : std_logic_vector(2 downto 0);
-- TX Datapath signals
signal txdata1_i : std_logic_vector(31 downto 0);
signal txkerr1_float_i : std_logic_vector(2 downto 0);
signal txrundisp1_float_i : std_logic_vector(2 downto 0);
--******************************** Main Body of Code***************************
begin
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
tied_to_vcc_vec_i(63 downto 0) <= (others => '1');
------------------- GTP Datapath byte mapping -----------------
RXDATA0_OUT <= rxdata0_i(7 downto 0);
txdata0_i <= (tied_to_ground_vec_i(23 downto 0) & TXDATA0_IN);
RXDATA1_OUT <= rxdata1_i(7 downto 0);
txdata1_i <= (tied_to_ground_vec_i(23 downto 0) & TXDATA1_IN);
----------------------------- GTPA1_DUAL Instance --------------------------
gtpa1_dual_i : GTPA1_DUAL
generic map
(
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS => (true),
SIM_TX_ELEC_IDLE_LEVEL => ("X"),
SIM_VERSION => ("2.0"),
SIM_REFCLK0_SOURCE => ("000"),
SIM_REFCLK1_SOURCE => ("000"),
SIM_GTPRESET_SPEEDUP => (TILE_SIM_GTPRESET_SPEEDUP),
CLK25_DIVIDER_0 => (TILE_CLK25_DIVIDER_0),
CLK25_DIVIDER_1 => (TILE_CLK25_DIVIDER_1),
PLL_DIVSEL_FB_0 => (TILE_PLL_DIVSEL_FB_0),
PLL_DIVSEL_FB_1 => (TILE_PLL_DIVSEL_FB_1),
PLL_DIVSEL_REF_0 => (TILE_PLL_DIVSEL_REF_0),
PLL_DIVSEL_REF_1 => (TILE_PLL_DIVSEL_REF_1),
--PLL Attributes
CLKINDC_B_0 => (true),
CLKRCV_TRST_0 => (true),
OOB_CLK_DIVIDER_0 => (4),
PLL_COM_CFG_0 => (x"21680a"),
PLL_CP_CFG_0 => (x"00"),
PLL_RXDIVSEL_OUT_0 => (2),
PLL_SATA_0 => (false),
PLL_SOURCE_0 => (TILE_PLL_SOURCE_0),
PLL_TXDIVSEL_OUT_0 => (2),
PLLLKDET_CFG_0 => ("111"),
--
CLKINDC_B_1 => (true),
CLKRCV_TRST_1 => (true),
OOB_CLK_DIVIDER_1 => (4),
PLL_COM_CFG_1 => (x"21680a"),
PLL_CP_CFG_1 => (x"00"),
PLL_RXDIVSEL_OUT_1 => (2),
PLL_SATA_1 => (false),
PLL_SOURCE_1 => (TILE_PLL_SOURCE_1),
PLL_TXDIVSEL_OUT_1 => (2),
PLLLKDET_CFG_1 => ("111"),
PMA_COM_CFG_EAST => (x"000008000"),
PMA_COM_CFG_WEST => (x"000008000"),
TST_ATTR_0 => (x"00000000"),
TST_ATTR_1 => (x"00000000"),
--TX Interface Attributes
CLK_OUT_GTP_SEL_0 => ("REFCLKPLL0"),
TX_TDCC_CFG_0 => ("00"),
CLK_OUT_GTP_SEL_1 => ("REFCLKPLL1"),
TX_TDCC_CFG_1 => ("00"),
--TX Buffer and Phase Alignment Attributes
PMA_TX_CFG_0 => (x"80082"),
TX_BUFFER_USE_0 => (false),
TX_XCLK_SEL_0 => ("TXUSR"),
TXRX_INVERT_0 => ("111"),
PMA_TX_CFG_1 => (x"80082"),
TX_BUFFER_USE_1 => (false),
TX_XCLK_SEL_1 => ("TXUSR"),
TXRX_INVERT_1 => ("111"),
--TX Driver and OOB signalling Attributes
CM_TRIM_0 => ("00"),
TX_IDLE_DELAY_0 => ("011"),
CM_TRIM_1 => ("00"),
TX_IDLE_DELAY_1 => ("011"),
--TX PIPE/SATA Attributes
COM_BURST_VAL_0 => ("1111"),
COM_BURST_VAL_1 => ("1111"),
--RX Driver,OOB signalling,Coupling and Eq,CDR Attributes
AC_CAP_DIS_0 => (true),
OOBDETECT_THRESHOLD_0 => ("110"),
PMA_CDR_SCAN_0 => (x"6404040"),
PMA_RX_CFG_0 => (x"05ce048"),
PMA_RXSYNC_CFG_0 => (x"00"),
RCV_TERM_GND_0 => (false),
RCV_TERM_VTTRX_0 => (true),
RXEQ_CFG_0 => ("01111011"),
TERMINATION_CTRL_0 => ("10100"),
TERMINATION_OVRD_0 => (false),
TX_DETECT_RX_CFG_0 => (x"1832"),
AC_CAP_DIS_1 => (true),
OOBDETECT_THRESHOLD_1 => ("110"),
PMA_CDR_SCAN_1 => (x"6404040"),
PMA_RX_CFG_1 => (x"05ce048"),
PMA_RXSYNC_CFG_1 => (x"00"),
RCV_TERM_GND_1 => (false),
RCV_TERM_VTTRX_1 => (true),
RXEQ_CFG_1 => ("01111011"),
TERMINATION_CTRL_1 => ("10100"),
TERMINATION_OVRD_1 => (false),
TX_DETECT_RX_CFG_1 => (x"1832"),
--PRBS Detection Attributes
RXPRBSERR_LOOPBACK_0 => ('0'),
RXPRBSERR_LOOPBACK_1 => ('0'),
--Comma Detection and Alignment Attributes
ALIGN_COMMA_WORD_0 => (1),
COMMA_10B_ENABLE_0 => ("1111111111"),
DEC_MCOMMA_DETECT_0 => (false),
DEC_PCOMMA_DETECT_0 => (false),
DEC_VALID_COMMA_ONLY_0 => (true),
MCOMMA_10B_VALUE_0 => ("1010000011"),
MCOMMA_DETECT_0 => (true),
PCOMMA_10B_VALUE_0 => ("0101111100"),
PCOMMA_DETECT_0 => (true),
RX_SLIDE_MODE_0 => ("PCS"),
ALIGN_COMMA_WORD_1 => (1),
COMMA_10B_ENABLE_1 => ("1111111111"),
DEC_MCOMMA_DETECT_1 => (false),
DEC_PCOMMA_DETECT_1 => (false),
DEC_VALID_COMMA_ONLY_1 => (true),
MCOMMA_10B_VALUE_1 => ("1010000011"),
MCOMMA_DETECT_1 => (true),
PCOMMA_10B_VALUE_1 => ("0101111100"),
PCOMMA_DETECT_1 => (true),
RX_SLIDE_MODE_1 => ("PCS"),
--RX Loss-of-sync State Machine Attributes
RX_LOS_INVALID_INCR_0 => (8),
RX_LOS_THRESHOLD_0 => (128),
RX_LOSS_OF_SYNC_FSM_0 => (false),
RX_LOS_INVALID_INCR_1 => (8),
RX_LOS_THRESHOLD_1 => (128),
RX_LOSS_OF_SYNC_FSM_1 => (false),
--RX Elastic Buffer and Phase alignment Attributes
RX_BUFFER_USE_0 => (true),
RX_EN_IDLE_RESET_BUF_0 => (true),
RX_IDLE_HI_CNT_0 => ("1000"),
RX_IDLE_LO_CNT_0 => ("0000"),
RX_XCLK_SEL_0 => ("RXREC"),
RX_BUFFER_USE_1 => (true),
RX_EN_IDLE_RESET_BUF_1 => (true),
RX_IDLE_HI_CNT_1 => ("1000"),
RX_IDLE_LO_CNT_1 => ("0000"),
RX_XCLK_SEL_1 => ("RXREC"),
--Clock Correction Attributes
CLK_COR_ADJ_LEN_0 => (1),
CLK_COR_DET_LEN_0 => (1),
CLK_COR_INSERT_IDLE_FLAG_0 => (false),
CLK_COR_KEEP_IDLE_0 => (false),
CLK_COR_MAX_LAT_0 => (18),
CLK_COR_MIN_LAT_0 => (16),
CLK_COR_PRECEDENCE_0 => (true),
CLK_COR_REPEAT_WAIT_0 => (0),
CLK_COR_SEQ_1_1_0 => ("0100000000"),
CLK_COR_SEQ_1_2_0 => ("0000000000"),
CLK_COR_SEQ_1_3_0 => ("0000000000"),
CLK_COR_SEQ_1_4_0 => ("0000000000"),
CLK_COR_SEQ_1_ENABLE_0 => ("0000"),
CLK_COR_SEQ_2_1_0 => ("0100000000"),
CLK_COR_SEQ_2_2_0 => ("0000000000"),
CLK_COR_SEQ_2_3_0 => ("0000000000"),
CLK_COR_SEQ_2_4_0 => ("0000000000"),
CLK_COR_SEQ_2_ENABLE_0 => ("0000"),
CLK_COR_SEQ_2_USE_0 => (false),
CLK_CORRECT_USE_0 => (false),
RX_DECODE_SEQ_MATCH_0 => (true),
CLK_COR_ADJ_LEN_1 => (1),
CLK_COR_DET_LEN_1 => (1),
CLK_COR_INSERT_IDLE_FLAG_1 => (false),
CLK_COR_KEEP_IDLE_1 => (false),
CLK_COR_MAX_LAT_1 => (18),
CLK_COR_MIN_LAT_1 => (16),
CLK_COR_PRECEDENCE_1 => (true),
CLK_COR_REPEAT_WAIT_1 => (0),
CLK_COR_SEQ_1_1_1 => ("0100000000"),
CLK_COR_SEQ_1_2_1 => ("0000000000"),
CLK_COR_SEQ_1_3_1 => ("0000000000"),
CLK_COR_SEQ_1_4_1 => ("0000000000"),
CLK_COR_SEQ_1_ENABLE_1 => ("0000"),
CLK_COR_SEQ_2_1_1 => ("0100000000"),
CLK_COR_SEQ_2_2_1 => ("0000000000"),
CLK_COR_SEQ_2_3_1 => ("0000000000"),
CLK_COR_SEQ_2_4_1 => ("0000000000"),
CLK_COR_SEQ_2_ENABLE_1 => ("0000"),
CLK_COR_SEQ_2_USE_1 => (false),
CLK_CORRECT_USE_1 => (false),
RX_DECODE_SEQ_MATCH_1 => (true),
--Channel Bonding Attributes
CHAN_BOND_1_MAX_SKEW_0 => (1),
CHAN_BOND_2_MAX_SKEW_0 => (1),
CHAN_BOND_KEEP_ALIGN_0 => (false),
CHAN_BOND_SEQ_1_1_0 => ("0000000000"),
CHAN_BOND_SEQ_1_2_0 => ("0000000000"),
CHAN_BOND_SEQ_1_3_0 => ("0000000000"),
CHAN_BOND_SEQ_1_4_0 => ("0000000000"),
CHAN_BOND_SEQ_1_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_1_0 => ("0000000000"),
CHAN_BOND_SEQ_2_2_0 => ("0000000000"),
CHAN_BOND_SEQ_2_3_0 => ("0000000000"),
CHAN_BOND_SEQ_2_4_0 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_USE_0 => (false),
CHAN_BOND_SEQ_LEN_0 => (1),
RX_EN_MODE_RESET_BUF_0 => (true),
CHAN_BOND_1_MAX_SKEW_1 => (1),
CHAN_BOND_2_MAX_SKEW_1 => (1),
CHAN_BOND_KEEP_ALIGN_1 => (false),
CHAN_BOND_SEQ_1_1_1 => ("0000000000"),
CHAN_BOND_SEQ_1_2_1 => ("0000000000"),
CHAN_BOND_SEQ_1_3_1 => ("0000000000"),
CHAN_BOND_SEQ_1_4_1 => ("0000000000"),
CHAN_BOND_SEQ_1_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_1_1 => ("0000000000"),
CHAN_BOND_SEQ_2_2_1 => ("0000000000"),
CHAN_BOND_SEQ_2_3_1 => ("0000000000"),
CHAN_BOND_SEQ_2_4_1 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_USE_1 => (false),
CHAN_BOND_SEQ_LEN_1 => (1),
RX_EN_MODE_RESET_BUF_1 => (true),
--RX PCI Express Attributes
CB2_INH_CC_PERIOD_0 => (8),
CDR_PH_ADJ_TIME_0 => ("01010"),
PCI_EXPRESS_MODE_0 => (false),
RX_EN_IDLE_HOLD_CDR_0 => (false),
RX_EN_IDLE_RESET_FR_0 => (true),
RX_EN_IDLE_RESET_PH_0 => (true),
RX_STATUS_FMT_0 => ("PCIE"),
TRANS_TIME_FROM_P2_0 => (x"03c"),
TRANS_TIME_NON_P2_0 => (x"19"),
TRANS_TIME_TO_P2_0 => (x"064"),
CB2_INH_CC_PERIOD_1 => (8),
CDR_PH_ADJ_TIME_1 => ("01010"),
PCI_EXPRESS_MODE_1 => (false),
RX_EN_IDLE_HOLD_CDR_1 => (false),
RX_EN_IDLE_RESET_FR_1 => (true),
RX_EN_IDLE_RESET_PH_1 => (true),
RX_STATUS_FMT_1 => ("PCIE"),
TRANS_TIME_FROM_P2_1 => (x"03c"),
TRANS_TIME_NON_P2_1 => (x"19"),
TRANS_TIME_TO_P2_1 => (x"064"),
--RX SATA Attributes
SATA_BURST_VAL_0 => ("100"),
SATA_IDLE_VAL_0 => ("100"),
SATA_MAX_BURST_0 => (9),
SATA_MAX_INIT_0 => (27),
SATA_MAX_WAKE_0 => (9),
SATA_MIN_BURST_0 => (5),
SATA_MIN_INIT_0 => (15),
SATA_MIN_WAKE_0 => (5),
SATA_BURST_VAL_1 => ("100"),
SATA_IDLE_VAL_1 => ("100"),
SATA_MAX_BURST_1 => (9),
SATA_MAX_INIT_1 => (27),
SATA_MAX_WAKE_1 => (9),
SATA_MIN_BURST_1 => (5),
SATA_MIN_INIT_1 => (15),
SATA_MIN_WAKE_1 => (5)
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0 => LOOPBACK0_IN,
LOOPBACK1 => LOOPBACK1_IN,
RXPOWERDOWN0 => tied_to_ground_vec_i(1 downto 0),
RXPOWERDOWN1 => tied_to_ground_vec_i(1 downto 0),
TXPOWERDOWN0 => tied_to_ground_vec_i(1 downto 0),
TXPOWERDOWN1 => tied_to_ground_vec_i(1 downto 0),
--------------------------------- PLL Ports --------------------------------
CLK00 => CLK00_IN,
CLK01 => CLK01_IN,
CLK10 => CLK10_IN,
CLK11 => CLK11_IN,
CLKINEAST0 => tied_to_ground_i,
CLKINEAST1 => tied_to_ground_i,
CLKINWEST0 => tied_to_ground_i,
CLKINWEST1 => tied_to_ground_i,
GCLK00 => tied_to_ground_i,
GCLK01 => tied_to_ground_i,
GCLK10 => tied_to_ground_i,
GCLK11 => tied_to_ground_i,
GTPRESET0 => GTPRESET0_IN,
GTPRESET1 => GTPRESET1_IN,
GTPTEST0 => "00010000",
GTPTEST1 => "00010000",
INTDATAWIDTH0 => tied_to_vcc_i,
INTDATAWIDTH1 => tied_to_vcc_i,
PLLCLK00 => tied_to_ground_i,
PLLCLK01 => tied_to_ground_i,
PLLCLK10 => tied_to_ground_i,
PLLCLK11 => tied_to_ground_i,
PLLLKDET0 => PLLLKDET0_OUT,
PLLLKDET1 => PLLLKDET1_OUT,
PLLLKDETEN0 => tied_to_vcc_i,
PLLLKDETEN1 => tied_to_vcc_i,
PLLPOWERDOWN0 => tied_to_ground_i,
PLLPOWERDOWN1 => tied_to_ground_i,
REFCLKOUT0 => open,
REFCLKOUT1 => open,
REFCLKPLL0 => open,
REFCLKPLL1 => open,
REFCLKPWRDNB0 => tied_to_vcc_i,
REFCLKPWRDNB1 => tied_to_vcc_i,
REFSELDYPLL0 => tied_to_ground_vec_i(2 downto 0),
REFSELDYPLL1 => tied_to_ground_vec_i(2 downto 0),
RESETDONE0 => RESETDONE0_OUT,
RESETDONE1 => RESETDONE1_OUT,
TSTCLK0 => tied_to_ground_i,
TSTCLK1 => tied_to_ground_i,
TSTIN0 => tied_to_ground_vec_i(11 downto 0),
TSTIN1 => tied_to_ground_vec_i(11 downto 0),
TSTOUT0 => open,
TSTOUT1 => open,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA0 => open,
RXCHARISCOMMA1 => open,
RXCHARISK0(3 downto 1) => rxcharisk0_float_i,
RXCHARISK0(0) => RXCHARISK0_OUT,
RXCHARISK1(3 downto 1) => rxcharisk1_float_i,
RXCHARISK1(0) => RXCHARISK1_OUT,
RXDEC8B10BUSE0 => tied_to_vcc_i,
RXDEC8B10BUSE1 => tied_to_vcc_i,
RXDISPERR0(3 downto 1) => rxdisperr0_float_i,
RXDISPERR0(0) => RXDISPERR0_OUT,
RXDISPERR1(3 downto 1) => rxdisperr1_float_i,
RXDISPERR1(0) => RXDISPERR1_OUT,
RXNOTINTABLE0(3 downto 1) => rxnotintable0_float_i,
RXNOTINTABLE0(0) => RXNOTINTABLE0_OUT,
RXNOTINTABLE1(3 downto 1) => rxnotintable1_float_i,
RXNOTINTABLE1(0) => RXNOTINTABLE1_OUT,
RXRUNDISP0 => open,
RXRUNDISP1 => open,
USRCODEERR0 => tied_to_ground_i,
USRCODEERR1 => tied_to_ground_i,
---------------------- Receive Ports - Channel Bonding ---------------------
RXCHANBONDSEQ0 => open,
RXCHANBONDSEQ1 => open,
RXCHANISALIGNED0 => open,
RXCHANISALIGNED1 => open,
RXCHANREALIGN0 => open,
RXCHANREALIGN1 => open,
RXCHBONDI => tied_to_ground_vec_i(2 downto 0),
RXCHBONDMASTER0 => tied_to_ground_i,
RXCHBONDMASTER1 => tied_to_ground_i,
RXCHBONDO => open,
RXCHBONDSLAVE0 => tied_to_ground_i,
RXCHBONDSLAVE1 => tied_to_ground_i,
RXENCHANSYNC0 => tied_to_ground_i,
RXENCHANSYNC1 => tied_to_ground_i,
---------------------- Receive Ports - Clock Correction --------------------
RXCLKCORCNT0 => open,
RXCLKCORCNT1 => open,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0 => RXBYTEISALIGNED0_OUT,
RXBYTEISALIGNED1 => RXBYTEISALIGNED1_OUT,
RXBYTEREALIGN0 => open,
RXBYTEREALIGN1 => open,
RXCOMMADET0 => RXCOMMADET0_OUT,
RXCOMMADET1 => RXCOMMADET1_OUT,
RXCOMMADETUSE0 => tied_to_vcc_i,
RXCOMMADETUSE1 => tied_to_vcc_i,
RXENMCOMMAALIGN0 => tied_to_ground_i,
RXENMCOMMAALIGN1 => tied_to_ground_i,
RXENPCOMMAALIGN0 => tied_to_ground_i,
RXENPCOMMAALIGN1 => tied_to_ground_i,
RXSLIDE0 => RXSLIDE0_IN,
RXSLIDE1 => RXSLIDE1_IN,
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET0 => tied_to_ground_i,
PRBSCNTRESET1 => tied_to_ground_i,
RXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
RXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
RXPRBSERR0 => open,
RXPRBSERR1 => open,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0 => rxdata0_i,
RXDATA1 => rxdata1_i,
RXDATAWIDTH0 => "00",
RXDATAWIDTH1 => "00",
RXRECCLK0 => open,
RXRECCLK1 => open,
RXRESET0 => tied_to_ground_i,
RXRESET1 => tied_to_ground_i,
RXUSRCLK0 => RXUSRCLK0_IN,
RXUSRCLK1 => RXUSRCLK1_IN,
RXUSRCLK20 => RXUSRCLK20_IN,
RXUSRCLK21 => RXUSRCLK21_IN,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE0 => tied_to_ground_i,
GATERXELECIDLE1 => tied_to_ground_i,
IGNORESIGDET0 => tied_to_ground_i,
IGNORESIGDET1 => tied_to_ground_i,
RCALINEAST => tied_to_ground_vec_i(4 downto 0),
RCALINWEST => tied_to_ground_vec_i(4 downto 0),
RCALOUTEAST => open,
RCALOUTWEST => open,
RXCDRRESET0 => RXCDRRESET0_IN,
RXCDRRESET1 => RXCDRRESET1_IN,
RXELECIDLE0 => open,
RXELECIDLE1 => open,
RXEQMIX0 => "00",
RXEQMIX1 => "00",
RXN0 => RXN0_IN,
RXN1 => RXN1_IN,
RXP0 => RXP0_IN,
RXP1 => RXP1_IN,
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
RXBUFRESET0 => tied_to_ground_i,
RXBUFRESET1 => tied_to_ground_i,
RXBUFSTATUS0 => open,
RXBUFSTATUS1 => open,
RXENPMAPHASEALIGN0 => tied_to_ground_i,
RXENPMAPHASEALIGN1 => tied_to_ground_i,
RXPMASETPHASE0 => tied_to_ground_i,
RXPMASETPHASE1 => tied_to_ground_i,
RXSTATUS0 => open,
RXSTATUS1 => open,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC0 => open,
RXLOSSOFSYNC1 => open,
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0 => open,
PHYSTATUS1 => open,
RXVALID0 => open,
RXVALID1 => open,
-------------------- Receive Ports - RX Polarity Control -------------------
RXPOLARITY0 => tied_to_ground_i,
RXPOLARITY1 => tied_to_ground_i,
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR => tied_to_ground_vec_i(7 downto 0),
DCLK => tied_to_ground_i,
DEN => tied_to_ground_i,
DI => tied_to_ground_vec_i(15 downto 0),
DRDY => open,
DRPDO => open,
DWE => tied_to_ground_i,
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST => GTPCLKFBEAST_OUT,
GTPCLKFBSEL0EAST => "10",
GTPCLKFBSEL0WEST => "00",
GTPCLKFBSEL1EAST => "11",
GTPCLKFBSEL1WEST => "01",
GTPCLKFBWEST => GTPCLKFBWEST_OUT,
GTPCLKOUT0 => GTPCLKOUT0_OUT,
GTPCLKOUT1 => GTPCLKOUT1_OUT,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXBYPASS8B10B0 => tied_to_ground_vec_i(3 downto 0),
TXBYPASS8B10B1 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPMODE0 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPMODE1 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPVAL0 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPVAL1 => tied_to_ground_vec_i(3 downto 0),
TXCHARISK0(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARISK0(0) => TXCHARISK0_IN,
TXCHARISK1(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARISK1(0) => TXCHARISK1_IN,
TXENC8B10BUSE0 => tied_to_vcc_i,
TXENC8B10BUSE1 => tied_to_vcc_i,
TXKERR0 => open,
TXKERR1 => open,
TXRUNDISP0 => TXRUNDISP0_OUT,
TXRUNDISP1 => TXRUNDISP1_OUT,
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXBUFSTATUS0 => open,
TXBUFSTATUS1 => open,
TXENPMAPHASEALIGN0 => TXENPMAPHASEALIGN0_IN,
TXENPMAPHASEALIGN1 => TXENPMAPHASEALIGN1_IN,
TXPMASETPHASE0 => TXPMASETPHASE0_IN,
TXPMASETPHASE1 => TXPMASETPHASE1_IN,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0 => txdata0_i,
TXDATA1 => txdata1_i,
TXDATAWIDTH0 => "00",
TXDATAWIDTH1 => "00",
TXOUTCLK0 => open,
TXOUTCLK1 => open,
TXRESET0 => tied_to_ground_i,
TXRESET1 => tied_to_ground_i,
TXUSRCLK0 => TXUSRCLK0_IN,
TXUSRCLK1 => TXUSRCLK1_IN,
TXUSRCLK20 => TXUSRCLK20_IN,
TXUSRCLK21 => TXUSRCLK21_IN,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXBUFDIFFCTRL0 => "101",
TXBUFDIFFCTRL1 => "101",
TXDIFFCTRL0 => "0110",
TXDIFFCTRL1 => "0110",
TXINHIBIT0 => tied_to_ground_i,
TXINHIBIT1 => tied_to_ground_i,
TXN0 => TXN0_OUT,
TXN1 => TXN1_OUT,
TXP0 => TXP0_OUT,
TXP1 => TXP1_OUT,
TXPREEMPHASIS0 => "000",
TXPREEMPHASIS1 => "000",
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
TXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
TXPRBSFORCEERR0 => tied_to_ground_i,
TXPRBSFORCEERR1 => tied_to_ground_i,
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY0 => tied_to_ground_i,
TXPOLARITY1 => tied_to_ground_i,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0 => tied_to_ground_i,
TXDETECTRX1 => tied_to_ground_i,
TXELECIDLE0 => tied_to_ground_i,
TXELECIDLE1 => tied_to_ground_i,
TXPDOWNASYNCH0 => tied_to_ground_i,
TXPDOWNASYNCH1 => tied_to_ground_i,
--------------------- Transmit Ports - TX Ports for SATA -------------------
TXCOMSTART0 => tied_to_ground_i,
TXCOMSTART1 => tied_to_ground_i,
TXCOMTYPE0 => tied_to_ground_i,
TXCOMTYPE1 => tied_to_ground_i
);
end RTL;
platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd 0 → 100644
View file @ 069fb021
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.7
-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard
-- / / Filename : whiterabbitgtx_wrapper_gtx.vhd
-- /___/ /\ Timestamp :
-- \ \ / \
-- \___\/\___\
--
--
-- Module WHITERABBITGTX_WRAPPER_GTX (a GTX Wrapper)
-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--
--
-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
--***************************** Entity Declaration ****************************
entity WHITERABBITGTX_WRAPPER_GTX is
generic
(
-- Simulation attributes
GTX_SIM_GTXRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
-- Share RX PLL parameter
GTX_TX_CLK_SOURCE : string := "TXPLL";
-- Save power parameter
GTX_POWER_SAVE : bit_vector := "0000000000"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK_IN : in std_logic_vector(2 downto 0);
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK_OUT : out std_logic_vector(1 downto 0);
RXDISPERR_OUT : out std_logic_vector(1 downto 0);
RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED_OUT : out std_logic;
RXCOMMADET_OUT : out std_logic;
RXSLIDE_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA_OUT : out std_logic_vector(15 downto 0);
RXRECCLK_OUT : out std_logic;
RXUSRCLK2_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXCDRRESET_IN : in std_logic;
RXN_IN : in std_logic;
RXP_IN : in std_logic;
------------------------ Receive Ports - RX PLL Ports ----------------------
GTXRXRESET_IN : in std_logic;
MGTREFCLKRX_IN : in std_logic_vector(1 downto 0);
PLLRXRESET_IN : in std_logic;
RXPLLLKDET_OUT : out std_logic;
RXRESETDONE_OUT : out std_logic;
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXCHARISK_IN : in std_logic_vector(1 downto 0);
------------------------- Transmit Ports - GTX Ports -----------------------
GTXTEST_IN : in std_logic_vector(12 downto 0);
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA_IN : in std_logic_vector(15 downto 0);
TXOUTCLK_OUT : out std_logic;
TXUSRCLK2_IN : in std_logic;
TXRUNDISP_OUT : out std_logic_vector(1 downto 0);
---------------- Transmit Ports - TX Driver and OOB signaling --------------
TXN_OUT : out std_logic;
TXP_OUT : out std_logic;
-------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
TXDLYALIGNDISABLE_IN : in std_logic;
TXDLYALIGNMONENB_IN : in std_logic;
TXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
TXDLYALIGNRESET_IN : in std_logic;
TXENPMAPHASEALIGN_IN : in std_logic;
TXPMASETPHASE_IN : in std_logic;
----------------------- Transmit Ports - TX PLL Ports ----------------------
GTXTXRESET_IN : in std_logic;
MGTREFCLKTX_IN : in std_logic_vector(1 downto 0);
PLLTXRESET_IN : in std_logic;
TXPLLLKDET_OUT : out std_logic;
TXRESETDONE_OUT : out std_logic
);
end WHITERABBITGTX_WRAPPER_GTX;
architecture RTL of WHITERABBITGTX_WRAPPER_GTX is
--**************************** Signal Declarations ****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
-- RX Datapath signals
signal rxdata_i : std_logic_vector(31 downto 0);
signal rxchariscomma_float_i : std_logic_vector(1 downto 0);
signal rxcharisk_float_i : std_logic_vector(1 downto 0);
signal rxdisperr_float_i : std_logic_vector(1 downto 0);
signal rxnotintable_float_i : std_logic_vector(1 downto 0);
signal rxrundisp_float_i : std_logic_vector(1 downto 0);
-- TX Datapath signals
signal txdata_i : std_logic_vector(31 downto 0);
signal txkerr_float_i : std_logic_vector(1 downto 0);
signal txrundisp_int : std_logic_vector(3 downto 0);
--******************************** Main Body of Code***************************
begin
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
------------------- GTX Datapath byte mapping -----------------
-- The GTX provides little endian data (first byte received on RXDATA(7 downto 0))
RXDATA_OUT <= rxdata_i(15 downto 0);
txdata_i <= (tied_to_ground_vec_i(15 downto 0) & TXDATA_IN);
----------------------------- GTX Instance --------------------------
gtxe1_i : GTXE1
generic map
(
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS => (true),
SIM_GTXRESET_SPEEDUP => (GTX_SIM_GTXRESET_SPEEDUP),
SIM_TX_ELEC_IDLE_LEVEL => ("X"),
SIM_VERSION => ("2.0"),
SIM_TXREFCLK_SOURCE => ("000"),
SIM_RXREFCLK_SOURCE => ("000"),
----------------------------TX PLL----------------------------
TX_CLK_SOURCE => (GTX_TX_CLK_SOURCE),
TX_OVERSAMPLE_MODE => (false),
TXPLL_COM_CFG => (x"21680a"),
TXPLL_CP_CFG => (x"0D"),
TXPLL_DIVSEL_FB => (4),
TXPLL_DIVSEL_OUT => (2),
TXPLL_DIVSEL_REF => (1),
TXPLL_DIVSEL45_FB => (5),
TXPLL_LKDET_CFG => ("111"),
TX_CLK25_DIVIDER => (3),
TXPLL_SATA => ("00"),
TX_TDCC_CFG => ("00"),
PMA_CAS_CLK_EN => (false),
POWER_SAVE => (GTX_POWER_SAVE),
-------------------------TX Interface-------------------------
GEN_TXUSRCLK => (true),
TX_DATA_WIDTH => (20),
TX_USRCLK_CFG => (x"00"),
TXOUTCLK_CTRL => ("TXPLLREFCLK_DIV2"),
TXOUTCLK_DLY => ("0000000000"),
--------------TX Buffering and Phase Alignment----------------
TX_PMADATA_OPT => ('1'),
PMA_TX_CFG => (x"80082"),
TX_BUFFER_USE => (false),
TX_BYTECLK_CFG => (x"00"),
TX_EN_RATE_RESET_BUF => (true),
TX_XCLK_SEL => ("TXUSR"),
TX_DLYALIGN_CTRINC => ("0100"),
TX_DLYALIGN_LPFINC => ("0110"),
TX_DLYALIGN_MONSEL => ("000"),
TX_DLYALIGN_OVRDSETTING => ("10000000"),
-------------------------TX Gearbox---------------------------
GEARBOX_ENDEC => ("000"),
TXGEARBOX_USE => (false),
----------------TX Driver and OOB Signalling------------------
TX_DRIVE_MODE => ("DIRECT"),
TX_IDLE_ASSERT_DELAY => ("100"),
TX_IDLE_DEASSERT_DELAY => ("010"),
TXDRIVE_LOOPBACK_HIZ => (false),
TXDRIVE_LOOPBACK_PD => (false),
--------------TX Pipe Control for PCI Express/SATA------------
COM_BURST_VAL => ("1111"),
------------------TX Attributes for PCI Express---------------
TX_DEEMPH_0 => ("11010"),
TX_DEEMPH_1 => ("10000"),
TX_MARGIN_FULL_0 => ("1001110"),
TX_MARGIN_FULL_1 => ("1001001"),
TX_MARGIN_FULL_2 => ("1000101"),
TX_MARGIN_FULL_3 => ("1000010"),
TX_MARGIN_FULL_4 => ("1000000"),
TX_MARGIN_LOW_0 => ("1000110"),
TX_MARGIN_LOW_1 => ("1000100"),
TX_MARGIN_LOW_2 => ("1000010"),
TX_MARGIN_LOW_3 => ("1000000"),
TX_MARGIN_LOW_4 => ("1000000"),
----------------------------RX PLL----------------------------
RX_OVERSAMPLE_MODE => (false),
RXPLL_COM_CFG => (x"21680a"),
RXPLL_CP_CFG => (x"0D"),
RXPLL_DIVSEL_FB => (4),
RXPLL_DIVSEL_OUT => (2),
RXPLL_DIVSEL_REF => (1),
RXPLL_DIVSEL45_FB => (5),
RXPLL_LKDET_CFG => ("111"),
RX_CLK25_DIVIDER => (3),
-------------------------RX Interface-------------------------
GEN_RXUSRCLK => (true),
RX_DATA_WIDTH => (20),
RXRECCLK_CTRL => ("RXRECCLKPMA_DIV2"),
RXRECCLK_DLY => ("0000000000"),
RXUSRCLK_DLY => (x"0000"),
----------RX Driver,OOB signalling,Coupling and Eq.,CDR-------
AC_CAP_DIS => (true),
CDR_PH_ADJ_TIME => ("10100"),
OOBDETECT_THRESHOLD => ("011"),
PMA_CDR_SCAN => (x"640404C"),
PMA_RX_CFG => (x"05ce008"),
RCV_TERM_GND => (false),
RCV_TERM_VTTRX => (true),
RX_EN_IDLE_HOLD_CDR => (false),
RX_EN_IDLE_RESET_FR => (false),
RX_EN_IDLE_RESET_PH => (false),
TX_DETECT_RX_CFG => (x"1832"),
TERMINATION_CTRL => ("00000"),
TERMINATION_OVRD => (false),
CM_TRIM => ("01"),
PMA_RXSYNC_CFG => (x"00"),
PMA_CFG => (x"0040000040000000003"),
BGTEST_CFG => ("00"),
BIAS_CFG => (x"00000"),
--------------RX Decision Feedback Equalizer(DFE)-------------
DFE_CAL_TIME => ("01100"),
DFE_CFG => ("00011011"),
RX_EN_IDLE_HOLD_DFE => (true),
RX_EYE_OFFSET => (x"4C"),
RX_EYE_SCANMODE => ("00"),
-------------------------PRBS Detection-----------------------
RXPRBSERR_LOOPBACK => ('0'),
------------------Comma Detection and Alignment---------------
ALIGN_COMMA_WORD => (2),
COMMA_10B_ENABLE => ("0001111111"),
COMMA_DOUBLE => (false),
DEC_MCOMMA_DETECT => (false),
DEC_PCOMMA_DETECT => (false),
DEC_VALID_COMMA_ONLY => (true),
MCOMMA_10B_VALUE => ("1010000011"),
MCOMMA_DETECT => (true),
PCOMMA_10B_VALUE => ("0101111100"),
PCOMMA_DETECT => (true),
RX_DECODE_SEQ_MATCH => (true),
RX_SLIDE_AUTO_WAIT => (5),
RX_SLIDE_MODE => ("PCS"),
-- SHOW_REALIGN_COMMA => (TRUE),
SHOW_REALIGN_COMMA => (false),
-----------------RX Loss-of-sync State Machine----------------
RX_LOS_INVALID_INCR => (8),
RX_LOS_THRESHOLD => (128),
RX_LOSS_OF_SYNC_FSM => (false),
-------------------------RX Gearbox---------------------------
RXGEARBOX_USE => (false),
-------------RX Elastic Buffer and Phase alignment------------
RX_BUFFER_USE => (true),
RX_EN_IDLE_RESET_BUF => (false),
RX_EN_MODE_RESET_BUF => (true),
RX_EN_RATE_RESET_BUF => (true),
RX_EN_REALIGN_RESET_BUF => (false),
RX_EN_REALIGN_RESET_BUF2 => (false),
RX_FIFO_ADDR_MODE => ("FULL"),
RX_IDLE_HI_CNT => ("1000"),
RX_IDLE_LO_CNT => ("0000"),
RX_XCLK_SEL => ("RXREC"),
RX_DLYALIGN_CTRINC => ("1110"),
RX_DLYALIGN_EDGESET => ("00010"),
RX_DLYALIGN_LPFINC => ("1110"),
RX_DLYALIGN_MONSEL => ("000"),
RX_DLYALIGN_OVRDSETTING => ("10000000"),
------------------------Clock Correction----------------------
CLK_COR_ADJ_LEN => (1),
CLK_COR_DET_LEN => (1),
CLK_COR_INSERT_IDLE_FLAG => (false),
CLK_COR_KEEP_IDLE => (false),
CLK_COR_MAX_LAT => (16),
CLK_COR_MIN_LAT => (14),
CLK_COR_PRECEDENCE => (true),
CLK_COR_REPEAT_WAIT => (0),
CLK_COR_SEQ_1_1 => ("0100000000"),
CLK_COR_SEQ_1_2 => ("0100000000"),
CLK_COR_SEQ_1_3 => ("0100000000"),
CLK_COR_SEQ_1_4 => ("0100000000"),
CLK_COR_SEQ_1_ENABLE => ("1111"),
CLK_COR_SEQ_2_1 => ("0100000000"),
CLK_COR_SEQ_2_2 => ("0100000000"),
CLK_COR_SEQ_2_3 => ("0100000000"),
CLK_COR_SEQ_2_4 => ("0100000000"),
CLK_COR_SEQ_2_ENABLE => ("1111"),
CLK_COR_SEQ_2_USE => (false),
CLK_CORRECT_USE => (false),
------------------------Channel Bonding----------------------
CHAN_BOND_1_MAX_SKEW => (1),
CHAN_BOND_2_MAX_SKEW => (1),
CHAN_BOND_KEEP_ALIGN => (false),
CHAN_BOND_SEQ_1_1 => ("0000000000"),
CHAN_BOND_SEQ_1_2 => ("0000000000"),
CHAN_BOND_SEQ_1_3 => ("0000000000"),
CHAN_BOND_SEQ_1_4 => ("0000000000"),
CHAN_BOND_SEQ_1_ENABLE => ("1111"),
CHAN_BOND_SEQ_2_1 => ("0000000000"),
CHAN_BOND_SEQ_2_2 => ("0000000000"),
CHAN_BOND_SEQ_2_3 => ("0000000000"),
CHAN_BOND_SEQ_2_4 => ("0000000000"),
CHAN_BOND_SEQ_2_CFG => ("00000"),
CHAN_BOND_SEQ_2_ENABLE => ("1111"),
CHAN_BOND_SEQ_2_USE => (false),
CHAN_BOND_SEQ_LEN => (1),
PCI_EXPRESS_MODE => (false),
-------------RX Attributes for PCI Express/SATA/SAS----------
SAS_MAX_COMSAS => (52),
SAS_MIN_COMSAS => (40),
SATA_BURST_VAL => ("100"),
SATA_IDLE_VAL => ("100"),
SATA_MAX_BURST => (9),
SATA_MAX_INIT => (27),
SATA_MAX_WAKE => (9),
SATA_MIN_BURST => (5),
SATA_MIN_INIT => (15),
SATA_MIN_WAKE => (5),
TRANS_TIME_FROM_P2 => (x"03c"),
TRANS_TIME_NON_P2 => (x"19"),
TRANS_TIME_RATE => (x"ff"),
TRANS_TIME_TO_P2 => (x"064")
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK => LOOPBACK_IN,
RXPOWERDOWN => "00",
TXPOWERDOWN => "00",
-------------- Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
RXDATAVALID => open,
RXGEARBOXSLIP => tied_to_ground_i,
RXHEADER => open,
RXHEADERVALID => open,
RXSTARTOFSEQ => open,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA => open,
RXCHARISK(3 downto 2) => rxcharisk_float_i,
RXCHARISK(1 downto 0) => RXCHARISK_OUT,
RXDEC8B10BUSE => tied_to_vcc_i,
RXDISPERR(3 downto 2) => rxdisperr_float_i,
RXDISPERR(1 downto 0) => RXDISPERR_OUT,
RXNOTINTABLE(3 downto 2) => rxnotintable_float_i,
RXNOTINTABLE(1 downto 0) => RXNOTINTABLE_OUT,
RXRUNDISP => open,
USRCODEERR => tied_to_ground_i,
------------------- Receive Ports - Channel Bonding Ports ------------------
RXCHANBONDSEQ => open,
RXCHBONDI => tied_to_ground_vec_i(3 downto 0),
RXCHBONDLEVEL => tied_to_ground_vec_i(2 downto 0),
RXCHBONDMASTER => tied_to_ground_i,
RXCHBONDO => open,
RXCHBONDSLAVE => tied_to_ground_i,
RXENCHANSYNC => tied_to_ground_i,
------------------- Receive Ports - Clock Correction Ports -----------------
RXCLKCORCNT => open,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED => RXBYTEISALIGNED_OUT,
RXBYTEREALIGN => open,
RXCOMMADET => RXCOMMADET_OUT,
RXCOMMADETUSE => tied_to_vcc_i,
RXENMCOMMAALIGN => tied_to_ground_i,
RXENPCOMMAALIGN => tied_to_ground_i,
RXSLIDE => RXSLIDE_IN,
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET => tied_to_ground_i,
RXENPRBSTST => tied_to_ground_vec_i(2 downto 0),
RXPRBSERR => open,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA => rxdata_i,
RXRECCLK => RXRECCLK_OUT,
RXRECCLKPCS => open,
RXRESET => tied_to_ground_i,
RXUSRCLK => tied_to_ground_i,
RXUSRCLK2 => RXUSRCLK2_IN,
------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
DFECLKDLYADJ => tied_to_ground_vec_i(5 downto 0),
DFECLKDLYADJMON => open,
DFEDLYOVRD => tied_to_vcc_i,
DFEEYEDACMON => open,
DFESENSCAL => open,
DFETAP1 => tied_to_ground_vec_i(4 downto 0),
DFETAP1MONITOR => open,
DFETAP2 => tied_to_ground_vec_i(4 downto 0),
DFETAP2MONITOR => open,
DFETAP3 => tied_to_ground_vec_i(3 downto 0),
DFETAP3MONITOR => open,
DFETAP4 => tied_to_ground_vec_i(3 downto 0),
DFETAP4MONITOR => open,
DFETAPOVRD => tied_to_vcc_i,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE => tied_to_vcc_i,
IGNORESIGDET => tied_to_vcc_i,
RXCDRRESET => RXCDRRESET_IN,
RXELECIDLE => open,
RXEQMIX => "0000000000",
RXN => RXN_IN,
RXP => RXP_IN,
-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
RXBUFRESET => tied_to_ground_i,
RXBUFSTATUS => open,
RXCHANISALIGNED => open,
RXCHANREALIGN => open,
RXDLYALIGNDISABLE => tied_to_ground_i,
RXDLYALIGNMONENB => tied_to_ground_i,
RXDLYALIGNMONITOR => open,
RXDLYALIGNOVERRIDE => tied_to_vcc_i,
RXDLYALIGNRESET => tied_to_ground_i,
RXDLYALIGNSWPPRECURB => tied_to_vcc_i,
RXDLYALIGNUPDSW => tied_to_ground_i,
RXENPMAPHASEALIGN => tied_to_ground_i,
RXPMASETPHASE => tied_to_ground_i,
RXSTATUS => open,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC => open,
---------------------- Receive Ports - RX Oversampling ---------------------
RXENSAMPLEALIGN => tied_to_ground_i,
RXOVERSAMPLEERR => open,
------------------------ Receive Ports - RX PLL Ports ----------------------
GREFCLKRX => tied_to_ground_i,
GTXRXRESET => GTXRXRESET_IN,
MGTREFCLKRX => MGTREFCLKRX_IN,
NORTHREFCLKRX => tied_to_ground_vec_i(1 downto 0),
PERFCLKRX => tied_to_ground_i,
PLLRXRESET => PLLRXRESET_IN,
RXPLLLKDET => RXPLLLKDET_OUT,
RXPLLLKDETEN => tied_to_vcc_i,
RXPLLPOWERDOWN => tied_to_ground_i,
RXPLLREFSELDY => tied_to_ground_vec_i(2 downto 0),
RXRATE => tied_to_ground_vec_i(1 downto 0),
RXRATEDONE => open,
RXRESETDONE => RXRESETDONE_OUT,
SOUTHREFCLKRX => tied_to_ground_vec_i(1 downto 0),
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS => open,
RXVALID => open,
----------------- Receive Ports - RX Polarity Control Ports ----------------
RXPOLARITY => tied_to_ground_i,
--------------------- Receive Ports - RX Ports for SATA --------------------
COMINITDET => open,
COMSASDET => open,
COMWAKEDET => open,
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR => tied_to_ground_vec_i(7 downto 0),
DCLK => tied_to_ground_i,
DEN => tied_to_ground_i,
DI => tied_to_ground_vec_i(15 downto 0),
DRDY => open,
DRPDO => open,
DWE => tied_to_ground_i,
-------------- Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
TXGEARBOXREADY => open,
TXHEADER => tied_to_ground_vec_i(2 downto 0),
TXSEQUENCE => tied_to_ground_vec_i(6 downto 0),
TXSTARTSEQ => tied_to_ground_i,
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXBYPASS8B10B => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPMODE => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPVAL => tied_to_ground_vec_i(3 downto 0),
TXCHARISK(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
TXCHARISK(1 downto 0) => TXCHARISK_IN,
TXENC8B10BUSE => tied_to_vcc_i,
TXKERR => open,
TXRUNDISP => txrundisp_int,
------------------------- Transmit Ports - GTX Ports -----------------------
GTXTEST => GTXTEST_IN,
MGTREFCLKFAB => open,
TSTCLK0 => tied_to_ground_i,
TSTCLK1 => tied_to_ground_i,
TSTIN => "11111111111111111111",
TSTOUT => open,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA => txdata_i,
TXOUTCLK => TXOUTCLK_OUT,
TXOUTCLKPCS => open,
TXRESET => tied_to_ground_i,
TXUSRCLK => tied_to_ground_i,
TXUSRCLK2 => TXUSRCLK2_IN,
---------------- Transmit Ports - TX Driver and OOB signaling --------------
TXBUFDIFFCTRL => "100",
TXDIFFCTRL => "1101",
TXINHIBIT => tied_to_ground_i,
TXN => TXN_OUT,
TXP => TXP_OUT,
TXPOSTEMPHASIS => "00000",
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXPREEMPHASIS => "0000",
----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
TXBUFSTATUS => open,
-------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
TXDLYALIGNDISABLE => TXDLYALIGNDISABLE_IN,
TXDLYALIGNMONENB => TXDLYALIGNMONENB_IN,
TXDLYALIGNMONITOR => TXDLYALIGNMONITOR_OUT,
TXDLYALIGNOVERRIDE => tied_to_ground_i,
TXDLYALIGNRESET => TXDLYALIGNRESET_IN,
TXDLYALIGNUPDSW => tied_to_ground_i,
TXENPMAPHASEALIGN => TXENPMAPHASEALIGN_IN,
TXPMASETPHASE => TXPMASETPHASE_IN,
----------------------- Transmit Ports - TX PLL Ports ----------------------
GREFCLKTX => tied_to_ground_i,
GTXTXRESET => GTXTXRESET_IN,
MGTREFCLKTX => MGTREFCLKTX_IN,
NORTHREFCLKTX => tied_to_ground_vec_i(1 downto 0),
PERFCLKTX => tied_to_ground_i,
PLLTXRESET => PLLTXRESET_IN,
SOUTHREFCLKTX => tied_to_ground_vec_i(1 downto 0),
TXPLLLKDET => TXPLLLKDET_OUT,
TXPLLLKDETEN => tied_to_vcc_i,
TXPLLPOWERDOWN => tied_to_ground_i,
TXPLLREFSELDY => tied_to_ground_vec_i(2 downto 0),
TXRATE => tied_to_ground_vec_i(1 downto 0),
TXRATEDONE => open,
TXRESETDONE => TXRESETDONE_OUT,
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST => tied_to_ground_vec_i(2 downto 0),
TXPRBSFORCEERR => tied_to_ground_i,
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY => tied_to_ground_i,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDEEMPH => tied_to_ground_i,
TXDETECTRX => tied_to_ground_i,
TXELECIDLE => tied_to_ground_i,
TXMARGIN => tied_to_ground_vec_i(2 downto 0),
TXPDOWNASYNCH => tied_to_ground_i,
TXSWING => tied_to_ground_i,
--------------------- Transmit Ports - TX Ports for SATA -------------------
COMFINISH => open,
TXCOMINIT => tied_to_ground_i,
TXCOMSAS => tied_to_ground_i,
TXCOMWAKE => tied_to_ground_i
);
TXRUNDISP_OUT <= txrundisp_int(1 downto 0);
end RTL;
platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd 0 → 100644
View file @ 069fb021
-------------------------------------------------------------------------------
-- Title : Deterministic Xilinx GTP wrapper - Spartan-6 top module
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wr_gtp_phy_spartan6.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2012-04-27
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Dual channel wrapper for Xilinx Spartan-6 GTP adapted for
-- deterministic delays at 1.25 Gbps.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 CERN / Tomasz Wlostowski
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-18 0.4 twlostow Initial release
-- 2011-02-07 0.5 twlostow Verified on Spartan6 GTP (single channel only)
-- 2011-05-15 0.6 twlostow Added reference clock output
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.all;
library work;
use work.gencores_pkg.all;
use work.disparity_gen_pkg.all;
entity wr_gtp_phy_spartan6 is
generic (
-- set to non-zero value to speed up the simulation by reducing some delays
g_simulation : integer := 1;
g_force_disparity : integer := 0
);
port (
-- Port 0
-- dedicated GTP clock input
gtp_clk_i: in std_logic;
-- TX path, synchronous to ch0_ref_clk_i
ch0_ref_clk_i : in std_logic;
-- data input (8 bits, not 8b10b-encoded)
ch0_tx_data_i : in std_logic_vector(7 downto 0);
-- 1 when tx_data_i contains a control code, 0 when it's a data byte
ch0_tx_k_i : in std_logic;
-- disparity of the currently transmitted 8b10b code (1 = plus, 0 = minus).
-- Necessary for the PCS to generate proper frame termination sequences.
ch0_tx_disparity_o : out std_logic;
-- Encoding error indication (1 = error, 0 = no error)
ch0_tx_enc_err_o : out std_logic;
-- RX path, synchronous to ch0_rx_rbclk_o.
-- RX recovered clock
ch0_rx_rbclk_o : out std_logic;
-- 8b10b-decoded data output. The data output must be kept invalid before
-- the transceiver is locked on the incoming signal to prevent the EP from
-- detecting a false carrier.
ch0_rx_data_o : out std_logic_vector(7 downto 0);
-- 1 when the byte on rx_data_o is a control code
ch0_rx_k_o : out std_logic;
-- encoding error indication
ch0_rx_enc_err_o : out std_logic;
-- RX bitslide indication, indicating the delay of the RX path of the
-- transceiver (in UIs). Must be valid when ch0_rx_data_o is valid.
ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
-- reset input, active hi
ch0_rst_i : in std_logic;
-- local loopback enable (Tx->Rx), active hi
ch0_loopen_i : in std_logic;
-- Port 1
ch1_ref_clk_i : in std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch1_tx_k_i : in std_logic := '0';
ch1_tx_disparity_o : out std_logic;
ch1_tx_enc_err_o : out std_logic;
ch1_rx_data_o : out std_logic_vector(7 downto 0);
ch1_rx_rbclk_o : out std_logic;
ch1_rx_k_o : out std_logic;
ch1_rx_enc_err_o : out std_logic;
ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
-- Serial I/O
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
pad_rxn0_i : in std_logic := '0';
pad_rxp0_i : in std_logic := '0';
pad_txn1_o : out std_logic;
pad_txp1_o : out std_logic;
pad_rxn1_i : in std_logic := '0';
pad_rxp1_i : in std_logic := '0'
);
end wr_gtp_phy_spartan6;
architecture rtl of wr_gtp_phy_spartan6 is
component WHITERABBITGTP_WRAPPER_TILE_SPARTAN6
generic (
TILE_SIM_GTPRESET_SPEEDUP : integer;
TILE_CLK25_DIVIDER_0 : integer;
TILE_CLK25_DIVIDER_1 : integer;
TILE_PLL_DIVSEL_FB_0 : integer;
TILE_PLL_DIVSEL_FB_1 : integer;
TILE_PLL_DIVSEL_REF_0 : integer;
TILE_PLL_DIVSEL_REF_1 : integer;
TILE_PLL_SOURCE_0 : string;
TILE_PLL_SOURCE_1 : string);
port (
LOOPBACK0_IN : in std_logic_vector(2 downto 0);
LOOPBACK1_IN : in std_logic_vector(2 downto 0);
REFCLKOUT0_OUT : out std_logic;
REFCLKOUT1_OUT : out std_logic;
CLK00_IN : in std_logic;
CLK01_IN : in std_logic;
CLK10_IN : in std_logic;
CLK11_IN : in std_logic;
GTPRESET0_IN : in std_logic;
GTPRESET1_IN : in std_logic;
PLLLKDET0_OUT : out std_logic;
PLLLKDET1_OUT : out std_logic;
RESETDONE0_OUT : out std_logic;
RESETDONE1_OUT : out std_logic;
RXCHARISK0_OUT : out std_logic;
RXCHARISK1_OUT : out std_logic;
RXDISPERR0_OUT : out std_logic;
RXDISPERR1_OUT : out std_logic;
RXNOTINTABLE0_OUT : out std_logic;
RXNOTINTABLE1_OUT : out std_logic;
RXBYTEISALIGNED0_OUT : out std_logic;
RXBYTEISALIGNED1_OUT : out std_logic;
RXCOMMADET0_OUT : out std_logic;
RXCOMMADET1_OUT : out std_logic;
RXSLIDE0_IN : in std_logic;
RXSLIDE1_IN : in std_logic;
RXDATA0_OUT : out std_logic_vector(7 downto 0);
RXDATA1_OUT : out std_logic_vector(7 downto 0);
RXUSRCLK0_IN : in std_logic;
RXUSRCLK1_IN : in std_logic;
RXUSRCLK20_IN : in std_logic;
RXUSRCLK21_IN : in std_logic;
RXCDRRESET0_IN : in std_logic;
RXCDRRESET1_IN : in std_logic;
RXN0_IN : in std_logic;
RXN1_IN : in std_logic;
RXP0_IN : in std_logic;
RXP1_IN : in std_logic;
GTPCLKFBEAST_OUT : out std_logic_vector(1 downto 0);
GTPCLKFBWEST_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
TXCHARISK0_IN : in std_logic;
TXCHARISK1_IN : in std_logic;
TXCHARDISPMODE0_IN : in std_logic;
TXCHARDISPMODE1_IN : in std_logic;
TXCHARDISPVAL0_IN : in std_logic;
TXCHARDISPVAL1_IN : in std_logic;
TXRUNDISP0_OUT : out std_logic_vector(3 downto 0);
TXRUNDISP1_OUT : out std_logic_vector(3 downto 0);
TXENPMAPHASEALIGN0_IN : in std_logic;
TXENPMAPHASEALIGN1_IN : in std_logic;
TXPMASETPHASE0_IN : in std_logic;
TXPMASETPHASE1_IN : in std_logic;
TXDATA0_IN : in std_logic_vector(7 downto 0);
TXDATA1_IN : in std_logic_vector(7 downto 0);
TXUSRCLK0_IN : in std_logic;
TXUSRCLK1_IN : in std_logic;
TXUSRCLK20_IN : in std_logic;
TXUSRCLK21_IN : in std_logic;
TXN0_OUT : out std_logic;
TXN1_OUT : out std_logic;
TXP0_OUT : out std_logic;
TXP1_OUT : out std_logic);
end component;
component BUFG
port (
O : out std_ulogic;
I : in std_ulogic);
end component;
component BUFIO2
generic (
DIVIDE_BYPASS : boolean := true;
DIVIDE : integer := 1;
I_INVERT : boolean := false;
USE_DOUBLER : boolean := false);
port (
DIVCLK : out std_ulogic;
IOCLK : out std_ulogic;
SERDESSTROBE : out std_ulogic;
I : in std_ulogic);
end component;
component gtp_phase_align
generic(
g_simulation : integer);
port (
gtp_rst_i : in std_logic;
gtp_tx_clk_i : in std_logic;
gtp_tx_en_pma_phase_align_o : out std_logic;
gtp_tx_pma_set_phase_o : out std_logic;
align_en_i : in std_logic;
align_done_o : out std_logic);
end component;
component gtp_bitslide
generic(
g_simulation : integer;
g_target : string := "spartan6");
port (
gtp_rst_i : in std_logic;
gtp_rx_clk_i : in std_logic;
gtp_rx_comma_det_i : in std_logic;
gtp_rx_byte_is_aligned_i : in std_logic;
serdes_ready_i : in std_logic;
gtp_rx_slide_o : out std_logic;
gtp_rx_cdr_rst_o : out std_logic;
bitslide_o : out std_logic_vector(4 downto 0);
synced_o : out std_logic);
end component;
signal ch0_gtp_reset : std_logic;
signal ch0_gtp_loopback : std_logic_vector(2 downto 0) := "000";
signal ch0_gtp_reset_done : std_logic;
signal ch0_gtp_pll_lockdet : std_logic;
signal ch0_tx_pma_set_phase : std_logic := '0';
signal ch0_tx_rundisp_vec : std_logic_vector(3 downto 0);
signal ch0_tx_en_pma_phase_align : std_logic := '0';
signal ch0_rx_data_int : std_logic_vector(7 downto 0);
signal ch0_rx_k_int : std_logic;
signal ch0_rx_disperr, ch0_rx_invcode : std_logic;
signal ch0_rx_byte_is_aligned : std_logic;
signal ch0_rx_comma_det : std_logic;
signal ch0_rx_cdr_rst : std_logic := '0';
signal ch0_rx_rec_clk_pad : std_logic;
signal ch0_rx_rec_clk : std_logic;
signal ch0_rx_divclk : std_logic;
signal ch0_rx_slide : std_logic := '0';
signal ch0_gtp_locked : std_logic;
signal ch0_align_done : std_logic;
signal ch0_rx_synced : std_logic;
signal ch0_gtp_clkout_int : std_logic_vector(1 downto 0);
signal ch0_rx_enable_output, ch0_rx_enable_output_synced : std_logic;
signal ch1_gtp_reset : std_logic;
signal ch1_gtp_loopback : std_logic_vector(2 downto 0) := "000";
signal ch1_gtp_reset_done : std_logic;
signal ch1_gtp_pll_lockdet : std_logic;
signal ch1_tx_pma_set_phase : std_logic := '0';
signal ch1_tx_rundisp_vec : std_logic_vector(3 downto 0);
signal ch1_tx_en_pma_phase_align : std_logic := '0';
signal ch1_rx_data_int : std_logic_vector(7 downto 0);
signal ch1_rx_k_int : std_logic;
signal ch1_rx_disperr, ch1_rx_invcode : std_logic;
signal ch1_rx_byte_is_aligned : std_logic;
signal ch1_rx_comma_det : std_logic;
signal ch1_rx_cdr_rst : std_logic := '0';
signal ch1_rx_rec_clk_pad : std_logic;
signal ch1_rx_rec_clk : std_logic;
signal ch1_rx_divclk : std_logic;
signal ch1_rx_slide : std_logic := '0';
signal ch1_gtp_locked : std_logic;
signal ch1_align_done : std_logic;
signal ch1_rx_synced : std_logic;
signal ch1_gtp_clkout_int : std_logic_vector(1 downto 0);
signal ch1_rx_enable_output, ch1_rx_enable_output_synced : std_logic;
signal ch0_rst_synced : std_logic;
signal ch0_rst_d0 : std_logic;
signal ch0_reset_counter : unsigned(9 downto 0);
signal ch1_rst_synced : std_logic;
signal ch1_rst_d0 : std_logic;
signal ch1_reset_counter : unsigned(9 downto 0);
signal ch0_rx_bitslide_int : std_logic_vector(4 downto 0);
signal ch1_rx_bitslide_int : std_logic_vector(4 downto 0);
signal ch0_ref_clk_in : std_logic_vector(1 downto 0);
signal ch1_ref_clk_in : std_logic_vector(1 downto 0);
signal ch0_disparity_set : std_logic;
signal ch1_disparity_set : std_logic;
signal ch0_tx_chardispmode : std_logic;
signal ch1_tx_chardispmode : std_logic;
signal ch0_tx_chardispval : std_logic;
signal ch1_tx_chardispval : std_logic;
component enc_8b10b
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
ctrl_i : in std_logic;
in_8b_i : in std_logic_vector(7 downto 0);
err_o : out std_logic;
dispar_o : out std_logic;
out_10b_o : out std_logic_vector(9 downto 0));
end component;
signal ch0_rst_n : std_logic;
signal ch1_rst_n : std_logic;
signal ch0_cur_disp : t_8b10b_disparity;
signal ch0_disp_pipe : std_logic_vector(1 downto 0);
signal ch1_cur_disp : t_8b10b_disparity;
signal ch1_disp_pipe : std_logic_vector(1 downto 0);
begin -- rtl
ch0_rst_n <= not ch0_gtp_reset;
ch1_rst_n <= not ch1_gtp_reset;
gen_disp_ch0 : process(ch0_ref_clk_i)
begin
if rising_edge(ch0_ref_clk_i) then
if(ch0_tx_chardispmode = '1' or ch0_rst_n = '0') then
if(g_force_disparity = 0) then
ch0_cur_disp <= RD_MINUS;
else
ch0_cur_disp <= RD_PLUS;
end if;
ch0_disp_pipe <= (others => '0');
else
ch0_cur_disp <= f_next_8b10b_disparity8(ch0_cur_disp, ch0_tx_k_i, ch0_tx_data_i);
ch0_disp_pipe(0) <= to_std_logic(ch0_cur_disp);
ch0_disp_pipe(1) <= ch0_disp_pipe(0);
end if;
end if;
end process;
gen_disp_ch1 : process(ch1_ref_clk_i)
begin
if rising_edge(ch1_ref_clk_i) then
if(ch1_tx_chardispmode = '1' or ch1_rst_n = '0') then
if(g_force_disparity = 0) then
ch1_cur_disp <= RD_MINUS;
else
ch1_cur_disp <= RD_PLUS;
end if;
ch1_disp_pipe <= (others => '0');
else
ch1_cur_disp <= f_next_8b10b_disparity8(ch1_cur_disp, ch1_tx_k_i, ch1_tx_data_i);
ch1_disp_pipe(0) <= to_std_logic(ch1_cur_disp);
ch1_disp_pipe(1) <= ch1_disp_pipe(0);
end if;
end if;
end process;
ch0_tx_disparity_o <= ch0_disp_pipe(0);
ch1_tx_disparity_o <= ch1_disp_pipe(1);
p_gen_reset_ch0 : process(ch0_ref_clk_i)
begin
if rising_edge(ch0_ref_clk_i) then
ch0_rst_d0 <= ch0_rst_i;
ch0_rst_synced <= ch0_rst_d0;
if(ch0_rst_synced = '1') then
ch0_reset_counter <= (others => '0');
else
if(ch0_reset_counter(ch0_reset_counter'left) = '0') then
ch0_reset_counter <= ch0_reset_counter + 1;
end if;
end if;
end if;
end process;
p_gen_reset_ch1 : process(ch1_ref_clk_i)
begin
if rising_edge(ch1_ref_clk_i) then
ch1_rst_d0 <= ch1_rst_i;
ch1_rst_synced <= ch1_rst_d0;
if(ch1_rst_synced = '1') then
ch1_reset_counter <= (others => '0');
else
if(ch1_reset_counter(ch1_reset_counter'left) = '0') then
ch1_reset_counter <= ch1_reset_counter + 1;
end if;
end if;
end if;
end process;
ch0_gtp_reset <= ch0_rst_synced or std_logic(not ch0_reset_counter(ch0_reset_counter'left));
ch1_gtp_reset <= ch1_rst_synced or std_logic(not ch1_reset_counter(ch1_reset_counter'left));
ch0_rx_rec_clk_pad <= ch0_gtp_clkout_int(1);
ch1_rx_rec_clk_pad <= ch1_gtp_clkout_int(1);
ch0_ref_clk_in(0) <= gtp_clk_i;
ch0_ref_clk_in(1) <= '0';
ch1_ref_clk_in(0) <= gtp_clk_i;
ch1_ref_clk_in(1) <= '0';
U_GTP_TILE_INST : WHITERABBITGTP_WRAPPER_TILE_SPARTAN6
generic map
(
TILE_SIM_GTPRESET_SPEEDUP => g_simulation, -- Set to 1 to speed up sim reset
TILE_CLK25_DIVIDER_0 => 5,
TILE_CLK25_DIVIDER_1 => 5,
TILE_PLL_DIVSEL_FB_0 => 2,
TILE_PLL_DIVSEL_FB_1 => 2,
TILE_PLL_DIVSEL_REF_0 => 1,
TILE_PLL_DIVSEL_REF_1 => 1,
--
TILE_PLL_SOURCE_0 => "PLL0",
TILE_PLL_SOURCE_1 => "PLL1"
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0_IN => ch0_gtp_loopback,
LOOPBACK1_IN => ch1_gtp_loopback,
--------------------------------- PLL Ports --------------------------------
REFCLKOUT0_OUT => open,
REFCLKOUT1_OUT => open,
CLK00_IN => ch0_ref_clk_in(0),
CLK01_IN => ch1_ref_clk_in(0),
CLK10_IN => ch0_ref_clk_in(1),
CLK11_IN => ch1_ref_clk_in(1),
GTPRESET0_IN => ch0_gtp_reset,
GTPRESET1_IN => ch1_gtp_reset,
PLLLKDET0_OUT => ch0_gtp_pll_lockdet,
PLLLKDET1_OUT => ch1_gtp_pll_lockdet,
RESETDONE0_OUT => ch0_gtp_reset_done,
RESETDONE1_OUT => ch1_gtp_reset_done,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT => ch0_rx_k_int,
RXCHARISK1_OUT => ch1_rx_k_int,
RXDISPERR0_OUT => ch0_rx_disperr,
RXDISPERR1_OUT => ch1_rx_disperr,
RXNOTINTABLE0_OUT => ch0_rx_invcode,
RXNOTINTABLE1_OUT => ch1_rx_invcode,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0_OUT => ch0_rx_byte_is_aligned,
RXBYTEISALIGNED1_OUT => ch1_rx_byte_is_aligned,
RXCOMMADET0_OUT => ch0_rx_comma_det,
RXCOMMADET1_OUT => ch1_rx_comma_det,
RXSLIDE0_IN => ch0_rx_slide,
RXSLIDE1_IN => ch1_rx_slide,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT => ch0_rx_data_int,
RXDATA1_OUT => ch1_rx_data_int,
RXUSRCLK0_IN => ch0_rx_rec_clk,
RXUSRCLK1_IN => ch1_rx_rec_clk,
RXUSRCLK20_IN => ch0_rx_rec_clk,
RXUSRCLK21_IN => ch1_rx_rec_clk,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXCDRRESET0_IN => ch0_rx_cdr_rst,
RXCDRRESET1_IN => ch1_rx_cdr_rst,
RXN0_IN => pad_rxn0_i,
RXN1_IN => pad_rxn1_i,
RXP0_IN => pad_rxp0_i,
RXP1_IN => pad_rxp1_i,
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST_OUT => open,
GTPCLKFBWEST_OUT => open,
GTPCLKOUT0_OUT => ch0_gtp_clkout_int,
GTPCLKOUT1_OUT => ch1_gtp_clkout_int,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARISK0_IN => ch0_tx_k_i,
TXCHARISK1_IN => ch1_tx_k_i,
TXRUNDISP0_OUT => ch0_tx_rundisp_vec,
TXRUNDISP1_OUT => ch1_tx_rundisp_vec,
TXCHARDISPMODE0_IN => ch0_tx_chardispmode,
TXCHARDISPMODE1_IN => ch1_tx_chardispmode,
TXCHARDISPVAL0_IN => ch0_tx_chardispval,
TXCHARDISPVAL1_IN => ch1_tx_chardispval,
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXENPMAPHASEALIGN0_IN => ch0_tx_en_pma_phase_align,
TXENPMAPHASEALIGN1_IN => ch1_tx_en_pma_phase_align,
TXPMASETPHASE0_IN => ch0_tx_pma_set_phase,
TXPMASETPHASE1_IN => ch1_tx_pma_set_phase,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN => ch0_tx_data_i,
TXDATA1_IN => ch1_tx_data_i,
TXUSRCLK0_IN => ch0_ref_clk_i,
TXUSRCLK1_IN => ch1_ref_clk_i,
TXUSRCLK20_IN => ch0_ref_clk_i,
TXUSRCLK21_IN => ch1_ref_clk_i,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT => pad_txn0_o,
TXN1_OUT => pad_txn1_o,
TXP0_OUT => pad_txp0_o,
TXP1_OUT => pad_txp1_o
);
U_Rbclk_buf_ch0 : BUFIO2
port map (
DIVCLK => ch0_rx_divclk,
IOCLK => open,
SERDESSTROBE => open,
I => ch0_rx_rec_clk_pad);
U_Rbclk_bufg_ch0 : BUFG
port map (
I => ch0_rx_divclk,
O => ch0_rx_rec_clk
);
U_Rbclk_buf_ch1 : BUFIO2
port map (
DIVCLK => ch1_rx_divclk,
IOCLK => open,
SERDESSTROBE => open,
I => ch1_rx_rec_clk_pad);
U_Rbclk_bufg_ch1 : BUFG
port map (
I => ch1_rx_divclk,
O => ch1_rx_rec_clk
);
ch0_gtp_locked <= ch0_gtp_pll_lockdet and ch0_gtp_reset_done;
ch0_tx_enc_err_o <= '0';
ch1_gtp_locked <= ch1_gtp_pll_lockdet and ch1_gtp_reset_done;
ch1_tx_enc_err_o <= '0';
U_align_ch0 : gtp_phase_align
generic map (
g_simulation => g_simulation)
port map (
gtp_rst_i => ch0_gtp_reset,
gtp_tx_clk_i => ch0_ref_clk_i,
gtp_tx_en_pma_phase_align_o => ch0_tx_en_pma_phase_align,
gtp_tx_pma_set_phase_o => ch0_tx_pma_set_phase,
align_en_i => ch0_gtp_locked,
align_done_o => ch0_align_done);
U_align_ch1 : gtp_phase_align
generic map (
g_simulation => g_simulation)
port map (
gtp_rst_i => ch1_gtp_reset,
gtp_tx_clk_i => ch1_ref_clk_i,
gtp_tx_en_pma_phase_align_o => ch1_tx_en_pma_phase_align,
gtp_tx_pma_set_phase_o => ch1_tx_pma_set_phase,
align_en_i => ch1_gtp_locked,
align_done_o => ch1_align_done);
U_bitslide_ch0 : gtp_bitslide
generic map (
g_simulation => g_simulation)
port map (
gtp_rst_i => ch0_gtp_reset,
gtp_rx_clk_i => ch0_rx_rec_clk,
gtp_rx_comma_det_i => ch0_rx_comma_det,
gtp_rx_byte_is_aligned_i => ch0_rx_byte_is_aligned,
serdes_ready_i => ch0_gtp_locked,
gtp_rx_slide_o => ch0_rx_slide,
gtp_rx_cdr_rst_o => ch0_rx_cdr_rst,
bitslide_o => ch0_rx_bitslide_int,
synced_o => ch0_rx_synced);
ch0_rx_bitslide_o <= ch0_rx_bitslide_int(3 downto 0);
U_bitslide_ch1 : gtp_bitslide
generic map (
g_simulation => g_simulation)
port map (
gtp_rst_i => ch1_gtp_reset,
gtp_rx_clk_i => ch1_rx_rec_clk,
gtp_rx_comma_det_i => ch1_rx_comma_det,
gtp_rx_byte_is_aligned_i => ch1_rx_byte_is_aligned,
serdes_ready_i => ch1_gtp_locked,
gtp_rx_slide_o => ch1_rx_slide,
gtp_rx_cdr_rst_o => ch1_rx_cdr_rst,
bitslide_o => ch1_rx_bitslide_int,
synced_o => ch1_rx_synced);
ch1_rx_bitslide_o <= ch1_rx_bitslide_int(3 downto 0);
ch0_rx_enable_output <= ch0_rx_synced and ch0_align_done;
ch1_rx_enable_output <= ch1_rx_synced and ch1_align_done;
U_sync_oen_ch0 : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => ch0_rx_rec_clk,
rst_n_i => '1',
data_i => ch0_rx_enable_output,
synced_o => ch0_rx_enable_output_synced,
npulse_o => open,
ppulse_o => open);
U_sync_oen_ch1 : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => ch1_rx_rec_clk,
rst_n_i => '1',
data_i => ch1_rx_enable_output,
synced_o => ch1_rx_enable_output_synced,
npulse_o => open,
ppulse_o => open);
p_force_proper_disparity_ch0 : process(ch0_ref_clk_i, ch0_gtp_reset)
begin
if (ch0_gtp_reset = '1') then
ch0_disparity_set <= '0';
ch0_tx_chardispval <= '0';
ch0_tx_chardispmode <= '0';
elsif rising_edge(ch0_ref_clk_i) then
if(ch0_disparity_set = '0' and ch0_tx_k_i = '1' and ch0_tx_data_i = x"bc" and ch0_align_done = '1') then
ch0_disparity_set <= '1';
if(g_force_disparity = 0) then
ch0_tx_chardispval <= '0' ;
else
ch0_tx_chardispval <= '1';
end if;
ch0_tx_chardispmode <= '1';
else
ch0_tx_chardispmode <= '0';
ch0_tx_chardispval <= '0';
end if;
end if;
end process;
p_force_proper_disparity_ch1 : process(ch1_ref_clk_i, ch1_gtp_reset)
begin
if (ch1_gtp_reset = '1') then
ch1_disparity_set <= '0';
ch1_tx_chardispval <= '0';
ch1_tx_chardispmode <= '0';
elsif rising_edge(ch1_ref_clk_i) then
if(ch1_disparity_set = '0' and ch1_tx_k_i = '1' and ch1_tx_data_i = x"bc" and ch1_align_done = '1') then
ch1_disparity_set <= '1';
if(g_force_disparity = 0) then
ch1_tx_chardispval <= '0';
else
ch1_tx_chardispval <= '1';
end if;
ch1_tx_chardispmode <= '1';
else
ch1_tx_chardispmode <= '0';
ch1_tx_chardispval <= '0';
end if;
end if;
end process;
p_gen_output_ch0 : process(ch0_rx_rec_clk, ch0_gtp_reset)
begin
if(ch0_gtp_reset = '1') then
ch0_rx_data_o <= (others => '0');
ch0_rx_k_o <= '0';
ch0_rx_enc_err_o <= '0';
elsif rising_edge(ch0_rx_rec_clk) then
if(ch0_rx_enable_output_synced = '0') then
-- make sure the output data is invalid when the link is down and that it will
-- trigger the sync loss detection
ch0_rx_data_o <= (others => '0');
ch0_rx_k_o <= '1';
ch0_rx_enc_err_o <= '1';
else
ch0_rx_data_o <= ch0_rx_data_int;
ch0_rx_k_o <= ch0_rx_k_int;
ch0_rx_enc_err_o <= ch0_rx_disperr or ch0_rx_invcode;
end if;
end if;
end process;
p_gen_output_ch1 : process(ch1_rx_rec_clk, ch1_rst_i)
begin
if(ch1_rst_i = '1') then
ch1_rx_data_o <= (others => '0');
ch1_rx_k_o <= '0';
ch1_rx_enc_err_o <= '0';
elsif rising_edge(ch1_rx_rec_clk) then
if(ch1_rx_enable_output_synced = '0') then
-- make sure the output data is invalid when the link is down and that it will
-- trigger the sync loss detection
ch1_rx_data_o <= (others => '0');
ch1_rx_k_o <= '1';
ch1_rx_enc_err_o <= '1';
else
ch1_rx_data_o <= ch1_rx_data_int;
ch1_rx_k_o <= ch1_rx_k_int;
ch1_rx_enc_err_o <= ch1_rx_disperr or ch1_rx_invcode;
end if;
end if;
end process;
-- drive the recovered clock output
ch0_rx_rbclk_o <= ch0_rx_rec_clk;
-- ch0_tx_disparity_o <= ch0_tx_rundisp_vec(0);
ch1_rx_rbclk_o <= ch1_rx_rec_clk;
-- ch1_tx_disparity_o <= ch1_tx_rundisp_vec(0);
end rtl;
platform/xilinx/wr_gtp_phy/wr_gtp_phy_spec.vhd 0 → 100644
View file @ 069fb021
library ieee;
use ieee.std_logic_1164.all;
entity wr_gtp_phy_spec_wrapper is
generic (
g_simulation : integer := 0);
port(
sfp_ref_clk_i : in std_logic;
sfp_ref_clk_o : out std_logic;
sfp_tx_data_i : in std_logic_vector(7 downto 0);
sfp_tx_k_i : in std_logic;
sfp_tx_disparity_o : out std_logic;
sfp_tx_enc_err_o : out std_logic;
sfp_rx_rbclk_o : out std_logic;
sfp_rx_data_o : out std_logic_vector(7 downto 0);
sfp_rx_k_o : out std_logic;
sfp_rx_enc_err_o : out std_logic;
sfp_rx_bitslide_o : out std_logic_vector(3 downto 0);
sfp_rst_i : in std_logic;
sfp_loopen_i : in std_logic;
sfp_txn_o : out std_logic;
sfp_txp_o : out std_logic;
sfp_rxn_i : in std_logic;
sfp_rxp_i : in std_logic;
sata0_ref_clk_i : in std_logic;
sata0_ref_clk_o : out std_logic;
sata0_tx_data_i : in std_logic_vector(7 downto 0);
sata0_tx_k_i : in std_logic;
sata0_tx_disparity_o : out std_logic;
sata0_tx_enc_err_o : out std_logic;
sata0_rx_rbclk_o : out std_logic;
sata0_rx_data_o : out std_logic_vector(7 downto 0);
sata0_rx_k_o : out std_logic;
sata0_rx_enc_err_o : out std_logic;
sata0_rx_bitslide_o : out std_logic_vector(3 downto 0);
sata0_rst_i : in std_logic;
sata0_loopen_i : in std_logic;
sata0_txn_o : out std_logic;
sata0_txp_o : out std_logic;
sata0_rxn_i : in std_logic;
sata0_rxp_i : in std_logic;
sata1_ref_clk_i : in std_logic;
sata1_ref_clk_o : out std_logic;
sata1_tx_data_i : in std_logic_vector(7 downto 0);
sata1_tx_k_i : in std_logic;
sata1_tx_disparity_o : out std_logic;
sata1_tx_enc_err_o : out std_logic;
sata1_rx_rbclk_o : out std_logic;
sata1_rx_data_o : out std_logic_vector(7 downto 0);
sata1_rx_k_o : out std_logic;
sata1_rx_enc_err_o : out std_logic;
sata1_rx_bitslide_o : out std_logic_vector(3 downto 0);
sata1_rst_i : in std_logic;
sata1_loopen_i : in std_logic;
sata1_txn_o : out std_logic;
sata1_txp_o : out std_logic;
sata1_rxn_i : in std_logic;
sata1_rxp_i : in std_logic;
fmc_ref_clk_i : in std_logic;
fmc_ref_clk_o : out std_logic;
fmc_tx_data_i : in std_logic_vector(7 downto 0);
fmc_tx_k_i : in std_logic;
fmc_tx_disparity_o : out std_logic;
fmc_tx_enc_err_o : out std_logic;
fmc_rx_rbclk_o : out std_logic;
fmc_rx_data_o : out std_logic_vector(7 downto 0);
fmc_rx_k_o : out std_logic;
fmc_rx_enc_err_o : out std_logic;
fmc_rx_bitslide_o : out std_logic_vector(3 downto 0);
fmc_rst_i : in std_logic;
fmc_loopen_i : in std_logic;
fmc_txn_o : out std_logic;
fmc_txp_o : out std_logic;
fmc_rxn_i : in std_logic;
fmc_rxp_i : in std_logic
);
end wr_gtp_phy_spec_wrapper;
architecture rtl of wr_gtp_phy_spec_wrapper is
component wr_gtp_phy_spartan6
generic (
g_simulation : integer);
port (
ch0_ref_clk_i : in std_logic;
ch0_ref_clk_o : out std_logic;
ch0_tx_data_i : in std_logic_vector(7 downto 0);
ch0_tx_k_i : in std_logic;
ch0_tx_disparity_o : out std_logic;
ch0_tx_enc_err_o : out std_logic;
ch0_rx_rbclk_o : out std_logic;
ch0_rx_data_o : out std_logic_vector(7 downto 0);
ch0_rx_k_o : out std_logic;
ch0_rx_enc_err_o : out std_logic;
ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch0_rst_i : in std_logic;
ch0_loopen_i : in std_logic;
ch1_ref_clk_i : in std_logic;
ch1_ref_clk_o : out std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch1_tx_k_i : in std_logic := '0';
ch1_tx_disparity_o : out std_logic;
ch1_tx_enc_err_o : out std_logic;
ch1_rx_data_o : out std_logic_vector(7 downto 0);
ch1_rx_rbclk_o : out std_logic;
ch1_rx_k_o : out std_logic;
ch1_rx_enc_err_o : out std_logic;
ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
pad_rxn0_i : in std_logic := '0';
pad_rxp0_i : in std_logic := '0';
pad_txn1_o : out std_logic;
pad_txp1_o : out std_logic;
pad_rxn1_i : in std_logic := '0';
pad_rxp1_i : in std_logic := '0');
end component;
begin -- rtl
U_GTP1 : wr_gtp_phy_spartan6
generic map (
g_simulation => g_simulation)
port map (
ch0_ref_clk_i => fmc_ref_clk_i,
ch0_ref_clk_o => fmc_ref_clk_o,
ch0_tx_data_i => fmc_tx_data_i,
ch0_tx_k_i => fmc_tx_k_i,
ch0_tx_disparity_o => fmc_tx_disparity_o,
ch0_tx_enc_err_o => fmc_tx_enc_err_o,
ch0_rx_rbclk_o => fmc_rx_rbclk_o,
ch0_rx_data_o => fmc_rx_data_o,
ch0_rx_k_o => fmc_rx_k_o,
ch0_rx_enc_err_o => fmc_rx_enc_err_o,
ch0_rx_bitslide_o => fmc_rx_bitslide_o,
ch0_rst_i => fmc_rst_i,
ch0_loopen_i => fmc_loopen_i,
ch1_ref_clk_i => sata0_ref_clk_i,
ch1_ref_clk_o => sata0_ref_clk_o,
ch1_tx_data_i => sata0_tx_data_i,
ch1_tx_k_i => sata0_tx_k_i,
ch1_tx_disparity_o => sata0_tx_disparity_o,
ch1_tx_enc_err_o => sata0_tx_enc_err_o,
ch1_rx_data_o => sata0_rx_data_o,
ch1_rx_rbclk_o => sata0_rx_rbclk_o,
ch1_rx_k_o => sata0_rx_k_o,
ch1_rx_enc_err_o => sata0_rx_enc_err_o,
ch1_rx_bitslide_o => sata0_rx_bitslide_o,
ch1_rst_i => sata0_rst_i,
ch1_loopen_i => sata0_loopen_i,
pad_txn0_o => fmc_txn_o,
pad_txp0_o => fmc_txp_o,
pad_rxn0_i => fmc_rxn_i,
pad_rxp0_i => fmc_rxp_i,
pad_txn1_o => sata0_txn_o,
pad_txp1_o => sata0_txp_o,
pad_rxn1_i => sata0_rxn_i,
pad_rxp1_i => sata0_rxp_i);
U_GTP2 : wr_gtp_phy_spartan6
generic map (
g_simulation => g_simulation)
port map (
ch0_ref_clk_i => sata1_ref_clk_i,
ch0_ref_clk_o => sata1_ref_clk_o,
ch0_tx_data_i => sata1_tx_data_i,
ch0_tx_k_i => sata1_tx_k_i,
ch0_tx_disparity_o => sata1_tx_disparity_o,
ch0_tx_enc_err_o => sata1_tx_enc_err_o,
ch0_rx_rbclk_o => sata1_rx_rbclk_o,
ch0_rx_data_o => sata1_rx_data_o,
ch0_rx_k_o => sata1_rx_k_o,
ch0_rx_enc_err_o => sata1_rx_enc_err_o,
ch0_rx_bitslide_o => sata1_rx_bitslide_o,
ch0_rst_i => sata1_rst_i,
ch0_loopen_i => sata1_loopen_i,
ch1_ref_clk_i => sfp_ref_clk_i,
ch1_ref_clk_o => sfp_ref_clk_o,
ch1_tx_data_i => sfp_tx_data_i,
ch1_tx_k_i => sfp_tx_k_i,
ch1_tx_disparity_o => sfp_tx_disparity_o,
ch1_tx_enc_err_o => sfp_tx_enc_err_o,
ch1_rx_data_o => sfp_rx_data_o,
ch1_rx_rbclk_o => sfp_rx_rbclk_o,
ch1_rx_k_o => sfp_rx_k_o,
ch1_rx_enc_err_o => sfp_rx_enc_err_o,
ch1_rx_bitslide_o => sfp_rx_bitslide_o,
ch1_rst_i => sfp_rst_i,
ch1_loopen_i => sfp_loopen_i,
pad_txn0_o => sata1_txn_o,
pad_txp0_o => sata1_txp_o,
pad_rxn0_i => sata1_rxn_i,
pad_rxp0_i => sata1_rxp_i,
pad_txn1_o => sfp_txn_o,
pad_txp1_o => sfp_txp_o,
pad_rxn1_i => sfp_rxn_i,
pad_rxp1_i => sfp_rxp_i);
end rtl;
platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd 0 → 100644
View file @ 069fb021
-------------------------------------------------------------------------------
-- Title : Deterministic Xilinx GTP wrapper - Spartan-6 top module
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wr_gtp_phy_spartan6.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2012-07-18
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Dual channel wrapper for Xilinx Spartan-6 GTP adapted for
-- deterministic delays at 1.25 Gbps.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 CERN / Tomasz Wlostowski
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-18 0.4 twlostow Initial release
-- 2011-02-07 0.5 twlostow Verified on Spartan6 GTP (single channel only)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.gencores_pkg.all;
use work.disparity_gen_pkg.all;
entity wr_gtx_phy_virtex6 is
generic (
-- set to non-zero value to speed up the simulation by reducing some delays
g_simulation : integer := 0;
g_use_slave_tx_clock : integer := 0;
g_use_bufr : boolean := false
);
port (
-- Reference 62.5 MHz clock input for the TX/RX logic (not the GTX itself)
clk_ref_i : in std_logic;
-- Reference 62.5 MHz clock for the GTX transceiver
clk_gtx_i : in std_logic;
-- TX path, clk_ref_i - synchronous:
-- data input (8 bits, not 8b10b-encoded)
tx_data_i : in std_logic_vector(15 downto 0);
-- 1 when tx_data_i contains a control code, 0 when it's a data byte
tx_k_i : in std_logic_vector(1 downto 0);
-- disparity of the currently transmitted 8b10b code (1 = plus, 0 = minus).
-- Necessary for the PCS to generate proper frame termination sequences.
-- Generated for the 2nd byte (LSB) of tx_data_i.
tx_disparity_o : out std_logic;
-- Encoding error indication (1 = error, 0 = no error)
tx_enc_err_o : out std_logic;
-- RX path, synchronous to ch0_rx_rbclk_o.
-- RX recovered clock
rx_rbclk_o : out std_logic;
-- 8b10b-decoded data output. The data output must be kept invalid before
-- the transceiver is locked on the incoming signal to prevent the EP from
-- detecting a false carrier.
rx_data_o : out std_logic_vector(15 downto 0);
-- 1 when the byte on rx_data_o is a control code
rx_k_o : out std_logic_vector(1 downto 0);
-- encoding error indication
rx_enc_err_o : out std_logic;
-- RX bitslide indication, indicating the delay of the RX path of the
-- transceiver (in UIs). Must be valid when ch0_rx_data_o is valid.
rx_bitslide_o : out std_logic_vector(4 downto 0);
-- reset input, active hi
rst_i : in std_logic;
loopen_i : in std_logic;
pad_txn_o : out std_logic;
pad_txp_o : out std_logic;
pad_rxn_i : in std_logic := '0';
pad_rxp_i : in std_logic := '0'
);
end wr_gtx_phy_virtex6;
architecture rtl of wr_gtx_phy_virtex6 is
component WHITERABBITGTX_WRAPPER_GTX
generic (
GTX_SIM_GTXRESET_SPEEDUP : integer;
GTX_TX_CLK_SOURCE : string;
GTX_POWER_SAVE : bit_vector);
port (
LOOPBACK_IN : in std_logic_vector(2 downto 0);
RXCHARISK_OUT : out std_logic_vector(1 downto 0);
RXDISPERR_OUT : out std_logic_vector(1 downto 0);
RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
RXBYTEISALIGNED_OUT : out std_logic;
RXCOMMADET_OUT : out std_logic;
RXSLIDE_IN : in std_logic;
RXDATA_OUT : out std_logic_vector(15 downto 0);
RXRECCLK_OUT : out std_logic;
RXUSRCLK2_IN : in std_logic;
RXCDRRESET_IN : in std_logic;
RXN_IN : in std_logic;
RXP_IN : in std_logic;
GTXRXRESET_IN : in std_logic;
MGTREFCLKRX_IN : in std_logic_vector(1 downto 0);
PLLRXRESET_IN : in std_logic;
RXPLLLKDET_OUT : out std_logic;
RXRESETDONE_OUT : out std_logic;
TXCHARISK_IN : in std_logic_vector(1 downto 0);
GTXTEST_IN : in std_logic_vector(12 downto 0);
TXDATA_IN : in std_logic_vector(15 downto 0);
TXOUTCLK_OUT : out std_logic;
TXUSRCLK2_IN : in std_logic;
TXRUNDISP_OUT : out std_logic_vector(1 downto 0);
TXN_OUT : out std_logic;
TXP_OUT : out std_logic;
TXDLYALIGNDISABLE_IN : in std_logic;
TXDLYALIGNMONENB_IN : in std_logic;
TXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
TXDLYALIGNRESET_IN : in std_logic;
TXENPMAPHASEALIGN_IN : in std_logic;
TXPMASETPHASE_IN : in std_logic;
GTXTXRESET_IN : in std_logic;
MGTREFCLKTX_IN : in std_logic_vector(1 downto 0);
PLLTXRESET_IN : in std_logic;
TXPLLLKDET_OUT : out std_logic;
TXRESETDONE_OUT : out std_logic);
end component;
component BUFG
port (
O : out std_ulogic;
I : in std_ulogic);
end component;
component BUFR
generic (
BUFR_DIVIDE : string := "BYPASS";
SIM_DEVICE : string := "VIRTEX6");
port (
O : out std_ulogic;
CE : in std_ulogic := '1';
CLR : in std_ulogic := '0';
I : in std_ulogic);
end component;
component gtp_phase_align_virtex6
generic (
g_simulation : integer);
port (
gtp_rst_i : in std_logic;
gtp_tx_clk_i : in std_logic;
gtp_tx_en_pma_phase_align_o : out std_logic;
gtp_tx_pma_set_phase_o : out std_logic;
gtp_tx_dly_align_disable_o : out std_logic;
gtp_tx_dly_align_reset_o : out std_logic;
align_en_i : in std_logic;
align_done_o : out std_logic);
end component;
component gtp_bitslide
generic (
g_simulation : integer;
g_target : string := "virtex6");
port (
gtp_rst_i : in std_logic;
gtp_rx_clk_i : in std_logic;
gtp_rx_comma_det_i : in std_logic;
gtp_rx_byte_is_aligned_i : in std_logic;
serdes_ready_i : in std_logic;
gtp_rx_slide_o : out std_logic;
gtp_rx_cdr_rst_o : out std_logic;
bitslide_o : out std_logic_vector(4 downto 0);
synced_o : out std_logic);
end component;
component gtx_reset
port (
clk_tx_i : in std_logic;
rst_i : in std_logic;
txpll_lockdet_i : in std_logic;
gtx_test_o : out std_logic_vector(12 downto 0));
end component;
signal trig0, trig1, trig2, trig3 : std_logic_vector(31 downto 0);
signal gtx_rst : std_logic;
signal gtx_loopback : std_logic_vector(2 downto 0) := "000";
signal gtx_reset_done : std_logic;
signal gtx_pll_lockdet : std_logic;
signal rst_synced : std_logic;
signal rst_d0 : std_logic;
signal reset_counter : unsigned(9 downto 0);
signal gtx_test : std_logic_vector(12 downto 0);
signal rx_rec_clk_bufin : std_logic;
signal rx_rec_clk : std_logic;
signal rx_comma_det : std_logic;
signal rx_byte_is_aligned : std_logic;
signal tx_dly_align_disable : std_logic;
signal tx_dly_align_reset : std_logic;
signal tx_en_pma_phase_align : std_logic;
signal tx_pma_set_phase : std_logic;
signal align_enable : std_logic;
signal align_done : std_logic;
signal tx_rst_done, rx_rst_done : std_logic;
signal txpll_lockdet, rxpll_lockdet : std_logic;
signal pll_lockdet : std_logic;
signal serdes_ready : std_logic;
signal rx_slide : std_logic;
signal rx_cdr_rst : std_logic;
signal rx_synced : std_logic;
signal rst_done : std_logic;
signal everything_ready : std_logic;
signal mgtrefclk_in : std_logic_vector(1 downto 0);
signal rx_k_int : std_logic_vector(1 downto 0);
signal rx_data_int : std_logic_vector(15 downto 0);
signal rx_disp_err, rx_code_err : std_logic_vector(1 downto 0);
signal tx_is_k_swapped : std_logic_vector(1 downto 0);
signal tx_data_swapped : std_logic_vector(15 downto 0);
signal cur_disp : t_8b10b_disparity;
signal tx_rundisp_v6 : std_logic_vector(1 downto 0);
begin -- rtl
tx_enc_err_o <= '0';
p_gen_reset : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
rst_d0 <= rst_i;
rst_synced <= rst_d0;
if(rst_synced = '1') then
reset_counter <= (others => '0');
else
if(reset_counter(reset_counter'left) = '0') then
reset_counter <= reset_counter + 1;
end if;
end if;
end if;
end process;
gtx_rst <= rst_synced or std_logic(not reset_counter(reset_counter'left));
U_Twice_Reset_Gen : gtx_reset
port map (
clk_tx_i => clk_ref_i,
rst_i => gtx_rst,
txpll_lockdet_i => txpll_lockdet,
gtx_test_o => gtx_test);
gen_rx_bufg : if(g_use_bufr = false) generate
U_BUF_RxRecClk : BUFG
port map (
I => rx_rec_clk_bufin,
O => rx_rec_clk);
end generate gen_rx_bufg;
gen_rx_bufr : if(g_use_bufr = true) generate
U_BUF_RxRecClk : BUFR
port map (
I => rx_rec_clk_bufin,
O => rx_rec_clk);
end generate gen_rx_bufr;
rx_rbclk_o <= rx_rec_clk;
tx_is_k_swapped <= tx_k_i(0) & tx_k_i(1);
tx_data_swapped <= tx_data_i(7 downto 0) & tx_data_i(15 downto 8);
U_GTX_INST : WHITERABBITGTX_WRAPPER_GTX
generic map (
GTX_SIM_GTXRESET_SPEEDUP => 1,
GTX_TX_CLK_SOURCE => "TXPLL",
GTX_POWER_SAVE => "0000110000")
port map (
LOOPBACK_IN => gtx_loopback,
RXCHARISK_OUT => rx_k_int,
RXDISPERR_OUT => rx_disp_err,
RXNOTINTABLE_OUT => rx_code_err,
RXBYTEISALIGNED_OUT => rx_byte_is_aligned,
RXCOMMADET_OUT => rx_comma_det,
RXSLIDE_IN => rx_slide,
RXDATA_OUT => rx_data_int,
RXRECCLK_OUT => rx_rec_clk_bufin,
RXUSRCLK2_IN => rx_rec_clk,
RXCDRRESET_IN => rx_cdr_rst,
RXN_IN => pad_rxn_i,
RXP_IN => pad_rxp_i,
GTXRXRESET_IN => gtx_rst,
MGTREFCLKRX_IN => mgtrefclk_in,
PLLRXRESET_IN => '0',
RXPLLLKDET_OUT => rxpll_lockdet,
RXRESETDONE_OUT => rx_rst_done,
TXCHARISK_IN => tx_is_k_swapped,
GTXTEST_IN => gtx_test,
TXDATA_IN => tx_data_swapped,
TXOUTCLK_OUT => open,
TXUSRCLK2_IN => clk_ref_i,
TXRUNDISP_OUT => tx_rundisp_v6,
TXN_OUT => pad_txn_o,
TXP_OUT => pad_txp_o,
TXDLYALIGNDISABLE_IN => tx_dly_align_disable,
TXDLYALIGNMONENB_IN => '1',
TXDLYALIGNMONITOR_OUT => open,
TXDLYALIGNRESET_IN => tx_dly_align_reset,
TXENPMAPHASEALIGN_IN => tx_en_pma_phase_align,
TXPMASETPHASE_IN => tx_pma_set_phase,
GTXTXRESET_IN => gtx_rst,
MGTREFCLKTX_IN => mgtrefclk_in,
PLLTXRESET_IN => '0',
TXPLLLKDET_OUT => txpll_lockdet,
TXRESETDONE_OUT => tx_rst_done);
mgtrefclk_in <= '0' & clk_gtx_i;
U_Phase_Align : gtp_phase_align_virtex6
generic map (
g_simulation => g_simulation)
port map (
gtp_rst_i => gtx_rst,
gtp_tx_clk_i => clk_ref_i,
gtp_tx_en_pma_phase_align_o => tx_en_pma_phase_align,
gtp_tx_pma_set_phase_o => tx_pma_set_phase,
gtp_tx_dly_align_disable_o => tx_dly_align_disable,
gtp_tx_dly_align_reset_o => tx_dly_align_reset,
align_en_i => align_enable,
align_done_o => align_done);
U_Bitslide : gtp_bitslide
generic map (
g_simulation => g_simulation,
g_target => "virtex6")
port map (
gtp_rst_i => gtx_rst,
gtp_rx_clk_i => rx_rec_clk,
gtp_rx_comma_det_i => rx_comma_det,
gtp_rx_byte_is_aligned_i => rx_byte_is_aligned,
serdes_ready_i => everything_ready,
gtp_rx_slide_o => rx_slide,
gtp_rx_cdr_rst_o => rx_cdr_rst,
bitslide_o => rx_bitslide_o,
synced_o => rx_synced);
rst_done <= rx_rst_done and tx_rst_done;
pll_lockdet <= txpll_lockdet and rxpll_lockdet;
serdes_ready <= rst_done and pll_lockdet;
align_enable <= serdes_ready;
everything_ready <= serdes_ready and align_done;
trig2(3) <= rx_rst_done;
trig2(4) <= tx_rst_done;
trig2(5) <= txpll_lockdet;
trig2(6) <= rxpll_lockdet;
trig2(7) <= align_done;
p_gen_rx_outputs : process(rx_rec_clk, gtx_rst)
begin
if(gtx_rst = '1') then
rx_data_o <= (others => '0');
rx_k_o <= (others => '0');
rx_enc_err_o <= '0';
elsif rising_edge(rx_rec_clk) then
if(everything_ready = '1' and rx_synced = '1') then
rx_data_o <= rx_data_int(7 downto 0) & rx_data_int(15 downto 8);
rx_k_o <= rx_k_int(0) & rx_k_int(1);
rx_enc_err_o <= rx_disp_err(0) or rx_disp_err(1) or rx_code_err(0) or rx_code_err(1);
else
rx_data_o <= (others => '1');
rx_k_o <= (others => '1');
rx_enc_err_o <= '1';
end if;
end if;
end process;
p_gen_tx_disparity : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if gtx_rst = '1' then
cur_disp <= RD_MINUS;
else
cur_disp <= f_next_8b10b_disparity16(cur_disp, tx_k_i, tx_data_i);
end if;
end if;
end process;
tx_disparity_o <= to_std_logic(cur_disp);
end rtl;
platform/xilinx/wr_xilinx_pkg.vhd 0 → 100644
View file @ 069fb021
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
use work.sysc_wbgen2_pkg.all;
use work.wr_fabric_pkg.all;
package wr_xilinx_pkg is
component wr_gtp_phy_spartan6
generic (
g_simulation : integer);
port (
gtp_clk_i : in std_logic;
ch0_ref_clk_i : in std_logic;
ch0_tx_data_i : in std_logic_vector(7 downto 0);
ch0_tx_k_i : in std_logic;
ch0_tx_disparity_o : out std_logic;
ch0_tx_enc_err_o : out std_logic;
ch0_rx_rbclk_o : out std_logic;
ch0_rx_data_o : out std_logic_vector(7 downto 0);
ch0_rx_k_o : out std_logic;
ch0_rx_enc_err_o : out std_logic;
ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch0_rst_i : in std_logic;
ch0_loopen_i : in std_logic;
ch1_ref_clk_i : in std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch1_tx_k_i : in std_logic := '0';
ch1_tx_disparity_o : out std_logic;
ch1_tx_enc_err_o : out std_logic;
ch1_rx_data_o : out std_logic_vector(7 downto 0);
ch1_rx_rbclk_o : out std_logic;
ch1_rx_k_o : out std_logic;
ch1_rx_enc_err_o : out std_logic;
ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
pad_rxn0_i : in std_logic := '0';
pad_rxp0_i : in std_logic := '0';
pad_txn1_o : out std_logic;
pad_txp1_o : out std_logic;
pad_rxn1_i : in std_logic := '0';
pad_rxp1_i : in std_logic := '0');
end component;
end wr_xilinx_pkg;
syn/spec/Manifest.py
View file @ 069fb021
......@@ -9,7 +9,8 @@ syn_package = "fgg484"
syn_top = "wr_nic_sdb_top"
syn_project = "wr_nic.xise"
modules = { "local" :
modules = {"local" :
[ "../../top/spec",
"../../platform/xilinx/chipscope" ]
"../../platform/xilinx"
]
}
syn/spec/wr_nic.xise
View file @ 069fb021
......@@ -19,9 +19,6 @@
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
<file xil_pn:name="../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>
<properties>
......@@ -35,7 +32,7 @@
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -81,7 +78,6 @@
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -93,6 +89,7 @@
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
......@@ -132,9 +129,8 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|wr_nic_top|rtl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../top/spec/wr_nic_top.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/wr_nic_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|wr_nic_sdb_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/wr_nic_sdb_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -156,7 +152,7 @@
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
......@@ -165,6 +161,7 @@
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
......@@ -175,7 +172,7 @@
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="High" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -195,7 +192,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="wr_nic_top" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="wr_nic_sdb_top" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
......@@ -209,16 +206,15 @@
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="wr_nic_top_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="wr_nic_top_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="wr_nic_top_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="wr_nic_top_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="wr_nic_sdb_top_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="wr_nic_sdb_top_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="wr_nic_sdb_top_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="wr_nic_sdb_top_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
......@@ -248,7 +244,7 @@
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -332,643 +328,802 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-07-09T19:28:02" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3A46D41074E4A469C2B97201F9FF0588" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-08-01T12:21:26" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="9842D9F52ECDAB716EBA636F10DC18B0" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<libraries>
<library xil_pn:name="blk_mem_gen_v4_1"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</libraries>
<libraries/>
<files>
<file xil_pn:name="../../top/spec/wr_nic_top.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/wr-switch-hdl/modules/wrsw_swcore/ram_bug/buggy_ram.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../ip_cores/wr-switch-hdl/platform/virtex6/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../ip_cores/wr-switch-hdl/platform/virtex6/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../platform/xilinx/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../platform/xilinx/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../top/spec/wr_nic_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../top/spec/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
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<file xil_pn:name="../../top/spec/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../platform/xilinx/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../platform/xilinx/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../modules/wrsw_nic/nic_constants_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../modules/wrsw_nic/nic_descriptors_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../modules/wrsw_dio/wrnic_sdb_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../modules/wrsw_nic/nic_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../modules/wrsw_nic/nic_descriptor_manager.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../modules/wrsw_dio/pulse_gen_pl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
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<file xil_pn:name="../../modules/wrsw_nic/nic_rx_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../modules/wrsw_dio/immed_pulse_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
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<file xil_pn:name="../../modules/wrsw_nic/nic_tx_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../modules/wrsw_dio/dummy_time.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
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<file xil_pn:name="../../modules/wrsw_nic/nic_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
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<file xil_pn:name="../../modules/wrsw_nic/nic_elastic_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
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<file xil_pn:name="../../modules/wrsw_nic/nic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
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<file xil_pn:name="../../modules/wrsw_nic/xwrsw_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
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<file xil_pn:name="../../modules/wrsw_nic/wrsw_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
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<file xil_pn:name="../../modules/wrsw_txtsu/xwrsw_txtsu.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
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<file xil_pn:name="../../modules/wrsw_txtsu/wrsw_txtsu_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
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<file xil_pn:name="../../modules/wrsw_txtsu/wrsw_txtsu_pkg.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/wr-switch-hdl/modules/wrsw_nic/nic_constants_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
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<file xil_pn:name="../../modules/wrsw_dio/wrsw_dio_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<file xil_pn:name="../../ip_cores/wr-switch-hdl/modules/wrsw_nic/nic_descriptors_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
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<file xil_pn:name="../../modules/wrsw_dio/xwrsw_dio.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/wr-switch-hdl/modules/wrsw_nic/nic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../modules/wrsw_dio/pulse_gen_pl.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/wr-switch-hdl/modules/wrsw_nic/nic_descriptor_manager.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../modules/wrsw_dio/immed_pulse_counter.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../modules/wrsw_dio/dummy_time.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/wr-switch-hdl/modules/wrsw_nic/nic_buffer.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/wr-switch-hdl/modules/wrsw_nic/nic_elastic_buffer.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/wr-switch-hdl/modules/wrsw_nic/xwrsw_nic.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/wr-switch-hdl/modules/wrsw_nic/wrsw_nic.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/wr-switch-hdl/modules/wrsw_txtsu/wrsw_txtsu_wb.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/wr-switch-hdl/modules/wrsw_txtsu/xwrsw_txtsu.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/wr-switch-hdl/modules/wrsw_shared_types_pkg.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/wr-switch-hdl/modules/wrsw_swcore/swc_swcore_pkg.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/wr-switch-hdl/modules/wrsw_swcore/old_allocator/swc_multiport_page_allocator.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/wr-switch-hdl/modules/wrsw_swcore/old_allocator/swc_page_alloc_old.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/wr-switch-hdl/modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="234"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="235"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="236"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="237"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="238"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="239"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="240"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="241"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="242"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<file xil_pn:name="../../modules/wrsw_dio/wrsw_dio_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="243"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="244"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="245"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="246"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="247"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="248"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="249"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="250"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="251"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="252"/>
</file>
<file xil_pn:name="../../modules/wrsw_dio/wrsw_dio.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="354"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<file xil_pn:name="../../platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="253"/>
</file>
<file xil_pn:name="../../platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="254"/>
</file>
<file xil_pn:name="../../platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="255"/>
</file>
<file xil_pn:name="../../platform/xilinx/wr_gtp_phy/gtx_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="256"/>
</file>
<file xil_pn:name="../../platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="257"/>
</file>
<file xil_pn:name="../../platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="258"/>
</file>
<file xil_pn:name="../../platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="259"/>
</file>
<file xil_pn:name="../../platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="260"/>
</file>
<file xil_pn:name="../../top/spec/wr_nic_sdb_top.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="261"/>
</file>
</files>
<bindings>
<binding xil_pn:location="/wr_nic_top" xil_pn:name="../../top/spec/wr_nic_top.ucf"/>
</bindings>
<bindings/>
<version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
</project>
testbench/wrsw_nic/Manifest.py deleted 100644 → 0
View file @ a216d4a9
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
vlog_opt="+incdir+../../sim"
files = [ "main.sv" ]
modules = { "local" : "../.." }
testbench/wrsw_nic/main.sv deleted 100644 → 0
View file @ a216d4a9
`timescale 1ns/1ps
`include "tbi_utils.sv"
`include "simdrv_defs.svh"
`include "if_wb_master.svh"
module main;
wire clk_ref;
wire clk_sys;
wire rst_n;
IWishboneMaster WB (
.clk_i(clk_sys),
.rst_n_i(rst_n));
tbi_clock_rst_gen
#(
.g_rbclk_period(8000))
clkgen(
.clk_ref_o(clk_ref),
.clk_sys_o(clk_sys),
.rst_n_o(rst_n)
);
wire clk_sys_dly;
assign #10 clk_sys_dly = clk_sys;
wrsw_nic
DUT (
.clk_sys_i (clk_sys),
.rst_n_i (rst_n),
.wb_cyc_i (WB.master.cyc),
.wb_stb_i (WB.master.stb),
.wb_we_i (WB.master.we),
.wb_sel_i (4'b1111),
.wb_adr_i (WB.master.adr[31:0]),
.wb_dat_i (WB.master.dat_o),
.wb_dat_o (WB.master.dat_i),
.wb_ack_o (WB.master.ack),
.wb_stall_o(WB.master.stall)
/*.dma_cyc_i (WB.master.cyc),
.dma_stb_i (WB.master.stb),
.dma_we_i (WB.master.we),
.dma_sel_i (4'b1111),
.dma_adr_i (WB.master.adr[31:0]),
.dma_dat_i (WB.master.dat_o),
.dma_dat_o (WB.master.dat_i),
.dma_ack_o (WB.master.ack),
.dma_stall_o(WB.master.stall)*/
);
initial begin
CWishboneAccessor acc;
uint64_t data;
@(posedge rst_n);
repeat(3) @(posedge clk_sys);
#1us;
acc = WB.get_accessor();
acc.set_mode(PIPELINED);
#1us;
acc.write(32'h00000000, 'hdeadbeef);
//acc.write(32'h00008000, 'hdeadbeef);
//#1us;
acc.write(32'h00000004, 'hcafebabe);
//acc.write(32'h00008004, 'hcafebabe);
acc.read(32'h00000000, data);
acc.read(32'h00000004, data);
//acc.read(32'h00008000, data);
//acc.read(32'h00008004, data);
acc.write(32'h0000004c, 'habcdef00);
acc.read(32'h00000004c, data);
end
endmodule // main
testbench/wrsw_nic/run.do deleted 100644 → 0
View file @ a216d4a9
vlog -sv main.sv +incdir+"." +incdir+../../sim
make -f Makefile
vsim -L unisim -t 10fs work.main -voptargs="+acc"
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 25us
wave zoomfull
radix -hexadecimal
testbench/wrsw_nic/wave.do deleted 100644 → 0
View file @ a216d4a9
onerror {resume}
quietly WaveActivateNextPane {} 0
#add wave -noupdate /main/DUT/g_USE_DMA
add wave -noupdate /main/DUT/clk_sys_i
add wave -noupdate /main/DUT/rst_n_i
#add wave -divider DMA
#add wave -noupdate /main/DUT/dma_cyc_i
#add wave -noupdate /main/DUT/dma_stb_i
#add wave -noupdate /main/DUT/dma_we_i
#add wave -noupdate /main/DUT/dma_sel_i
#add wave -noupdate /main/DUT/dma_adr_i
#add wave -noupdate /main/DUT/dma_dat_i
#add wave -noupdate /main/DUT/dma_dat_o
#add wave -noupdate /main/DUT/dma_ack_o
#add wave -noupdate /main/DUT/dma_stall_o
add wave -divider WB
add wave -noupdate /main/DUT/wb_cyc_i
add wave -noupdate /main/DUT/wb_stb_i
add wave -noupdate /main/DUT/wb_we_i
add wave -noupdate /main/DUT/wb_sel_i
add wave -noupdate /main/DUT/wb_adr_i
add wave -noupdate /main/DUT/wb_dat_i
add wave -noupdate /main/DUT/wb_dat_o
add wave -noupdate /main/DUT/wb_ack_o
add wave -noupdate /main/DUT/wb_stall_o
add wave -divider RAM
add wave -noupdate /main/DUT/U_Wrapped_NIC/U_BUFFER/wb_cyc_i
add wave -noupdate /main/DUT/U_Wrapped_NIC/U_BUFFER/wb_stb_i
add wave -noupdate /main/DUT/U_Wrapped_NIC/U_BUFFER/wb_we_i
add wave -noupdate /main/DUT/U_Wrapped_NIC/U_BUFFER/wb_addr_i
add wave -noupdate /main/DUT/U_Wrapped_NIC/U_BUFFER/wb_data_i
add wave -noupdate /main/DUT/U_Wrapped_NIC/U_BUFFER/wb_data_o
add wave -divider BRAM
add wave -noupdate /main/DUT/U_Wrapped_NIC/U_BUFFER/RAM/qb_o
#add wave -noupdate /main/DUT/U_Wrapped_NIC/U_BUFFER/RAM/ram(0:5)
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {90685000000 fs} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {90556826170 fs} {90813173830 fs}
top/spec/wr_nic_sdb_top.vhd
View file @ 069fb021
......@@ -64,17 +64,34 @@ use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.wishbone_pkg.all;
--library work;
--use work.wishbone_pkg.all;
--use work.gn4124_core_pkg.all;
--use work.gencores_pkg.all;
--use work.wrcore_pkg.all;
--use work.wr_fabric_pkg.all;
--use work.endpoint_pkg.all;
--use work.genram_pkg.all;
--use work.wr_xilinx_pkg.all;
--use work.wrnic_sdb_pkg.all;
use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.wrsw_txtsu_pkg.all;
use work.genram_pkg.all;
use work.wr_xilinx_pkg.all;
--use work.etherbone_pkg.all;
--library UNISIM;
--use UNISIM.vcomponents.all;
library work;
use work.wishbone_pkg.all;
use work.endpoint_pkg.all;
use work.wrnic_sdb_pkg.all;
entity wr_nic_sdb_top is
generic
(
......@@ -143,7 +160,7 @@ entity wr_nic_sdb_top is
button1_i : in std_logic;
button2_i : in std_logic;
thermo_id : inout std_logic; -- 1-Wire interface to DS18B20
thermo_id : inout std_logic; -- 1-Wire interface to DS18B20 on SPEC
-------------------------------------------------------------------------
-- SFP pins
......@@ -380,27 +397,29 @@ architecture rtl of wr_nic_sdb_top is
end component; --DIO core
-- -- DEBUG STUFF
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
-- component chipscope_ila
-- port (
-- CONTROL : inout std_logic_vector(35 downto 0);
-- CLK : in std_logic;
-- TRIG0 : in std_logic_vector(31 downto 0);
-- TRIG1 : in std_logic_vector(31 downto 0);
-- TRIG2 : in std_logic_vector(31 downto 0);
-- TRIG3 : in std_logic_vector(31 downto 0));
-- end component;
--
-- component chipscope_icon
-- port (
-- CONTROL0 : inout std_logic_vector (35 downto 0));
-- end component;
-- signal CONTROL : std_logic_vector(35 downto 0);
-- signal CLK : std_logic;
-- signal TRIG0 : std_logic_vector(31 downto 0);
-- signal TRIG1 : std_logic_vector(31 downto 0);
-- signal TRIG2 : std_logic_vector(31 downto 0);
-- signal TRIG3 : std_logic_vector(31 downto 0);
signal CONTROL : std_logic_vector(35 downto 0);
signal CLK : std_logic;
signal TRIG0 : std_logic_vector(31 downto 0);
signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector (35 downto 0));
end component;
------------------------------------------------------------------------------
-- Constants declaration
......@@ -820,8 +839,8 @@ begin
g_with_external_clock_input => true,
g_aux_clks => 1,
g_ep_rxbuf_size => 1024,
g_dpram_initf => "../../../wrpc-sw/wrc.ram", -- Path to the lm32 file (wrc.ram) of the wrpc_sw repository
g_dpram_size => 20480,
g_dpram_initf => "../../../wrpc-sw/wrc.ram", --Path to the lm32 file (wrc.ram) of the wrpc_sw repository
g_dpram_size => 90112/4,-- 20480, it is the old value, it does not fit anymore
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
......@@ -871,8 +890,8 @@ begin
owr_en_o => owr_en,
owr_i => owr_i,
slave_i => cbar_master_o(0), -- cbar_slave_i, --
slave_o => cbar_master_i(0), -- cbar_slave_o, --
slave_i => cbar_master_o(0), --cbar_slave_i, --
slave_o => cbar_master_i(0), --cbar_slave_o, --
wrf_src_o => nic_snk_in,
wrf_src_i => nic_snk_out,
......@@ -1083,13 +1102,13 @@ begin
tm_cycles_i => tm_cycles,
slave_i => cbar_master_o(4),
slave_o => cbar_master_i(4),
slave_o => cbar_master_i(4)
-- Chipscope, debugging signals
TRIG0 => TRIG0,
TRIG1 => TRIG1
--TRIG2 => TRIG2,
--TRIG3 => TRIG3,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3,
);
gen_dio_iobufs : for i in 0 to 4 generate
......@@ -1122,7 +1141,7 @@ begin
-- .............................................
-- ............... DEBUGGING ...................
-- .............................................
--
-- chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
......@@ -1151,15 +1170,15 @@ begin
-- TRIG2(30 downto 29) <= GPIO(1 downto 0);
-- TRIG2(31) <= vic_irq;
--
-- -- DIO wb bus
-- TRIG3(18 downto 0) <= cbar_master_o(4).adr (18 downto 0);
-- TRIG3(19) <= cbar_master_o(4).stb;
-- -- crossbar slaves wb bus (0 wrpc, 4 dio, ...)
-- TRIG3(18 downto 0) <= cbar_master_o(0).adr (18 downto 0);
-- TRIG3(19) <= cbar_master_o(0).stb;
-- --TRIG3(20) <= cbar_master_o(4).dat;
-- TRIG3(21) <= cbar_master_o(4).cyc;
-- TRIG3(22) <= cbar_master_o(4).we;
-- TRIG3(26 downto 23) <= cbar_master_o(4).sel;
-- TRIG3(27) <= cbar_master_i(4).ack;
-- TRIG3(28) <= cbar_master_i(4).stall;
-- TRIG3(21) <= cbar_master_o(0).cyc;
-- TRIG3(22) <= cbar_master_o(0).we;
-- TRIG3(26 downto 23) <= cbar_master_o(0).sel;
-- TRIG3(27) <= cbar_master_i(0).ack;
-- TRIG3(28) <= cbar_master_i(0).stall;
--
-- -- Peripherals interrupts
-- TRIG3(29) <= vic_slave_irq(0);
......
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