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Distributed Direct Digital Synthesis over White Rabbit D3S
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Last edited by Erik van der Bij Mar 23, 2022
Page history

Project description

This project aims at distributing periodic (mainly clock) signals of arbitrary frequencies over a White Rabbit network. A clock is encoded at a master node and unidirectionally broadcast to any number of receiver nodes, which recover an in-phase copy of the original signal. Number of distributed clocks depends only on network bandwidth, required latency and acceptable accuracy level.

Possible applications in the accelerators are:

  • Beam-synchronous timing
  • RF clock distribution
  • RF or beam-synchronous signal acquisition

Requirements

Note*: this is just a preliminary specification for the proof-of-concept demo project, it may be modified.

  • Frequency range: 0 - 250 MHz (to be able to distribute 40.079 MHz LHC bunch crossing frequency and 200 MHz SPS RF clocks)
  • System must accept clocks with abrupt frequency changes (i.e. FSK modulation), such as the SPS RF clock for ions.
  • Required jitter: < 10 ps rms (10 Hz - 10 MHz). More jitter allowed for rapidly changing input clocks (e.g. SPS Ions).
  • Accuracy: < 1ns
  • Precision: < 100 ps
  • Hardware platform: FMC DDS on a SPEC carrier or SVEC carrier

Project repositories

  • Hardware (schematics/PCB design): FMC DDS Mezzanine project
  • Gateware (VHDL) is currently hosted in the Mock Turtle (a.k.a. WR Node Core) HDL repository:
    > * VHDL DDS Core
    > * Top level for the SPEC carrier
    > * Top level for the SVEC carrier
  • Embedded software © is currently hosted in the Mock Turtle (a.k.a. WR Node Core) software repository

The Git repository in this project binds together the right versions of the respective hardware, softaware & gateware repos and scripts allowing to build and set up a WR DDS test system.

Documentation & HowTo-s

  • Frequently Asked Questions
  • Setup for CERN VME platforms

Contacts

Commercial producers

  • Creotech

General questions about project

  • Tomasz Włostowski - CERN

Status

Date Event
01-04-2013 Project started.
03-04-2013 Specification ready.
10-04-2013 V0 schematics created & reviewed.
15-04-2013 FMC hardware order sent to company.
20-04-2013 Started VHDL/software development.
24-04-2013 Received & powered up 2 DDS mezzanines.
08-05-2013 First working demo design.
15-05-2013 2013 Demo presented on PH-ESE seminar.
20-10-2015 Mock Turtle-based RF distribution system presented on ICALEPCS' 2015.
01-12-2015 Project specification extended to include SPS ion RF clock.
20-01-2016 Successful simulation of distributing SPS ion RF clock using undersampling ADC.
2022 Project was a proof of concept. Project finished.

Tomasz Wlostowski - 21 January 2016

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  • Documents
  • Home
  • Rf distribution demo
  • Setup cern vme
  • Faq
  • Documents
    • 2013 demo presentation in ph ese
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