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Maciej Lipinski authored
- this new module contains the PLLs, buffers, PHY and DAC arbiter that would be usually copied in the top_level of each design - it was created to make integration of WRPC in user's design easier and cleaner - it is expected to be extended with more families in which case, only the PHY is expected to change - similar module will be created for Altera
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| ip_cores | ||
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| syn/spec_1_1/wr_core_demo | ||
| testbench | ||
| top | ||
| .gitignore | ||
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| Manifest.py |