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Opened May 12, 2020 by Maciej Lipinski@lipinskimm
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wr streamers: tx FIFO interace - tx_dreq_o is synchronous to clk_ref only

It should depend on the configuration, it should be synchronous to clk_sys_i by default, see:

xtx_streamers.vhd

U_SyncReset_to_RefClk : gc_sync_ffs port map ( clk_i => clk_ref_i, rst_n_i => '1', data_i => rst_int_n, synced_o => rst_n_ref);

U_SyncLinkOK_to_RefClk : gc_sync_ffs port map ( clk_i => clk_ref_i, rst_n_i => rst_n_ref, data_i => link_ok_i, synced_o => link_ok_ref);

U_SyncLinkDelayExpired_to_RefClk : gc_sync_ffs port map ( clk_i => clk_ref_i, rst_n_i => rst_n_ref, data_i => link_ok_delay_expired, synced_o => link_ok_delay_expired_ref);

p_tx_dreq_gen : process(link_ok_delay_expired_ref, tx_almost_full, link_ok_ref) begin if link_ok_delay_expired_ref = '0' then tx_dreq_o <= '0'; else tx_dreq_o <= not tx_almost_full and link_ok_ref; end if; end process;

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Reference: project/wr-cores#85