improve clocks handling
In spec_top, 125MHz reference clock is now always routed through a BUFG component. This happens e.g. when chipscope is instantiated. To prevent this, we should manually instantiate BUFG in the VHDL file.
In spec_top, 125MHz reference clock is now always routed through a BUFG component. This happens e.g. when chipscope is instantiated. To prevent this, we should manually instantiate BUFG in the VHDL file.