GTP reference clock is connected to CLK01 and/or CLK11 in our instance of GTP_DUAL.

According to UG386, figure 2-3, page 41, REFSELDYPLLx must be set to '4' to select
CLK10/CLK11.

This is done in order to ensure backward compatibility with previous versions of
the Xilinx platform support package.

Otherwise, counter gets crazy when watchdog resets the swcore and feeds all the
endpoints and NIC with ack=1.

This way one Tx OOB word may be lost, and tx timestamp won't be generated
causing _wrn_start_xmit: descriptor overflow: tx timestamp pending_ message from
wr-nic driver

- removed declarations of unused signals
- reduced padding_size to bits needed for padding possible runt Ethernet
  frames
- simplified signal assignments and conditions in FSM (e.g. no need to
  check if needs_padding = 1 and padding_size /= 0, because when former
  is true, the latter is always true too)
- moved assignment of outputs validated with other outputs outside FSM
  to simplify the logic (fake rtu decision)