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White Rabbit core collection
Commit fe370b69 authored by Tristan Gingold's avatar Tristan Gingold
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board/fasec: support aux pll

parent 8e79d0bc
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Showing with 9 additions and 3 deletions
board/fasec/xwrc_board_fasec.vhd
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......@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-08-02
-- Last update: 2017-08-02
-- Last update: 2022-07-20
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -43,7 +43,7 @@ library work;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wishbone_pkg.all;
use work.etherbone_pkg.all;
-- use work.etherbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.streamers_pkg.all;
......@@ -78,7 +78,9 @@ entity xwrc_board_fasec is
g_diag_ver : integer := 0;
-- size the generic diag interface
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0
g_diag_rw_size : integer := 0;
-- User-defined PLL_BASE outputs config
g_aux_pll_cfg : t_auxpll_cfg_array := c_AUXPLL_CFG_ARRAY_DEFAULT
);
port (
---------------------------------------------------------------------------
......@@ -105,6 +107,8 @@ entity xwrc_board_fasec is
clk_sys_62m5_o : out std_logic;
-- 125MHz ref clock output
clk_ref_125m_o : out std_logic;
-- Configurable (with g_aux_pll_cfg) clock outputs from the main PLL_BASE
clk_pll_aux_o : out std_logic_vector(3 downto 0);
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
......@@ -357,6 +361,7 @@ begin -- architecture struct
g_fpga_family => "kintex7",
g_with_external_clock_input => g_with_external_clock_input,
g_use_default_plls => TRUE,
g_aux_pll_cfg => g_aux_pll_cfg,
g_simulation => g_simulation)
port map (
areset_n_i => areset_n_i,
......@@ -375,6 +380,7 @@ begin -- architecture struct
clk_62m5_sys_o => clk_pll_62m5,
clk_125m_ref_o => clk_pll_125m,
clk_62m5_dmtd_o => clk_pll_dmtd,
clk_pll_aux_o => clk_pll_aux_o,
pll_locked_o => pll_locked,
clk_10m_ext_o => clk_10m_ext,
phy16_o => phy16_to_wrc,
......
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