Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
White Rabbit core collection
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
30
Issues
30
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Schedules
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
White Rabbit core collection
Commits
fe045ba6
Commit
fe045ba6
authored
Feb 14, 2017
by
Dimitris Lampridis
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
cleanup and improvements to reduce number of warnings generated by some of the cores
parent
34bd6f04
Hide whitespace changes
Inline
Side-by-side
Showing
35 changed files
with
511 additions
and
353 deletions
+511
-353
Manifest.py
Manifest.py
+6
-18
vme64x-core
ip_cores/vme64x-core
+1
-1
Manifest.py
modules/Manifest.py
+17
-0
wr_fabric_pkg.vhd
modules/fabric/wr_fabric_pkg.vhd
+3
-0
xwrf_mux.vhd
modules/fabric/xwrf_mux.vhd
+3
-1
endpoint_pkg.vhd
modules/wr_endpoint/endpoint_pkg.vhd
+13
-2
endpoint_private_pkg.vhd
modules/wr_endpoint/endpoint_private_pkg.vhd
+11
-11
ep_1000basex_pcs.vhd
modules/wr_endpoint/ep_1000basex_pcs.vhd
+37
-13
ep_rtu_header_extract.vhd
modules/wr_endpoint/ep_rtu_header_extract.vhd
+21
-15
ep_rx_buffer.vhd
modules/wr_endpoint/ep_rx_buffer.vhd
+5
-4
ep_rx_crc_size_check.vhd
modules/wr_endpoint/ep_rx_crc_size_check.vhd
+2
-4
ep_rx_oob_insert.vhd
modules/wr_endpoint/ep_rx_oob_insert.vhd
+37
-35
ep_rx_path.vhd
modules/wr_endpoint/ep_rx_path.vhd
+16
-3
ep_rx_pcs_8bit.vhd
modules/wr_endpoint/ep_rx_pcs_8bit.vhd
+2
-1
ep_rx_status_reg_insert.vhd
modules/wr_endpoint/ep_rx_status_reg_insert.vhd
+3
-0
ep_rx_wb_master.vhd
modules/wr_endpoint/ep_rx_wb_master.vhd
+7
-7
ep_timestamping_unit.vhd
modules/wr_endpoint/ep_timestamping_unit.vhd
+18
-4
ep_ts_counter.vhd
modules/wr_endpoint/ep_ts_counter.vhd
+1
-3
ep_tx_crc_inserter.vhd
modules/wr_endpoint/ep_tx_crc_inserter.vhd
+7
-10
ep_tx_header_processor.vhd
modules/wr_endpoint/ep_tx_header_processor.vhd
+9
-9
ep_tx_path.vhd
modules/wr_endpoint/ep_tx_path.vhd
+9
-8
ep_tx_pcs_16bit.vhd
modules/wr_endpoint/ep_tx_pcs_16bit.vhd
+1
-2
ep_tx_pcs_8bit.vhd
modules/wr_endpoint/ep_tx_pcs_8bit.vhd
+2
-4
wr_endpoint.vhd
modules/wr_endpoint/wr_endpoint.vhd
+41
-27
xwr_endpoint.vhd
modules/wr_endpoint/xwr_endpoint.vhd
+10
-6
wr_mini_nic.vhd
modules/wr_mini_nic/wr_mini_nic.vhd
+55
-49
xwr_mini_nic.vhd
modules/wr_mini_nic/xwr_mini_nic.vhd
+2
-0
wr_pps_gen.vhd
modules/wr_pps_gen/wr_pps_gen.vhd
+7
-11
spll_aligner.vhd
modules/wr_softpll_ng/spll_aligner.vhd
+0
-1
wr_softpll_ng.vhd
modules/wr_softpll_ng/wr_softpll_ng.vhd
+56
-19
xwr_softpll_ng.vhd
modules/wr_softpll_ng/xwr_softpll_ng.vhd
+1
-3
wr_core.vhd
modules/wrc_core/wr_core.vhd
+104
-74
wrc_periph.vhd
modules/wrc_core/wrc_periph.vhd
+3
-2
wrcore_pkg.vhd
modules/wrc_core/wrcore_pkg.vhd
+0
-3
xwr_core.vhd
modules/wrc_core/xwr_core.vhd
+1
-3
No files found.
Manifest.py
View file @
fe045ba6
fetchto
=
"ip_cores"
modules
=
{
"local"
:
[
"modules/fabric"
,
"modules/wr_tbi_phy"
,
"modules/timing"
,
"modules/wr_mini_nic"
,
"modules/wr_softpll_ng"
,
"modules/wr_endpoint"
,
"modules/wr_pps_gen"
,
"modules/wr_dacs"
,
"modules/wr_si57x_interface"
,
"modules/wr_eca"
,
"modules/wr_tlu"
,
"modules/wrc_core"
,
"modules/wr_streamers"
,
"platform"
]
}
modules
=
{
"local"
:
[
"modules"
,
"platform"
,
],
}
vme64x-core
@
6994f35b
Subproject commit
52d537441e6187619dee7b908534d72408cc03f0
Subproject commit
6994f35bdbe717f3df69e7226ee35d507ea87f5f
modules/Manifest.py
0 → 100644
View file @
fe045ba6
modules
=
{
"local"
:
[
"fabric"
,
"wr_tbi_phy"
,
"timing"
,
"wr_mini_nic"
,
"wr_softpll_ng"
,
"wr_endpoint"
,
"wr_pps_gen"
,
"wr_dacs"
,
"wr_si57x_interface"
,
"wr_eca"
,
"wr_tlu"
,
"wrc_core"
,
"wr_streamers"
,
]
}
modules/fabric/wr_fabric_pkg.vhd
View file @
fe045ba6
...
...
@@ -62,6 +62,9 @@ package wr_fabric_pkg is
function
f_marshall_wrf_status
(
stat
:
t_wrf_status_reg
)
return
std_logic_vector
;
function
f_unmarshall_wrf_status
(
stat
:
std_logic_vector
)
return
t_wrf_status_reg
;
constant
c_wrf_status_init_value
:
t_wrf_status_reg
:
=
(
'0'
,
'0'
,
'0'
,
'0'
,
'0'
,
(
others
=>
'0'
));
constant
c_dummy_src_in
:
t_wrf_source_in
:
=
(
'0'
,
'0'
,
'0'
,
'0'
);
constant
c_dummy_snk_in
:
t_wrf_sink_in
:
=
...
...
modules/fabric/xwrf_mux.vhd
View file @
fe045ba6
...
...
@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2011-08-11
-- Last update: 201
3-05-1
3
-- Last update: 201
7-02-0
3
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -154,6 +154,7 @@ begin
'1'
;
mux_snk_o
(
J
)
.
err
<=
ep_src_i
.
err
when
(
mux
/=
MUX_SEL
and
mux_select
(
J
)
=
'1'
)
else
'0'
;
mux_snk_o
(
J
)
.
rty
<=
'0'
;
end
generate
;
ep_src_o
.
cyc
<=
mux_snk_i
(
f_hot_to_bin
(
mux_select
))
.
cyc
when
(
mux
/=
MUX_SEL
)
else
...
...
@@ -283,6 +284,7 @@ begin
ep_snk_o
.
stall
<=
ep_snk_out_stall
;
ep_snk_o
.
rty
<=
'0'
;
end
behaviour
;
modules/wr_endpoint/endpoint_pkg.vhd
View file @
fe045ba6
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-04-26
-- Last update: 201
2-11-16
-- Last update: 201
7-02-03
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
...
...
@@ -14,7 +14,7 @@
-- structures and component declarations.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 - 201
2
CERN / BE-CO-HT
-- Copyright (c) 2011 - 201
7
CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
@@ -46,6 +46,7 @@ package endpoint_pkg is
function
f_pcs_data_width
(
pcs_16
:
boolean
)
return
integer
;
function
f_pcs_k_width
(
pcs_16
:
boolean
)
return
integer
;
function
f_pcs_bts_width
(
pcs_16
:
boolean
)
return
integer
;
function
f_pcs_clock_rate
(
pcs_16
:
boolean
)
return
integer
;
type
t_txtsu_timestamp
is
record
stb
:
std_logic
;
...
...
@@ -451,4 +452,14 @@ package body endpoint_pkg is
end
if
;
end
function
;
function
f_pcs_clock_rate
(
pcs_16
:
boolean
)
return
integer
is
begin
if
(
pcs_16
)
then
return
62500000
;
else
return
125000000
;
end
if
;
end
function
;
end
package
body
endpoint_pkg
;
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @
fe045ba6
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 201
3-03-15
-- Last update: 201
7-02-03
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -648,8 +648,7 @@ package endpoint_private_pkg is
full_o
:
out
std_logic
;
drop_req_i
:
in
std_logic
;
dropped_o
:
out
std_logic
;
regs_i
:
in
t_ep_out_registers
;
rmon_o
:
out
t_rmon_triggers
);
regs_i
:
in
t_ep_out_registers
);
end
component
;
...
...
@@ -770,10 +769,10 @@ package endpoint_private_pkg is
procedure
f_unpack_fifo_contents
(
signal
din
:
in
std_logic_vector
;
signal
din_valid
:
in
std_logic
;
signal
fab
:
out
t_ep_internal_fabric
;
early_eof
:
boolean
:
=
false
);
signal
din
:
in
std_logic_vector
;
constant
din_valid
:
in
std_logic
;
signal
fab
:
out
t_ep_internal_fabric
;
early_eof
:
boolean
:
=
false
);
procedure
f_pack_rmon_triggers
(
...
...
@@ -852,13 +851,14 @@ package body endpoint_private_pkg is
procedure
f_unpack_fifo_contents
(
signal
din
:
in
std_logic_vector
;
signal
din_valid
:
in
std_logic
;
signal
fab
:
out
t_ep_internal_fabric
;
early_eof
:
boolean
:
=
false
)
is
signal
din
:
in
std_logic_vector
;
constant
din_valid
:
in
std_logic
;
signal
fab
:
out
t_ep_internal_fabric
;
early_eof
:
boolean
:
=
false
)
is
begin
fab
.
data
<=
din
(
15
downto
0
);
fab
.
addr
<=
(
others
=>
'0'
);
if
(
din_valid
=
'1'
)
then
if
(
early_eof
)
then
fab
.
dvalid
<=
not
(
not
din
(
17
)
and
din
(
16
));
...
...
modules/wr_endpoint/ep_1000basex_pcs.vhd
View file @
fe045ba6
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2017-02-0
2
-- Last update: 2017-02-0
3
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -200,13 +200,12 @@ entity ep_1000basex_pcs is
dbg_tx_pcs_wr_count_o
:
out
std_logic_vector
(
5
+
4
downto
0
);
dbg_tx_pcs_rd_count_o
:
out
std_logic_vector
(
5
+
4
downto
0
);
nice_dbg_o
:
out
t_dbg_ep_pcs
);
nice_dbg_o
:
out
t_dbg_ep_pcs
);
end
ep_1000basex_pcs
;
architecture
rtl
of
ep_1000basex_pcs
is
signal
mdio_mcr_uni_en
:
std_logic
;
signal
mdio_mcr_anrestart
:
std_logic
;
signal
mdio_mcr_pdown
:
std_logic
;
signal
mdio_mcr_pdown_cpu
:
std_logic
;
...
...
@@ -227,6 +226,8 @@ architecture rtl of ep_1000basex_pcs is
signal
mdio_wr_spec_rx_cal_stat
:
std_logic
;
signal
mdio_wr_spec_cal_crst
:
std_logic
;
signal
mdio_wr_spec_bslide
:
std_logic_vector
(
4
downto
0
);
signal
mdio_data_in
:
std_logic_vector
(
31
downto
0
);
signal
mdio_data_out
:
std_logic_vector
(
31
downto
0
);
signal
lstat_read_notify
:
std_logic
;
...
...
@@ -251,8 +252,6 @@ architecture rtl of ep_1000basex_pcs is
signal
wb_stb
,
wb_ack
:
std_logic
;
signal
dummy
:
std_logic_vector
(
31
downto
0
);
signal
tx_clk
,
rx_clk
:
std_logic
;
--RMON events
...
...
@@ -403,6 +402,10 @@ begin -- rtl
mdio_wr_spec_bslide
<=
'0'
&
serdes_rx_bitslide_i
(
3
downto
0
);
dbg_tx_pcs_rd_count_o
<=
(
others
=>
'0'
);
dbg_tx_pcs_wr_count_o
<=
(
others
=>
'0'
);
nice_dbg_o
.
rx
.
fsm
<=
(
others
=>
'0'
);
end
generate
gen_8bit
;
txpcs_busy_o
<=
txpcs_busy_int
;
...
...
@@ -415,13 +418,11 @@ begin -- rtl
U_MDIO_WB
:
ep_pcs_tbi_mdio_wb
port
map
(
rst_n_i
=>
rst_n_i
,
clk_sys_i
=>
clk_sys_i
,
wb_adr_i
=>
mdio_addr_i
(
4
downto
0
),
wb_dat_i
(
15
downto
0
)
=>
mdio_data_i
,
wb_dat_i
(
31
downto
16
)
=>
x"0000"
,
wb_dat_o
(
15
downto
0
)
=>
mdio_data_o
,
wb_dat_o
(
31
downto
16
)
=>
dummy
(
31
downto
16
),
rst_n_i
=>
rst_n_i
,
clk_sys_i
=>
clk_sys_i
,
wb_adr_i
=>
mdio_addr_i
(
4
downto
0
),
wb_dat_i
=>
mdio_data_in
,
wb_dat_o
=>
mdio_data_out
,
wb_cyc_i
=>
wb_stb
,
wb_sel_i
=>
"1111"
,
...
...
@@ -432,7 +433,7 @@ begin -- rtl
tx_clk_i
=>
serdes_tx_clk_i
,
rx_clk_i
=>
serdes_rx_clk_i
,
mdio_mcr_uni_en_o
=>
mdio_mcr_uni_
en
,
mdio_mcr_uni_en_o
=>
op
en
,
mdio_mcr_anrestart_o
=>
mdio_mcr_anrestart
,
mdio_mcr_pdown_o
=>
mdio_mcr_pdown_cpu
,
mdio_mcr_anenable_o
=>
mdio_mcr_anenable
,
...
...
@@ -463,6 +464,9 @@ begin -- rtl
);
mdio_data_in
<=
X"0000"
&
mdio_data_i
;
mdio_data_o
<=
mdio_data_out
(
15
downto
0
);
mdio_msr_rfault
<=
'0'
;
U_AUTONEGOTIATION
:
ep_autonegotiation
...
...
@@ -582,4 +586,24 @@ begin -- rtl
npulse_o
=>
open
,
ppulse_o
=>
rmon_o
.
rx_sync_lost
);
-- drive unused outputs
rmon_o
.
rx_crc_err
<=
'0'
;
rmon_o
.
rx_ok
<=
'0'
;
rmon_o
.
rx_pfilter_drop
<=
'0'
;
rmon_o
.
rx_runt
<=
'0'
;
rmon_o
.
rx_giant
<=
'0'
;
rmon_o
.
rx_pause
<=
'0'
;
rmon_o
.
rx_pcs_err
<=
'0'
;
rmon_o
.
rx_buffer_overrun
<=
'0'
;
rmon_o
.
rx_rtu_overrun
<=
'0'
;
rmon_o
.
rx_path_timing_failure
<=
'0'
;
rmon_o
.
tx_pause
<=
'0'
;
rmon_o
.
rx_pclass
<=
(
others
=>
'0'
);
rmon_o
.
rx_tclass
<=
(
others
=>
'0'
);
rmon_o
.
tx_frame
<=
'0'
;
rmon_o
.
rx_frame
<=
'0'
;
rmon_o
.
rx_drop_at_rtu_full
<=
'0'
;
serdes_syncen_o
<=
'1'
;
serdes_enable_o
<=
'1'
;
end
rtl
;
modules/wr_endpoint/ep_rtu_header_extract.vhd
View file @
fe045ba6
...
...
@@ -145,24 +145,30 @@ begin -- rtl
end
generate
gen_with_rtu
;
gen_without_rtu
:
if
(
not
g_with_rtu
)
generate
src_fab_o
.
sof
<=
snk_fab_i
.
sof
;
rtu_rq_valid_out
<=
'0'
;
src_fab_o
.
sof
<=
snk_fab_i
.
sof
;
rtu_rq_valid_out
<=
'0'
;
rtu_rq_o
.
smac
<=
(
others
=>
'0'
);
rtu_rq_o
.
dmac
<=
(
others
=>
'0'
);
rtu_rq_abort_o
<=
'0'
;
rmon_drp_at_rtu_full_o
<=
'0'
;
end
generate
gen_without_rtu
;
snk_dreq_o
<=
src_dreq_i
;
src_fab_o
.
eof
<=
snk_fab_i
.
eof
;
src_fab_o
.
dvalid
<=
snk_fab_i
.
dvalid
;
src_fab_o
.
error
<=
snk_fab_i
.
error
;
src_fab_o
.
bytesel
<=
snk_fab_i
.
bytesel
;
src_fab_o
.
data
<=
snk_fab_i
.
data
;
src_fab_o
.
addr
<=
snk_fab_i
.
addr
;
src_fab_o
.
has_rx_timestamp
<=
snk_fab_i
.
has_rx_timestamp
;
rtu_rq_o
.
vid
<=
vlan_vid_i
;
rtu_rq_o
.
has_vid
<=
vlan_is_tagged_i
;
rtu_rq_o
.
prio
<=
vlan_class_i
;
rtu_rq_o
.
has_prio
<=
vlan_is_tagged_i
;
rtu_rq_valid_o
<=
rtu_rq_valid_out
and
not
snk_fab_i
.
error
;
src_fab_o
.
eof
<=
snk_fab_i
.
eof
;
src_fab_o
.
dvalid
<=
snk_fab_i
.
dvalid
;
src_fab_o
.
error
<=
snk_fab_i
.
error
;
src_fab_o
.
bytesel
<=
snk_fab_i
.
bytesel
;
src_fab_o
.
data
<=
snk_fab_i
.
data
;
src_fab_o
.
addr
<=
snk_fab_i
.
addr
;
src_fab_o
.
has_rx_timestamp
<=
snk_fab_i
.
has_rx_timestamp
;
src_fab_o
.
rx_timestamp_valid
<=
snk_fab_i
.
rx_timestamp_valid
;
rtu_rq_o
.
vid
<=
vlan_vid_i
;
rtu_rq_o
.
has_vid
<=
vlan_is_tagged_i
;
rtu_rq_o
.
prio
<=
vlan_class_i
;
rtu_rq_o
.
has_prio
<=
vlan_is_tagged_i
;
rtu_rq_valid_o
<=
rtu_rq_valid_out
and
not
snk_fab_i
.
ERROR
;
rtu_rq_o
.
hash
<=
(
others
=>
'0'
);
end
rtl
;
modules/wr_endpoint/ep_rx_buffer.vhd
View file @
fe045ba6
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 201
2-01-23
-- Last update: 201
7-02-02
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -64,8 +64,7 @@ entity ep_rx_buffer is
full_o
:
out
std_logic
;
drop_req_i
:
in
std_logic
;
dropped_o
:
out
std_logic
;
regs_i
:
in
t_ep_out_registers
;
rmon_o
:
out
t_rmon_triggers
regs_i
:
in
t_ep_out_registers
);
end
ep_rx_buffer
;
...
...
@@ -160,6 +159,8 @@ architecture behavioral of ep_rx_buffer is
fab
.
error
<=
'0'
;
fab
.
data
<=
(
others
=>
'0'
);
end
if
;
fab
.
has_rx_timestamp
<=
'0'
;
fab
.
rx_timestamp_valid
<=
'0'
;
end
f_unpack_rbuf_contents
;
...
...
@@ -232,7 +233,7 @@ begin
end
process
;
p_encode_fifo_in
:
process
(
snk_fab_i
,
state
,
q_drop
)
p_encode_fifo_in
:
process
(
drop_req_i
,
q_drop
,
snk_fab_i
,
state
)
variable
fab_pre_encode
:
t_ep_internal_fabric
;
begin
...
...
modules/wr_endpoint/ep_rx_crc_size_check.vhd
View file @
fe045ba6
...
...
@@ -82,7 +82,6 @@ architecture behavioral of ep_rx_crc_size_check is
signal
q_dvalid_in
:
std_logic
;
signal
q_dvalid_out
:
std_logic
;
signal
q_dreq_out
:
std_logic
;
signal
d_eof
:
std_logic
;
-- bypass_queue stuff comes here
constant
c_crc_size
:
integer
:
=
2
;
...
...
@@ -226,7 +225,6 @@ begin -- behavioral
q_purge
<=
'0'
;
q_bytesel
<=
'0'
;
d_eof
<=
'0'
;
state
<=
ST_WAIT_FRAME
;
...
...
@@ -248,7 +246,6 @@ begin -- behavioral
q_bytesel
<=
'0'
;
src_fab_o
.
error
<=
'0'
;
src_fab_o
.
sof
<=
'0'
;
d_eof
<=
'0'
;
if
(
snk_fab_i
.
sof
=
'1'
)
then
state
<=
ST_DATA
;
...
...
@@ -278,7 +275,6 @@ begin -- behavioral
src_fab_o
.
error
<=
'1'
;
q_purge
<=
'1'
;
elsif
(
snk_fab_i
.
eof
=
'1'
)
then
d_eof
<=
'1'
;
state
<=
ST_WAIT_FRAME
;
else
state
<=
ST_OOB
;
...
...
@@ -316,6 +312,8 @@ begin -- behavioral
src_fab_o
.
bytesel
<=
snk_fab_i
.
bytesel
when
(
dat_in
=
'1'
)
else
'0'
;
src_fab_o
.
eof
<=
snk_fab_i
.
eof
;
src_fab_o
.
has_rx_timestamp
<=
snk_fab_i
.
has_rx_timestamp
;
src_fab_o
.
rx_timestamp_valid
<=
snk_fab_i
.
rx_timestamp_valid
;
--------------------- the whole of bypass_queue is here ------------------------------------
-- it was put inside as the optimization made it far from "universal" and apparently this
...
...
modules/wr_endpoint/ep_rx_oob_insert.vhd
View file @
fe045ba6
...
...
@@ -32,27 +32,27 @@ architecture behavioral of ep_rx_oob_insert is
signal
src_dreq_d0
:
std_logic
;
component
chipscope_ila
port
(
CONTROL
:
inout
std_logic_vector
(
35
downto
0
);
CLK
:
in
std_logic
;
TRIG0
:
in
std_logic_vector
(
31
downto
0
);
TRIG1
:
in
std_logic_vector
(
31
downto
0
);
TRIG2
:
in
std_logic_vector
(
31
downto
0
);
TRIG3
:
in
std_logic_vector
(
31
downto
0
));
end
component
;
component
chipscope_icon
port
(
CONTROL0
:
inout
std_logic_vector
(
35
downto
0
));
end
component
;
--
component chipscope_ila
--
port (
--
CONTROL : inout std_logic_vector(35 downto 0);
--
CLK : in std_logic;
--
TRIG0 : in std_logic_vector(31 downto 0);
--
TRIG1 : in std_logic_vector(31 downto 0);
--
TRIG2 : in std_logic_vector(31 downto 0);
--
TRIG3 : in std_logic_vector(31 downto 0));
--
end component;
--
component chipscope_icon
--
port (
--
CONTROL0 : inout std_logic_vector (35 downto 0));
--
end component;
signal
CONTROL
:
std_logic_vector
(
35
downto
0
);
signal
CLK
:
std_logic
;
signal
TRIG0
:
std_logic_vector
(
31
downto
0
);
signal
TRIG1
:
std_logic_vector
(
31
downto
0
);
signal
TRIG2
:
std_logic_vector
(
31
downto
0
);
signal
TRIG3
:
std_logic_vector
(
31
downto
0
);
--
signal CONTROL : std_logic_vector(35 downto 0);
--
signal CLK : std_logic;
--
signal TRIG0 : std_logic_vector(31 downto 0);
--
signal TRIG1 : std_logic_vector(31 downto 0);
--
signal TRIG2 : std_logic_vector(31 downto 0);
--
signal TRIG3 : std_logic_vector(31 downto 0);
begin
--chipscope_ila_1 : chipscope_ila
...
...
@@ -68,22 +68,24 @@ begin
-- port map (
-- CONTROL0 => CONTROL);
TRIG0
(
15
downto
0
)
<=
snk_fab_i
.
data
;
trig0
(
16
)
<=
snk_fab_i
.
sof
;
trig0
(
17
)
<=
snk_fab_i
.
eof
;
trig0
(
18
)
<=
snk_fab_i
.
error
;
trig0
(
19
)
<=
snk_fab_i
.
bytesel
;
trig0
(
20
)
<=
snk_fab_i
.
has_rx_timestamp
;
trig0
(
21
)
<=
snk_fab_i
.
dvalid
;
trig0
(
22
)
<=
'1'
when
state
=
WAIT_OOB
else
'0'
;
trig0
(
24
downto
23
)
<=
snk_fab_i
.
addr
;
--TRIG0(15 downto 0) <= snk_fab_i.data;
--trig0(16) <= snk_fab_i.sof;
--trig0(17) <= snk_fab_i.eof;
--trig0(18) <= snk_fab_i.error;
--trig0(19) <= snk_fab_i.bytesel;
--trig0(20) <= snk_fab_i.has_rx_timestamp;
--trig0(21) <= snk_fab_i.dvalid;
--trig0(22) <= '1' when state = WAIT_OOB else '0';
--trig0(24 downto 23) <= snk_fab_i.addr;
snk_dreq_o
<=
src_dreq_i
;
src_fab_o
.
sof
<=
snk_fab_i
.
sof
;
src_fab_o
.
eof
<=
snk_fab_i
.
eof
;
src_fab_o
.
ERROR
<=
snk_fab_i
.
ERROR
;
src_fab_o
.
bytesel
<=
snk_fab_i
.
bytesel
;
src_fab_o
.
has_rx_timestamp
<=
snk_fab_i
.
has_rx_timestamp
;
src_fab_o
.
rx_timestamp_valid
<=
snk_fab_i
.
rx_timestamp_valid
;
snk_dreq_o
<=
src_dreq_i
;
src_fab_o
.
sof
<=
snk_fab_i
.
sof
;
src_fab_o
.
eof
<=
snk_fab_i
.
eof
;
src_fab_o
.
error
<=
snk_fab_i
.
error
;
src_fab_o
.
bytesel
<=
snk_fab_i
.
bytesel
;
p_comb_src
:
process
(
state
,
snk_fab_i
,
src_dreq_i
,
regs_i
)
begin
...
...
modules/wr_endpoint/ep_rx_path.vhd
View file @
fe045ba6
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 201
3-03-1
2
-- Last update: 201
7-02-0
2
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -365,6 +365,7 @@ begin -- behavioral
vlan_vid
<=
(
others
=>
'0'
);
vlan_tag_done
<=
'0'
;
vlan_is_tagged
<=
'0'
;
regs_o
<=
c_ep_in_registers_init_value
;
end
generate
gen_without_vlan_unit
;
U_RTU_Header_Extract
:
ep_rtu_header_extract
...
...
@@ -413,8 +414,7 @@ begin -- behavioral
-- stored in mbuf => mbuf is probably full so we
-- should drop this frame
dropped_o
=>
rxbuf_dropped
,
regs_i
=>
regs_i
,
rmon_o
=>
open
);
regs_i
=>
regs_i
);
end
generate
gen_with_rx_buffer
;
gen_without_rx_buffer
:
if
(
not
g_with_rx_buffer
)
generate
...
...
@@ -498,5 +498,18 @@ begin -- behavioral
rmon_o
.
rx_frame
<=
'1'
when
(
src_wb_out
.
cyc
=
'1'
and
src_wb_cyc_d0
=
'0'
)
else
'0'
;
-- drive unused signals and outputs
dreq_pipe
(
2
downto
0
)
<=
(
others
=>
'0'
);
rmon_o
.
rx_sync_lost
<=
'0'
;
rmon_o
.
rx_invalid_code
<=
'0'
;
rmon_o
.
rx_overrun
<=
'0'
;
rmon_o
.
rx_ok
<=
'0'
;
rmon_o
.
rx_buffer_overrun
<=
'0'
;
rmon_o
.
rx_rtu_overrun
<=
'0'
;
rmon_o
.
rx_path_timing_failure
<=
'0'
;
rmon_o
.
tx_pause
<=
'0'
;
rmon_o
.
tx_underrun
<=
'0'
;
rmon_o
.
tx_frame
<=
'0'
;
end
behavioral
;
modules/wr_endpoint/ep_rx_pcs_8bit.vhd
View file @
fe045ba6
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-16
-- Last update: 201
2-03-16
-- Last update: 201
7-02-02
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -346,6 +346,7 @@ begin
fifo_wrreq
<=
fifo_wr_toggle
and
fifo_mask_write
;
pcs_fab_o
.
data
<=
fifo_rx_data
;
pcs_fab_o
.
addr
<=
(
others
=>
'0'
);
pcs_fab_o
.
sof
<=
fifo_sof
and
fifo_wrreq
;
pcs_fab_o
.
eof
<=
fifo_eof
and
fifo_wrreq
;
pcs_fab_o
.
bytesel
<=
fifo_bytesel
;
...
...
modules/wr_endpoint/ep_rx_status_reg_insert.vhd
View file @
fe045ba6
...
...
@@ -53,6 +53,9 @@ begin -- rtl
src_fab_out
.
bytesel
<=
snk_fab_i
.
bytesel
;
src_fab_out
.
dvalid
<=
snk_fab_i
.
dvalid
or
(
embed_status
and
src_dreq_i
);
src_fab_out
.
has_rx_timestamp
<=
snk_fab_i
.
has_rx_timestamp
;
src_fab_out
.
rx_timestamp_valid
<=
snk_fab_i
.
rx_timestamp_valid
;
src_fab_o
<=
src_fab_out
;
src_fab_out
.
sof
<=
'1'
when
(
mbuf_valid_i
=
'1'
and
state
=
WAIT_MBUF
and
mbuf_drop_i
=
'0'
and
mbuf_is_pause_i
=
'0'
)
else
'0'
;
...
...
modules/wr_endpoint/ep_rx_wb_master.vhd
View file @
fe045ba6
...
...
@@ -6,14 +6,14 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 201
1-10-30
-- Last update: 201
7-02-02
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: RX Wishbone Master. Converts the internal fabric (DREQ-VALID
-- throttling) to Pipelined Wishbone (b4)
-------------------------------------------------------------------------------
-- Copyright (c) 2011
Tomasz Wlostowski
-- Copyright (c) 2011
-2017 CERN/
Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
@@ -60,7 +60,7 @@ architecture behavioral of ep_rx_wb_master is
signal
tmp_sel
:
std_logic
;
signal
tmp_dat
:
std_logic_vector
(
15
downto
0
);
signal
tmp_adr
:
std_logic_vector
(
1
downto
0
);
signal
enter_idle
:
std_logic
;
signal
enter_idle
:
std_logic
;
signal
sof_reg
:
std_logic
;
begin
-- behavioral
...
...
@@ -94,7 +94,7 @@ begin -- behavioral
end
process
;
process
(
clk_sys_i
)
variable
stat
:
t_wrf_status_reg
;
variable
stat
:
t_wrf_status_reg
:
=
c_wrf_status_init_value
;
begin
if
rising_edge
(
clk_sys_i
)
then
if
rst_n_i
=
'0'
then
...
...
@@ -130,7 +130,7 @@ begin -- behavioral
if
(
src_wb_i
.
err
=
'1'
)
then
state
<=
IDLE
;
enter_idle
<=
'1'
;
enter_idle
<=
'1'
;
src_out_int
.
cyc
<=
'0'
;
src_out_int
.
stb
<=
'0'
;
elsif
(
snk_fab_i
.
error
=
'1'
)
then
...
...
@@ -152,7 +152,7 @@ begin -- behavioral
when
FLUSH_STALL
=>
if
(
src_wb_i
.
err
=
'1'
)
then
state
<=
IDLE
;
enter_idle
<=
'1'
;
enter_idle
<=
'1'
;
src_out_int
.
cyc
<=
'0'
;
src_out_int
.
stb
<=
'0'
;
elsif
(
src_wb_i
.
stall
=
'0'
)
then
...
...
@@ -192,7 +192,7 @@ enter_idle <= '1';
if
(((
ack_count
=
0
)
or
g_ignore_ack
)
and
src_out_int
.
stb
=
'0'
)
then
src_out_int
.
cyc
<=
'0'
;
enter_idle
<=
'1'
;
enter_idle
<=
'1'
;
state
<=
IDLE
;
end
if
;
when
others
=>
null
;
...
...
modules/wr_endpoint/ep_timestamping_unit.vhd
View file @
fe045ba6
...
...
@@ -7,7 +7,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 201
3-03-15
-- Last update: 201
7-02-03
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
...
...
@@ -164,6 +164,9 @@ architecture syn of ep_timestamping_unit is
signal
cal_count
:
unsigned
(
5
downto
0
);
signal
rx_trigger_mask
,
rx_trigger_a
,
rx_cal_pulse_a
:
std_logic
;
signal
regs_o_tscr_cs_done
:
std_logic
;
signal
regs_o_tscr_rx_cal_result
:
std_logic
;
begin
-- syn
...
...
@@ -183,10 +186,21 @@ begin -- syn
value_r_o
=>
cntr_r
,
value_f_o
=>
cntr_f
,
sync_start_p_i
=>
regs_i
.
tscr_cs_start_o
,
sync_done_o
=>
regs_o
.
tscr_cs_done_i
sync_done_o
=>
regs_o
_tscr_cs_done
);
p_gen_regs_o
:
process
(
regs_o_tscr_cs_done
,
regs_o_tscr_rx_cal_result
)
is
begin
-- initial values
regs_o
<=
c_ep_in_registers_init_value
;
-- override initial values
regs_o
.
tscr_cs_done_i
<=
regs_o_tscr_cs_done
;
regs_o
.
tscr_rx_cal_result_i
<=
regs_o_tscr_rx_cal_result
;
end
process
p_gen_regs_o
;
p_rx_timestamper_calibration
:
process
(
clk_rx_i
)
begin
if
rising_edge
(
clk_rx_i
)
then
...
...
@@ -203,9 +217,9 @@ begin -- syn
if
(
rx_ts_done
=
'1'
)
then
if
(
cntr_rx_f
/=
cntr_rx_r
(
g_timestamp_bits_f
-1
downto
0
))
then
regs_o
.
tscr_rx_cal_result_i
<=
'1'
;
regs_o
_tscr_rx_cal_result
<=
'1'
;
else
regs_o
.
tscr_rx_cal_result_i
<=
'0'
;
regs_o
_tscr_rx_cal_result
<=
'0'
;
end
if
;
end
if
;
...
...
modules/wr_endpoint/ep_ts_counter.vhd
View file @
fe045ba6
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 201
1-05-27
-- Last update: 201
7-02-03
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
...
...
@@ -74,7 +74,6 @@ architecture syn of ep_ts_counter is
signal
cntr_r
:
unsigned
(
g_num_bits_r
-1
downto
0
)
:
=
(
others
=>
'0'
);
signal
cntr_f
:
unsigned
(
g_num_bits_f
-1
downto
0
);
signal
sync_in_progress
:
std_logic
;
begin
-- syn
...
...
@@ -85,7 +84,6 @@ begin -- syn
if
rising_edge
(
clk_i
)
then
if
(
rst_n_i
=
'0'
)
then
cntr_r
<=
to_unsigned
(
g_init_value
,
g_num_bits_r
);
sync_in_progress
<=
'0'
;
sync_done_o
<=
'1'
;
else
...
...
modules/wr_endpoint/ep_tx_crc_inserter.vhd
View file @
fe045ba6
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 201
2-11-15
-- Last update: 201
7-02-02
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -76,7 +76,7 @@ architecture behavioral of ep_tx_crc_inserter is
signal
odd_length
:
std_logic
;
signal
embed_valid
,
embed_eof
:
std_logic
;
signal
embed_valid
:
std_logic
;
signal
stored_msb
:
std_logic_vector
(
7
downto
0
);
signal
in_payload
:
std_logic
;
...
...
@@ -162,11 +162,9 @@ begin -- behavioral
if
rising_edge
(
clk_sys_i
)
then
if
(
rst_n_i
=
'0'
or
snk_fab_i
.
error
=
'1'
)
then
state
<=
IDLE
;
embed_eof
<=
'0'
;
else
case
state
is
when
IDLE
=>
embed_eof
<=
'0'
;
odd_length
<=
'0'
;
if
(
snk_fab_i
.
sof
=
'1'
)
then
...
...
@@ -194,14 +192,12 @@ begin -- behavioral
state
<=
EMBED_3
;
else
state
<=
IDLE
;
embed_eof
<=
'1'
;
end
if
;
end
if
;
when
EMBED_3
=>
if
(
src_dreq_d0
=
'1'
)
then
state
<=
IDLE
;
embed_eof
<=
'1'
;
end
if
;
end
case
;
end
if
;
...
...
@@ -261,10 +257,11 @@ begin -- behavioral
src_fab_o
.
addr
<=
c_WRF_DATA
;
end
process
;
snk_dreq_o
<=
src_dreq_i
and
in_payload
;
src_fab_o
.
sof
<=
snk_fab_i
.
sof
;
src_fab_o
.
error
<=
snk_fab_i
.
error
;
snk_dreq_o
<=
src_dreq_i
and
in_payload
;
src_fab_o
.
sof
<=
snk_fab_i
.
sof
;
src_fab_o
.
error
<=
snk_fab_i
.
error
;
src_fab_o
.
has_rx_timestamp
<=
snk_fab_i
.
has_rx_timestamp
;
src_fab_o
.
rx_timestamp_valid
<=
snk_fab_i
.
rx_timestamp_valid
;
end
behavioral
;
modules/wr_endpoint/ep_tx_header_processor.vhd
View file @
fe045ba6
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 201
2-11-16
-- Last update: 201
7-02-02
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -16,7 +16,7 @@
-- - decodes TX OOB data and passes it to the timestamping unit
-------------------------------------------------------------------------------
--
-- Copyright (c) 2009 - 201
2
CERN
-- Copyright (c) 2009 - 201
7
CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
@@ -149,7 +149,6 @@ architecture behavioral of ep_tx_header_processor is
-- Flow Control-related signals
signal
tx_pause_mode
:
std_logic
;
signal
tx_pause_delay
:
std_logic_vector
(
15
downto
0
);
signal
snk_valid
:
std_logic
;
...
...
@@ -346,11 +345,13 @@ begin -- behavioral
if
(
rst_n_i
=
'0'
)
then
state
<=
TXF_IDLE
;
src_fab_o
.
dvalid
<=
'0'
;
src_fab_o
.
error
<=
'0'
;
src_fab_o
.
sof
<=
'0'
;
src_fab_o
.
eof
<=
'0'
;
src_fab_o
.
bytesel
<=
'0'
;
src_fab_o
.
has_rx_timestamp
<=
'0'
;
src_fab_o
.
rx_timestamp_valid
<=
'0'
;
src_fab_o
.
dvalid
<=
'0'
;
src_fab_o
.
ERROR
<=
'0'
;
src_fab_o
.
sof
<=
'0'
;
src_fab_o
.
eof
<=
'0'
;
src_fab_o
.
bytesel
<=
'0'
;
wb_out
.
err
<=
'0'
;
wb_out
.
rty
<=
'0'
;
...
...
@@ -418,7 +419,6 @@ begin -- behavioral
fc_pause_ready_o
<=
'0'
;
tx_pause_mode
<=
fc_pause_req_i
;
tx_pause_delay
<=
fc_pause_delay_i
;
counter
<=
(
others
=>
'0'
);
...
...
modules/wr_endpoint/ep_tx_path.vhd
View file @
fe045ba6
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-11-01
-- Last update: 201
2-11-16
-- Last update: 201
7-02-03
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -162,7 +162,6 @@ architecture rtl of ep_tx_path is
signal
inject_mode
:
std_logic_vector
(
1
downto
0
);
signal
inj_ctr_req
:
std_logic
;
signal
inj_ctr_ready
:
std_logic
;
signal
inj_ctr_packet_sel
:
std_logic_vector
(
2
downto
0
);
signal
inj_ctr_user_value
:
std_logic_vector
(
15
downto
0
);
signal
inj_ctr_ena
:
std_logic
;
...
...
@@ -227,7 +226,7 @@ begin -- rtl
src_fab_o
=>
fab_pipe
(
1
),
src_dreq_i
=>
dreq_pipe
(
1
),
inject_req_o
=>
inj_ctr_req
,
inject_ready_i
=>
inj
_ctr
_ready
,
inject_ready_i
=>
inj
ect
_ready
,
inject_packet_sel_o
=>
inj_ctr_packet_sel
,
inject_user_value_o
=>
inj_ctr_user_value
,
inject_ctr_ena_o
=>
inj_ctr_ena
,
...
...
@@ -238,20 +237,17 @@ begin -- rtl
inject_req
<=
inj_ctr_req
when
(
inj_ctr_ena
=
'1'
)
else
inject_req_i
;
inject_packet_sel
<=
inj_ctr_packet_sel
when
(
inj_ctr_ena
=
'1'
)
else
inject_packet_sel_i
;
inject_user_value
<=
inj_ctr_user_value
when
(
inj_ctr_ena
=
'1'
)
else
inject_user_value_i
;
inject_mode
<=
inj_ctr_mode
when
(
inj_ctr_ena
=
'1'
)
else
"00"
;
inj_ctr_ready
<=
inject_ready
;
inject_ready_o
<=
inject_ready
;
gen_without_inj_ctrl
:
if
((
not
g_with_inj_ctrl
)
or
(
not
g_with_packet_injection
))
generate
fab_pipe
(
1
)
<=
fab_pipe
(
0
);
dreq_pipe
(
0
)
<=
dreq_pipe
(
1
);
inj_ctr_req
<=
'0'
;
inj_ctr_
ready
<=
'0'
;
inj_ctr_
mode
<=
(
others
=>
'0'
)
;
inj_ctr_packet_sel
<=
(
others
=>
'0'
);
inj_ctr_user_value
<=
(
others
=>
'0'
);
inj_ctr_ena
<=
'0'
;
regs_o
.
inj_ctrl_pic_ena_i
<=
'0'
;
regs_o
<=
c_ep_in_registers_init_value
;
end
generate
gen_without_inj_ctrl
;
gen_with_vlan_unit
:
if
(
g_with_vlans
)
generate
...
...
@@ -276,6 +272,10 @@ begin -- rtl
end
generate
gen_without_vlan_unit
;
gen_with_injection
:
if
(
g_with_packet_injection
)
generate
inject_user_value
<=
inj_ctr_user_value
when
(
inj_ctr_ena
=
'1'
)
else
inject_user_value_i
;
inject_mode
<=
inj_ctr_mode
when
(
inj_ctr_ena
=
'1'
)
else
"00"
;
U_Injector
:
ep_tx_packet_injection
port
map
(
clk_sys_i
=>
clk_sys_i
,
...
...
@@ -296,6 +296,7 @@ begin -- rtl
gen_without_injection
:
if
(
not
g_with_packet_injection
)
generate
fab_pipe
(
3
)
<=
fab_pipe
(
2
);
dreq_pipe
(
2
)
<=
dreq_pipe
(
3
);
inject_ready
<=
'0'
;
end
generate
gen_without_injection
;
U_Insert_CRC
:
ep_tx_crc_inserter
...
...
modules/wr_endpoint/ep_tx_pcs_16bit.vhd
View file @
fe045ba6
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT section
-- Created : 2009-06-16
-- Last update: 201
3-03-1
2
-- Last update: 201
7-02-0
2
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -149,7 +149,6 @@ architecture behavioral of ep_tx_pcs_16bit is
signal
reset_synced_txclk
:
std_logic
;
signal
mdio_mcr_pdown_synced
:
std_logic
;
signal
s_one
:
std_logic
:
=
'1'
;
signal
an_tx_en_synced
:
std_logic
;
signal
wr_count
:
std_logic_vector
(
6
downto
0
);
...
...
modules/wr_endpoint/ep_tx_pcs_8bit.vhd
View file @
fe045ba6
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT section
-- Created : 2009-06-16
-- Last update: 201
4-11-28
-- Last update: 201
7-02-03
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -157,8 +157,6 @@ architecture behavioral of ep_tx_pcs_8bit is
signal
mdio_mcr_pdown_synced
:
std_logic
;
signal
an_tx_en_synced
:
std_logic
;
signal
s_one
:
std_logic
:
=
'1'
;
begin
U_sync_pcs_busy_o
:
gc_sync_ffs
...
...
@@ -248,7 +246,7 @@ begin
fifo_enough_data
<=
not
fifo_almost_empty
;
f_unpack_fifo_contents
(
fifo_packed_out
,
s_one
,
fifo_fab
,
true
);
f_unpack_fifo_contents
(
fifo_packed_out
,
'1'
,
fifo_fab
,
true
);
-----------------------------------------------------------------------------
-- TX PCS state machine
...
...
modules/wr_endpoint/wr_endpoint.vhd
View file @
fe045ba6
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-04-26
-- Last update: 2017-02-0
2
-- Last update: 2017-02-0
3
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -105,16 +105,16 @@ entity wr_endpoint is
-- PHY Interace (8/16 bit PCS)
-------------------------------------------------------------------------------
phy_rst_o
:
out
std_logic
;
phy_rst_o
:
out
std_logic
;
phy_loopen_o
:
out
std_logic
;
phy_loopen_vec_o
:
out
std_logic_vector
(
2
downto
0
);
phy_tx_prbs_sel_o
:
out
std_logic_vector
(
2
downto
0
);
phy_sfp_tx_fault_i
:
in
std_logic
;
phy_sfp_los_i
:
in
std_logic
;
phy_sfp_tx_disable_o
:
out
std_logic
;
phy_enable_o
:
out
std_logic
;
phy_syncen_o
:
out
std_logic
;
phy_rdy_i
:
in
std_logic
;
phy_enable_o
:
out
std_logic
;
phy_syncen_o
:
out
std_logic
;
phy_rdy_i
:
in
std_logic
;
phy_ref_clk_i
:
in
std_logic
;
phy_tx_data_o
:
out
std_logic_vector
(
f_pcs_data_width
(
g_pcs_16bit
)
-1
downto
0
);
...
...
@@ -132,15 +132,15 @@ entity wr_endpoint is
-- GMII Interface (8-bit)
-------------------------------------------------------------------------------
gmii_tx_clk_i
:
in
std_logic
;
gmii_txd_o
:
out
std_logic_vector
(
7
downto
0
)
:
=
x"00"
;
gmii_tx_en_o
:
out
std_logic
:
=
'0'
;
gmii_tx_er_o
:
out
std_logic
:
=
'0'
;
gmii_tx_clk_i
:
in
std_logic
:
=
'0'
;
gmii_txd_o
:
out
std_logic_vector
(
7
downto
0
);
gmii_tx_en_o
:
out
std_logic
;
gmii_tx_er_o
:
out
std_logic
;
gmii_rx_clk_i
:
in
std_logic
;
gmii_rxd_i
:
in
std_logic_vector
(
7
downto
0
);
gmii_rx_er_i
:
in
std_logic
;
gmii_rx_dv_i
:
in
std_logic
;
gmii_rx_clk_i
:
in
std_logic
:
=
'0'
;
gmii_rxd_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
x"00"
;
gmii_rx_er_i
:
in
std_logic
:
=
'0'
;
gmii_rx_dv_i
:
in
std_logic
:
=
'0'
;
---------------------------------------------------------------------------
-- Wishbone I/O
...
...
@@ -308,15 +308,6 @@ architecture syn of wr_endpoint is
constant
c_zeros
:
std_logic_vector
(
63
downto
0
)
:
=
(
others
=>
'0'
);
constant
c_ones
:
std_logic_vector
(
63
downto
0
)
:
=
(
others
=>
'0'
);
function
f_pick_rate
(
pcs_16bit
:
boolean
)
return
integer
is
begin
if
(
pcs_16bit
)
then
return
62500000
;
else
return
125000000
;
end
if
;
end
f_pick_rate
;
-------------------------------------------------------------------------------
component
dmtd_phase_meas
generic
(
...
...
@@ -382,7 +373,7 @@ architecture syn of wr_endpoint is
signal
regs_towb_tsu
:
t_ep_in_registers
;
signal
regs_towb_rpath
:
t_ep_in_registers
;
signal
regs_towb_tpath
:
t_ep_in_registers
;
signal
regs_towb_dmtd
:
t_ep_in_registers
;
signal
regs_towb_dmtd
:
t_ep_in_registers
;
-------------------------------------------------------------------------------
-- flow control signals
...
...
@@ -398,8 +389,8 @@ architecture syn of wr_endpoint is
signal
link_ok
:
std_logic
;
signal
txfra_enable
,
rxfra_enable
:
std_logic
;
signal
mdio_addr
:
std_logic_vector
(
15
downto
0
);
signal
txfra_enable
:
std_logic
;
signal
mdio_addr
:
std_logic_vector
(
15
downto
0
);
signal
sink_in
:
t_wrf_sink_in
;
signal
sink_out
:
t_wrf_sink_out
;
...
...
@@ -619,7 +610,6 @@ begin
-------------------------------------------------------------------------------
-- RX deframer
-------------------------------------------------------------------------------
rxfra_enable
<=
link_ok
and
regs_fromwb
.
ecr_rx_en_o
;
U_Rx_Path
:
ep_rx_path
generic
map
(
...
...
@@ -678,6 +668,7 @@ begin
src_in
.
stall
<=
src_stall_i
;
src_in
.
ack
<=
src_ack_i
;
src_in
.
err
<=
src_err_i
;
src_in
.
rty
<=
'0'
;
-------------------------------------------------------------------------------
-- Flow control unit
...
...
@@ -715,7 +706,7 @@ begin
generic
map
(
g_timestamp_bits_r
=>
28
,
g_timestamp_bits_f
=>
4
,
g_ref_clock_rate
=>
f_p
i
ck_rate
(
g_pcs_16bit
))
g_ref_clock_rate
=>
f_p
cs_clo
ck_rate
(
g_pcs_16bit
))
port
map
(
clk_ref_i
=>
clk_ref_i
,
clk_rx_i
=>
phy_rx_clk_i
,
...
...
@@ -811,6 +802,23 @@ begin
end
if
;
end
process
;
-- drive unused regs_towb_ep signals
regs_towb_ep
.
ecr_feat_vlan_i
<=
'0'
;
regs_towb_ep
.
ecr_feat_dmtd_i
<=
'0'
;
regs_towb_ep
.
ecr_feat_ptp_i
<=
'0'
;
regs_towb_ep
.
ecr_feat_dpi_i
<=
'0'
;
regs_towb_ep
.
tscr_cs_done_i
<=
'0'
;
regs_towb_ep
.
tscr_rx_cal_result_i
<=
'0'
;
regs_towb_ep
.
tcar_pcp_map_i
<=
(
others
=>
'0'
);
regs_towb_ep
.
dsr_lstatus_i
<=
'0'
;
regs_towb_ep
.
dmcr_en_i
<=
'0'
;
regs_towb_ep
.
dmcr_n_avg_i
<=
(
others
=>
'0'
);
regs_towb_ep
.
inj_ctrl_pic_conf_ifg_i
<=
(
others
=>
'0'
);
regs_towb_ep
.
inj_ctrl_pic_conf_sel_i
<=
(
others
=>
'0'
);
regs_towb_ep
.
inj_ctrl_pic_conf_valid_i
<=
'0'
;
regs_towb_ep
.
inj_ctrl_pic_mode_id_i
<=
(
others
=>
'0'
);
regs_towb_ep
.
inj_ctrl_pic_mode_valid_i
<=
'0'
;
regs_towb_ep
.
inj_ctrl_pic_ena_i
<=
'0'
;
-------------------------------------------------------------------------------
-- DMTD phase meter
...
...
@@ -876,6 +884,7 @@ begin
gen_without_dmtd
:
if
(
not
g_with_dmtd
)
generate
regs_towb_ep
.
dmsr_ps_rdy_i
<=
'0'
;
regs_towb_ep
.
dmsr_ps_val_i
<=
(
others
=>
'X'
);
regs_towb_dmtd
<=
c_ep_in_registers_init_value
;
end
generate
gen_without_dmtd
;
dvalid_tx
<=
snk_cyc_i
and
snk_stb_i
and
link_ok
;
...
...
@@ -991,6 +1000,11 @@ begin
-- TRIG0( 18) <= phy_rx_enc_err_i;
-- TRIG0(23 downto 19) <= phy_rx_bitslide_i;
-- Drive unsued GMII outputs
gmii_txd_o
<=
(
others
=>
'0'
);
gmii_tx_en_o
<=
'0'
;
gmii_tx_er_o
<=
'0'
;
end
syn
;
modules/wr_endpoint/xwr_endpoint.vhd
View file @
fe045ba6
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-04-26
-- Last update: 201
2-11-16
-- Last update: 201
7-02-02
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
...
...
@@ -277,19 +277,19 @@ architecture syn of xwr_endpoint is
signal
phy_loopen_vec
:
std_logic_vector
(
2
downto
0
);
signal
phy_enable
:
std_logic
;
signal
phy_syncen
:
std_logic
;
signal
phy_tx_data
:
std_logic_vector
(
f_pcs_data_width
(
g_pcs_16bit
)
-1
downto
0
);
signal
phy_tx_k
:
std_logic_vector
(
f_pcs_k_width
(
g_pcs_16bit
)
-1
downto
0
);
signal
phy_tx_data
:
std_logic_vector
(
f_pcs_data_width
(
g_pcs_16bit
)
-1
downto
0
);
signal
phy_tx_k
:
std_logic_vector
(
f_pcs_k_width
(
g_pcs_16bit
)
-1
downto
0
);
signal
phy_tx_prbs_sel
:
std_logic_vector
(
2
downto
0
);
signal
sfp_tx_disable
:
std_logic
;
signal
phy_tx_clk
:
std_logic
;
signal
phy_tx_disparity
:
std_logic
;
signal
phy_tx_enc_err
:
std_logic
;
signal
phy_rx_data
:
std_logic_vector
(
f_pcs_data_width
(
g_pcs_16bit
)
-1
downto
0
);
signal
phy_rx_data
:
std_logic_vector
(
f_pcs_data_width
(
g_pcs_16bit
)
-1
downto
0
);
signal
phy_rx_clk
:
std_logic
;
signal
phy_rx_k
:
std_logic_vector
(
f_pcs_k_width
(
g_pcs_16bit
)
-1
downto
0
);
signal
phy_rx_k
:
std_logic_vector
(
f_pcs_k_width
(
g_pcs_16bit
)
-1
downto
0
);
signal
phy_rx_enc_err
:
std_logic
;
signal
phy_rx_bts
:
std_logic_vector
(
f_pcs_bts_width
(
g_pcs_16bit
)
-1
downto
0
);
signal
phy_rx_bts
:
std_logic_vector
(
f_pcs_bts_width
(
g_pcs_16bit
)
-1
downto
0
);
signal
phy_rdy
:
std_logic
;
signal
sfp_tx_fault
:
std_logic
;
signal
sfp_los
:
std_logic
;
...
...
@@ -501,6 +501,10 @@ begin
phy_rdy
<=
phy_rdy_i
;
sfp_tx_fault
<=
phy_sfp_tx_fault_i
;
sfp_los
<=
phy_sfp_los_i
;
-- drive unused ports with dummy values
phy8_o
<=
c_dummy_phy8_from_wrc
;
phy16_o
<=
c_dummy_phy16_from_wrc
;
end
generate
;
end
syn
;
...
...
modules/wr_mini_nic/wr_mini_nic.vhd
View file @
fe045ba6
...
...
@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk, Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-07-26
-- Last update: 201
6-10-27
-- Last update: 201
7-02-03
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -228,27 +228,27 @@ architecture behavioral of wr_mini_nic is
signal
irq_tx_mask
:
std_logic
;
component
chipscope_ila
port
(
CONTROL
:
inout
std_logic_vector
(
35
downto
0
);
CLK
:
in
std_logic
;
TRIG0
:
in
std_logic_vector
(
31
downto
0
);
TRIG1
:
in
std_logic_vector
(
31
downto
0
);
TRIG2
:
in
std_logic_vector
(
31
downto
0
);
TRIG3
:
in
std_logic_vector
(
31
downto
0
));
end
component
;
signal
CONTROL
:
std_logic_vector
(
35
downto
0
);
signal
CLK
:
std_logic
;
signal
TRIG0
:
std_logic_vector
(
31
downto
0
);
signal
TRIG1
:
std_logic_vector
(
31
downto
0
);
signal
TRIG2
:
std_logic_vector
(
31
downto
0
);
signal
TRIG3
:
std_logic_vector
(
31
downto
0
);
component
chipscope_icon
port
(
CONTROL0
:
inout
std_logic_vector
(
35
downto
0
));
end
component
;
--
component chipscope_ila
--
port (
--
CONTROL : inout std_logic_vector(35 downto 0);
--
CLK : in std_logic;
--
TRIG0 : in std_logic_vector(31 downto 0);
--
TRIG1 : in std_logic_vector(31 downto 0);
--
TRIG2 : in std_logic_vector(31 downto 0);
--
TRIG3 : in std_logic_vector(31 downto 0));
--
end component;
--
signal CONTROL : std_logic_vector(35 downto 0);
--
signal CLK : std_logic;
--
signal TRIG0 : std_logic_vector(31 downto 0);
--
signal TRIG1 : std_logic_vector(31 downto 0);
--
signal TRIG2 : std_logic_vector(31 downto 0);
--
signal TRIG3 : std_logic_vector(31 downto 0);
--
component chipscope_icon
--
port (
--
CONTROL0 : inout std_logic_vector (35 downto 0));
--
end component;
begin
-- behavioral
...
...
@@ -265,7 +265,9 @@ begin -- behavioral
-- port map (
-- CONTROL0 => CONTROL);
regs_in
.
mcr_ver_i
<=
x"1"
;
regs_in
.
mcr_ver_i
<=
x"1"
;
regs_in
.
dbgr_irq_cnt_i
<=
(
others
=>
'0'
);
regs_in
.
dbgr_wb_irq_val_i
<=
'0'
;
-------------------------------------------------------------------------------
-- Tx / Rx FIFO
...
...
@@ -763,31 +765,35 @@ begin -- behavioral
irq_rx_ack_o
=>
irq_rx_ack
,
irq_txts_i
=>
irq_txts
);
TRIG0
(
0
)
<=
regs_out
.
mcr_rx_en_o
;
TRIG0
(
1
)
<=
rx_fifo_empty
;
TRIG0
(
2
)
<=
rx_fifo_full
;
TRIG0
(
3
)
<=
rx_fifo_rd
;
TRIG0
(
4
)
<=
rx_fifo_we
;
TRIG0
(
6
downto
5
)
<=
rx_fifo_q
(
17
downto
16
);
TRIG0
(
22
downto
7
)
<=
rx_fifo_q
(
15
downto
0
);
TRIG0
(
24
downto
23
)
<=
"00"
when
(
nrx_state
=
RX_WAIT_FRAME
)
else
"01"
when
(
nrx_state
=
RX_FRAME
)
else
"10"
when
(
nrx_state
=
RX_FULL
)
else
"11"
;
TRIG0
(
25
)
<=
nrx_sof
;
TRIG0
(
26
)
<=
nrx_eof
;
TRIG0
(
27
)
<=
snk_cyc_i
;
TRIG0
(
28
)
<=
snk_stb_i
;
TRIG0
(
29
)
<=
snk_stall_int
;
TRIG0
(
31
downto
30
)
<=
snk_adr_i
;
TRIG1
(
15
downto
0
)
<=
snk_dat_i
;
TRIG1
(
16
)
<=
rx_fifo_afull
;
TRIG1
(
17
)
<=
wb_out
.
cyc
;
TRIG1
(
18
)
<=
wb_out
.
stb
;
TRIG1
(
19
)
<=
wb_in
.
ack
;
TRIG1
(
20
)
<=
irq_rx
;
TRIG2
(
31
downto
0
)
<=
wb_out
.
adr
;
wb_in
.
err
<=
'0'
;
wb_in
.
rty
<=
'0'
;
wb_in
.
int
<=
'0'
;
--TRIG0(0) <= regs_out.mcr_rx_en_o;
--TRIG0(1) <= rx_fifo_empty;
--TRIG0(2) <= rx_fifo_full;
--TRIG0(3) <= rx_fifo_rd;
--TRIG0(4) <= rx_fifo_we;
--TRIG0(6 downto 5) <= rx_fifo_q(17 downto 16);
--TRIG0(22 downto 7) <= rx_fifo_q(15 downto 0);
--TRIG0(24 downto 23) <= "00" when(nrx_state = RX_WAIT_FRAME) else
-- "01" when(nrx_state = RX_FRAME) else
-- "10" when(nrx_state = RX_FULL) else
-- "11";
--TRIG0(25) <= nrx_sof;
--TRIG0(26) <= nrx_eof;
--TRIG0(27) <= snk_cyc_i;
--TRIG0(28) <= snk_stb_i;
--TRIG0(29) <= snk_stall_int;
--TRIG0(31 downto 30) <= snk_adr_i;
--TRIG1(15 downto 0) <= snk_dat_i;
--TRIG1(16) <= rx_fifo_afull;
--TRIG1(17) <= wb_out.cyc;
--TRIG1(18) <= wb_out.stb;
--TRIG1(19) <= wb_in.ack;
--TRIG1(20) <= irq_rx;
--TRIG2(31 downto 0) <= wb_out.adr;
end
behavioral
;
modules/wr_mini_nic/xwr_mini_nic.vhd
View file @
fe045ba6
...
...
@@ -148,4 +148,6 @@ begin -- wrapper
wb_o
.
err
<=
'0'
;
wb_o
.
rty
<=
'0'
;
snk_o
.
rty
<=
'0'
;
end
wrapper
;
modules/wr_pps_gen/wr_pps_gen.vhd
View file @
fe045ba6
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-09-02
-- Last update: 201
4-07-15
-- Last update: 201
7-02-03
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -160,10 +160,8 @@ architecture behavioral of wr_pps_gen is
signal
rst_synced_refclk
:
std_logic
;
signal
adjust_in_progress_nsec
:
std_logic
;
signal
adjust_done_nsec
:
std_logic
;
signal
adjust_in_progress_utc
:
std_logic
;
signal
adjust_done_utc
:
std_logic
;
signal
width_cntr
:
unsigned
(
27
downto
0
);
...
...
@@ -305,7 +303,6 @@ begin -- behavioral
ns_overflow
<=
'0'
;
ns_overflow_adv
<=
'0'
;
adjust_in_progress_nsec
<=
'0'
;
adjust_done_nsec
<=
'1'
;
-- counter is enabled?
elsif
(
ppsg_cr_cnt_en
=
'1'
)
then
...
...
@@ -314,14 +311,12 @@ begin -- behavioral
if
(
cntr_adjust_p
=
'1'
)
then
-- start waiting for next counter overflow
adjust_done_nsec
<=
'0'
;
adjust_in_progress_nsec
<=
'1'
;
end
if
;
-- got SET TIME command - load the counter with new value
if
(
ppsg_cr_cnt_set_p
=
'1'
or
ext_sync_p
=
'1'
or
ppsg_escr_nsec_set
=
'1'
)
then
cntr_nsec
<=
adj_nsec
;
adjust_done_nsec
<=
'1'
;
ns_overflow
<=
'0'
;
ns_overflow_adv
<=
'0'
;
...
...
@@ -342,7 +337,6 @@ begin -- behavioral
-- but takes less logic.
if
(
adjust_in_progress_nsec
=
'1'
)
then
cntr_nsec
<=
adj_nsec
;
adjust_done_nsec
<=
'1'
;
-- assert done flag at the end
adjust_in_progress_nsec
<=
'0'
;
else
-- normal counter reset. Generate overflow pulse.
...
...
@@ -386,16 +380,13 @@ begin -- behavioral
if
rising_edge
(
clk_ref_i
)
then
if
rst_synced_refclk
=
'0'
or
ppsg_cr_cnt_rst
=
'1'
then
cntr_utc
<=
(
others
=>
'0'
);
adjust_done_utc
<=
'1'
;
adjust_in_progress_utc
<=
'0'
;
elsif
(
ppsg_cr_cnt_en
=
'1'
)
then
if
(
ppsg_cr_cnt_set_p
=
'1'
or
ppsg_escr_sec_set
=
'1'
)
then
cntr_utc
<=
adj_utc
;
adjust_done_utc
<=
'1'
;
elsif
(
cntr_adjust_p
=
'1'
)
then
adjust_in_progress_utc
<=
'1'
;
adjust_done_utc
<=
'0'
;
if
(
ns_overflow
=
'1'
)
then
cntr_utc
<=
cntr_utc
+
1
;
...
...
@@ -403,7 +394,6 @@ begin -- behavioral
elsif
(
adjust_in_progress_utc
=
'1'
and
ns_overflow
=
'1'
)
then
cntr_utc
<=
cntr_utc
+
adj_utc
+
1
;
adjust_done_utc
<=
'1'
;
adjust_in_progress_utc
<=
'0'
;
elsif
(
ns_overflow
=
'1'
)
then
cntr_utc
<=
cntr_utc
+
1
;
...
...
@@ -491,6 +481,12 @@ begin -- behavioral
ppsg_escr_sec_set_o
=>
ppsg_escr_sec_set
,
ppsg_escr_nsec_set_o
=>
ppsg_escr_nsec_set
);
-- drive unused signals
wb_out
.
rty
<=
'0'
;
wb_out
.
stall
<=
'0'
;
wb_out
.
int
<=
'0'
;
wb_out
.
err
<=
'0'
;
-- start the adjustment upon write of 1 to CNT_ADJ bit
cntr_adjust_p
<=
ppsg_cr_cnt_adj_load
and
ppsg_cr_cnt_adj_o
;
...
...
modules/wr_softpll_ng/spll_aligner.vhd
View file @
fe045ba6
...
...
@@ -23,7 +23,6 @@ entity spll_aligner is
sample_cref_o
:
out
std_logic_vector
(
g_counter_width
-1
downto
0
);
sample_cin_o
:
out
std_logic_vector
(
g_counter_width
-1
downto
0
);
sample_pps_o
:
out
std_logic
;
sample_valid_o
:
out
std_logic
;
sample_ack_i
:
in
std_logic
);
...
...
modules/wr_softpll_ng/wr_softpll_ng.vhd
View file @
fe045ba6
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-29
-- Last update: 201
4-07-15
-- Last update: 201
7-02-03
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -18,7 +18,7 @@
-- The rest of the magic is done in the software.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012-201
3
CERN
-- Copyright (c) 2012-201
7
CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
@@ -137,8 +137,6 @@ entity wr_softpll_ng is
-- When HI, the respective clock output is locked.
out_locked_o
:
out
std_logic_vector
(
g_num_outputs
-1
downto
0
);
out_status_o
:
out
std_logic_vector
(
4
*
g_num_outputs
-1
downto
0
);
wb_adr_i
:
in
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
...
...
@@ -227,7 +225,6 @@ architecture rtl of wr_softpll_ng is
pps_csync_p1_i
:
in
std_logic
;
sample_cref_o
:
out
std_logic_vector
(
g_counter_width
-1
downto
0
);
sample_cin_o
:
out
std_logic_vector
(
g_counter_width
-1
downto
0
);
sample_pps_o
:
out
std_logic
;
sample_valid_o
:
out
std_logic
;
sample_ack_i
:
in
std_logic
);
end
component
;
...
...
@@ -303,6 +300,7 @@ architecture rtl of wr_softpll_ng is
signal
dbg_fifo_almostfull
:
std_logic
;
signal
dbg_seq_id
:
unsigned
(
15
downto
0
);
signal
dbg_fifo_permit_write
:
std_logic
;
signal
dbg_fifo_irq
:
std_logic
:
=
'0'
;
-- Temporary vectors for DDMTD clock selection (straight/reversed)
signal
dmtd_ref_clk_in
,
dmtd_ref_clk_dmtd
:
std_logic_vector
(
g_num_ref_inputs
-1
downto
0
);
...
...
@@ -473,11 +471,14 @@ begin -- rtl
end
generate
gen_feedback_dmtds
;
-- drive unused debug output
debug_o
(
4
)
<=
'0'
;
gen_with_ext_clock_input
:
if
(
g_with_ext_clock_input
)
generate
debug_o
(
0
)
<=
fb_resync_out
(
0
);
debug_o
(
1
)
<=
tags_p
(
g_num_ref_inputs
+
g_num_outputs
);
debug_o
(
2
)
<=
tags_p
(
g_num_ref_inputs
);
debug_o
(
0
)
<=
fb_resync_out
(
0
);
debug_o
(
1
)
<=
tags_p
(
g_num_ref_inputs
+
g_num_outputs
);
debug_o
(
2
)
<=
tags_p
(
g_num_ref_inputs
);
U_DMTD_EXT
:
dmtd_with_deglitcher
generic
map
(
...
...
@@ -505,7 +506,7 @@ begin -- rtl
deglitch_threshold_i
=>
deglitch_thr_slv
,
dbg_dmtdout_o
=>
debug_o
(
3
),
dbg_clk_d3_o
=>
debug_o
(
5
));
dbg_clk_d3_o
=>
debug_o
(
5
));
U_Aligner_EXT
:
spll_aligner
generic
map
(
...
...
@@ -526,23 +527,38 @@ begin -- rtl
sample_ack_i
=>
aligner_sample_ack
(
g_num_outputs
)
);
aligner_sample_valid
(
g_num_outputs
-1
downto
0
)
<=
(
others
=>
'0'
);
aligner_sample_cref
(
0
to
g_num_outputs
-1
)
<=
(
others
=>
(
others
=>
'0'
));
aligner_sample_cin
(
0
to
g_num_outputs
-1
)
<=
(
others
=>
(
others
=>
'0'
));
regs_out
.
eccr_ext_supported_i
<=
'1'
;
regs_out
.
eccr_ext_ref_locked_i
<=
clk_ext_mul_locked_i
;
regs_out
.
eccr_ext_ref_stopped_i
<=
clk_ext_stopped_i
;
clk_ext_rst_o
<=
regs_in
.
eccr_ext_ref_pllrst_o
;
end
generate
gen_with_ext_clock_input
;
aligner_sample_valid
(
g_num_outputs
-1
downto
0
)
<=
(
others
=>
'0'
);
gen_without_ext_clock_input
:
if
(
not
g_with_ext_clock_input
)
generate
aligner_sample_valid
<=
(
others
=>
'0'
);
aligner_sample_cref
<=
(
others
=>
(
others
=>
'0'
));
aligner_sample_cin
<=
(
others
=>
(
others
=>
'0'
));
regs_out
.
eccr_ext_supported_i
<=
'0'
;
regs_out
.
eccr_ext_ref_locked_i
<=
'0'
;
regs_out
.
eccr_ext_ref_stopped_i
<=
'0'
;
clk_ext_rst_o
<=
'0'
;
-- drive unused debug outputs
debug_o
(
0
)
<=
'0'
;
debug_o
(
1
)
<=
'0'
;
debug_o
(
2
)
<=
'0'
;
debug_o
(
3
)
<=
'0'
;
debug_o
(
5
)
<=
'0'
;
end
generate
gen_without_ext_clock_input
;
p_ack_aligner_samples
:
process
(
regs_in
,
aligner_sample_valid
)
begin
regs_out
.
al_cr_valid_i
<=
(
others
=>
'0'
);
for
i
in
0
to
g_num_outputs
loop
aligner_sample_ack
(
i
)
<=
regs_in
.
al_cr_valid_o
(
i
)
and
regs_in
.
al_cr_valid_load_o
;
regs_out
.
al_cr_valid_i
(
i
)
<=
aligner_sample_valid
(
i
);
...
...
@@ -584,6 +600,12 @@ begin -- rtl
irq_tag_i
=>
irq_tag
);
-- drive unused outputs
wb_out
.
err
<=
'0'
;
wb_out
.
rty
<=
'0'
;
wb_out
.
stall
<=
'0'
;
wb_out
.
int
<=
'0'
;
p_ocer_rcer_regs
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
...
...
@@ -602,9 +624,11 @@ begin -- rtl
end
if
;
end
process
;
-- Drive back the respective registers
regs_out
.
ocer_i
(
g_num_outputs
-1
downto
0
)
<=
ocer_int
;
regs_out
.
ocer_i
(
g_num_outputs
-1
downto
0
)
<=
ocer_int
;
regs_out
.
ocer_i
(
7
downto
g_num_outputs
)
<=
(
others
=>
'0'
);
regs_out
.
rcer_i
(
g_num_ref_inputs
-1
downto
0
)
<=
rcer_int
;
regs_out
.
rcer_i
(
31
downto
g_num_ref_inputs
)
<=
(
others
=>
'0'
);
p_latch_tags
:
process
(
clk_sys_i
)
begin
...
...
@@ -687,10 +711,12 @@ begin -- rtl
end
if
;
end
process
;
regs_out
.
trr_wr_req_i
<=
tag_valid
and
not
regs_in
.
trr_wr_full_o
;
regs_out
.
trr_value_i
(
g_tag_bits
-1
downto
0
)
<=
tag_muxed
;
regs_out
.
trr_chan_id_i
<=
'0'
&
tag_src
;
regs_out
.
trr_wr_req_i
<=
tag_valid
and
not
regs_in
.
trr_wr_full_o
;
regs_out
.
trr_chan_id_i
<=
'0'
&
tag_src
;
regs_out
.
trr_value_i
(
g_tag_bits
-1
downto
0
)
<=
tag_muxed
;
regs_out
.
trr_value_i
(
23
downto
g_tag_bits
)
<=
(
others
=>
'0'
);
regs_out
.
occr_out_en_i
(
g_num_outputs
-1
downto
0
)
<=
out_enable_i
;
regs_out
.
occr_out_en_i
(
7
downto
g_num_outputs
)
<=
(
others
=>
'0'
);
...
...
@@ -742,12 +768,12 @@ begin -- rtl
begin
if
rising_edge
(
clk_sys_i
)
then
if
rst_n_i
=
'0'
then
dbg_fifo_irq
_o
<=
'0'
;
dbg_fifo_irq
<=
'0'
;
else
if
(
unsigned
(
regs_in
.
dfr_host_wr_usedw_o
)
=
0
)
then
dbg_fifo_irq
_o
<=
'0'
;
dbg_fifo_irq
<=
'0'
;
elsif
(
unsigned
(
regs_in
.
dfr_host_wr_usedw_o
)
=
c_DBG_FIFO_COALESCE
)
then
dbg_fifo_irq
_o
<=
'1'
;
dbg_fifo_irq
<=
'1'
;
end
if
;
end
if
;
end
if
;
...
...
@@ -760,9 +786,14 @@ begin -- rtl
end
generate
gen_with_debug_fifo
;
gen_without_debug_fifo
:
if
(
g_with_debug_fifo
=
false
)
generate
dbg_fifo_irq
<=
'0'
;
regs_out
.
dfr_host_wr_req_i
<=
'0'
;
regs_out
.
dfr_host_value_i
<=
(
others
=>
'0'
);
regs_out
.
dfr_host_seq_id_i
<=
(
others
=>
'0'
);
end
generate
gen_without_debug_fifo
;
dbg_fifo_irq_o
<=
dbg_fifo_irq
;
-----------------------------------------------------------------------------
-- CSR N_OUT/N_REF fields
-----------------------------------------------------------------------------
...
...
@@ -779,5 +810,11 @@ begin -- rtl
wb_irq_o
<=
wb_irq_out
;
regs_out
.
al_cr_required_i
<=
(
others
=>
'0'
);
regs_out
.
csr_dbg_supported_i
<=
'0'
;
regs_out
.
f_dmtd_valid_i
<=
'0'
;
regs_out
.
f_ref_valid_i
<=
'0'
;
regs_out
.
f_ext_valid_i
<=
'0'
;
regs_out
.
trr_disc_i
<=
'0'
;
end
rtl
;
modules/wr_softpll_ng/xwr_softpll_ng.vhd
View file @
fe045ba6
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-29
-- Last update: 201
4-07-15
-- Last update: 201
7-02-02
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -122,7 +122,6 @@ entity xwr_softpll_ng is
out_enable_i
:
in
std_logic_vector
(
g_num_outputs
-1
downto
0
);
out_locked_o
:
out
std_logic_vector
(
g_num_outputs
-1
downto
0
);
out_status_o
:
out
std_logic_vector
(
4
*
g_num_outputs
-1
downto
0
);
slave_i
:
in
t_wishbone_slave_in
;
slave_o
:
out
t_wishbone_slave_out
;
...
...
@@ -167,7 +166,6 @@ architecture wrapper of xwr_softpll_ng is
dac_out_load_o
:
out
std_logic
;
out_enable_i
:
in
std_logic_vector
(
g_num_outputs
-1
downto
0
);
out_locked_o
:
out
std_logic_vector
(
g_num_outputs
-1
downto
0
);
out_status_o
:
out
std_logic_vector
(
4
*
g_num_outputs
-1
downto
0
);
wb_adr_i
:
in
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
...
...
modules/wrc_core/wr_core.vhd
View file @
fe045ba6
...
...
@@ -5,7 +5,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-02
-- Last update: 201
4-07-15
-- Last update: 201
7-02-03
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -70,6 +70,7 @@ use ieee.numeric_std.all;
library
work
;
use
work
.
wrcore_pkg
.
all
;
use
work
.
gencores_pkg
.
all
;
use
work
.
genram_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
endpoint_pkg
.
all
;
...
...
@@ -294,7 +295,6 @@ entity wr_core is
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
dio_o
:
out
std_logic_vector
(
3
downto
0
);
rst_aux_n_o
:
out
std_logic
;
link_ok_o
:
out
std_logic
;
...
...
@@ -309,15 +309,6 @@ end wr_core;
architecture
struct
of
wr_core
is
function
f_int_to_bool
(
x
:
integer
)
return
boolean
is
begin
if
(
x
/=
0
)
then
return
true
;
else
return
false
;
end
if
;
end
f_int_to_bool
;
function
f_choose_lm32_firmware_file
return
string
is
begin
if
(
g_dpram_initf
=
"default"
)
then
...
...
@@ -372,9 +363,14 @@ architecture struct of wr_core is
signal
ep_txtsu_stb
,
ep_txtsu_ack
:
std_logic
;
signal
ep_led_link
:
std_logic
;
constant
c_mnic_memsize_log2
:
integer
:
=
f_log2_size
(
g_dpram_size
);
-----------------------------------------------------------------------------
--Mini-NIC
-----------------------------------------------------------------------------
signal
mnic_mem_data_o
:
std_logic_vector
(
31
downto
0
);
signal
mnic_mem_addr_o
:
std_logic_vector
(
c_mnic_memsize_log2
-1
downto
0
);
signal
mnic_mem_wr_o
:
std_logic
;
signal
mnic_txtsu_ack
:
std_logic
;
signal
mnic_txtsu_stb
:
std_logic
;
...
...
@@ -382,7 +378,6 @@ architecture struct of wr_core is
--Dual-port RAM
-----------------------------------------------------------------------------
signal
dpram_wbb_i
:
t_wishbone_slave_in
;
signal
dpram_wbb_o
:
t_wishbone_slave_out
;
-----------------------------------------------------------------------------
--WB Peripherials
...
...
@@ -395,32 +390,36 @@ architecture struct of wr_core is
-----------------------------------------------------------------------------
--WB Secondary Crossbar
-----------------------------------------------------------------------------
constant
c_secbar_layout
:
t_sdb_record_array
(
8
downto
0
)
:
=
(
0
=>
f_sdb_embed_device
(
f_xwb_dpram
(
g_dpram_size
),
x"00000000"
),
1
=>
f_sdb_embed_device
(
c_xwr_mini_nic_sdb
,
x"00020000"
),
2
=>
f_sdb_embed_device
(
c_xwr_endpoint_sdb
,
x"00020100"
),
3
=>
f_sdb_embed_device
(
c_xwr_softpll_ng_sdb
,
x"00020200"
),
4
=>
f_sdb_embed_device
(
c_xwr_pps_gen_sdb
,
x"00020300"
),
5
=>
f_sdb_embed_device
(
c_wrc_periph0_sdb
,
x"00020400"
),
-- Syscon
6
=>
f_sdb_embed_device
(
c_wrc_periph1_sdb
,
x"00020500"
),
-- UART
7
=>
f_sdb_embed_device
(
c_wrc_periph2_sdb
,
x"00020600"
),
-- 1-Wire
8
=>
f_sdb_embed_device
(
g_aux_sdb
,
x"00020700"
)
-- aux WB bus
constant
c_secbar_layout
:
t_sdb_record_array
(
7
downto
0
)
:
=
(
0
=>
f_sdb_embed_device
(
c_xwr_mini_nic_sdb
,
x"00000000"
),
1
=>
f_sdb_embed_device
(
c_xwr_endpoint_sdb
,
x"00000100"
),
2
=>
f_sdb_embed_device
(
c_xwr_softpll_ng_sdb
,
x"00000200"
),
3
=>
f_sdb_embed_device
(
c_xwr_pps_gen_sdb
,
x"00000300"
),
4
=>
f_sdb_embed_device
(
c_wrc_periph0_sdb
,
x"00000400"
),
-- Syscon
5
=>
f_sdb_embed_device
(
c_wrc_periph1_sdb
,
x"00000500"
),
-- UART
6
=>
f_sdb_embed_device
(
c_wrc_periph2_sdb
,
x"00000600"
),
-- 1-Wire
7
=>
f_sdb_embed_device
(
g_aux_sdb
,
x"00000700"
)
-- aux WB bus
);
constant
c_secbar_sdb_address
:
t_wishbone_address
:
=
x"000
300
00"
;
constant
c_secbar_sdb_address
:
t_wishbone_address
:
=
x"000
008
00"
;
constant
c_secbar_bridge_sdb
:
t_sdb_bridge
:
=
f_xwb_bridge_layout_sdb
(
true
,
c_secbar_layout
,
c_secbar_sdb_address
);
signal
secbar_master_i
:
t_wishbone_master_in_array
(
8
downto
0
);
signal
secbar_master_o
:
t_wishbone_master_out_array
(
8
downto
0
);
signal
secbar_master_i
:
t_wishbone_master_in_array
(
7
downto
0
);
signal
secbar_master_o
:
t_wishbone_master_out_array
(
7
downto
0
);
-----------------------------------------------------------------------------
--WB intercon
-----------------------------------------------------------------------------
signal
cbar_slave_i
:
t_wishbone_slave_in_array
(
1
downto
0
);
signal
cbar_slave_o
:
t_wishbone_slave_out_array
(
1
downto
0
);
signal
cbar_master_i
:
t_wishbone_master_in_array
(
0
downto
0
);
signal
cbar_master_o
:
t_wishbone_master_out_array
(
0
downto
0
);
constant
c_layout
:
t_sdb_record_array
(
1
downto
0
)
:
=
(
0
=>
f_sdb_embed_device
(
f_xwb_dpram
(
g_dpram_size
),
x"00000000"
),
1
=>
f_sdb_embed_bridge
(
c_secbar_bridge_sdb
,
x"00020000"
));
constant
c_sdb_address
:
t_wishbone_address
:
=
x"00030000"
;
signal
cbar_slave_i
:
t_wishbone_slave_in_array
(
2
downto
0
);
signal
cbar_slave_o
:
t_wishbone_slave_out_array
(
2
downto
0
);
signal
cbar_master_i
:
t_wishbone_master_in_array
(
1
downto
0
);
signal
cbar_master_o
:
t_wishbone_master_out_array
(
1
downto
0
);
-----------------------------------------------------------------------------
--External WB interface
...
...
@@ -634,7 +633,7 @@ begin
generic
map
(
g_interface_mode
=>
PIPELINED
,
g_address_granularity
=>
BYTE
,
g_simulation
=>
f_int
_to_
bool
(
g_simulation
),
g_simulation
=>
f_int
2
bool
(
g_simulation
),
g_tx_runt_padding
=>
g_tx_runt_padding
,
g_pcs_16bit
=>
g_pcs_16bit
,
g_records_for_phy
=>
g_records_for_phy
,
...
...
@@ -751,8 +750,9 @@ begin
dwb_o
=>
cbar_slave_i
(
0
),
dwb_i
=>
cbar_slave_o
(
0
),
iwb_o
=>
dpram_wbb_i
,
iwb_i
=>
dpram_wbb_o
);
iwb_o
=>
cbar_slave_i
(
1
),
iwb_i
=>
cbar_slave_o
(
1
)
);
-----------------------------------------------------------------------------
-- Dual-port RAM
...
...
@@ -765,15 +765,23 @@ begin
g_slave1_interface_mode
=>
PIPELINED
,
g_slave2_interface_mode
=>
PIPELINED
,
g_slave1_granularity
=>
BYTE
,
g_slave2_granularity
=>
BYTE
)
g_slave2_granularity
=>
WORD
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
slave1_i
=>
se
cbar_master_o
(
0
),
slave1_o
=>
se
cbar_master_i
(
0
),
slave1_i
=>
cbar_master_o
(
0
),
slave1_o
=>
cbar_master_i
(
0
),
slave2_i
=>
dpram_wbb_i
,
slave2_o
=>
dpram_wbb_o
);
slave2_o
=>
open
);
dpram_wbb_i
.
cyc
<=
'0'
;
dpram_wbb_i
.
stb
<=
'0'
;
dpram_wbb_i
.
adr
<=
(
c_mnic_memsize_log2
-1
downto
0
=>
'0'
,
others
=>
'0'
);
--mnic_mem_addr_o;
dpram_wbb_i
.
sel
<=
"1111"
;
dpram_wbb_i
.
we
<=
'0'
;
--mnic_mem_wr_o;
dpram_wbb_i
.
dat
<=
(
others
=>
'0'
);
--mnic_mem_data_o;
-----------------------------------------------------------------------------
-- WB Peripherials
...
...
@@ -855,13 +863,15 @@ begin
-----------------------------------------------------------------------------
-- WB intercon
-----------------------------------------------------------------------------
WB_CON
:
xwb_crossbar
WB_CON
:
xwb_
sdb_
crossbar
generic
map
(
g_num_masters
=>
2
,
g_num_slaves
=>
1
,
g_num_masters
=>
3
,
g_num_slaves
=>
2
,
g_registered
=>
true
,
g_address
=>
(
0
=>
x"00000000"
),
g_mask
=>
(
0
=>
x"00000000"
))
g_wraparound
=>
true
,
g_layout
=>
c_layout
,
g_sdb_addr
=>
c_sdb_address
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
...
...
@@ -873,8 +883,8 @@ begin
master_o
=>
cbar_master_o
);
cbar_slave_i
(
1
)
<=
ext_wb_in
;
ext_wb_out
<=
cbar_slave_o
(
1
);
cbar_slave_i
(
2
)
<=
ext_wb_in
;
ext_wb_out
<=
cbar_slave_o
(
2
);
--chipscope_ila_1 : chipscope_ila
-- port map (
...
...
@@ -924,7 +934,7 @@ begin
WB_SECONDARY_CON
:
xwb_sdb_crossbar
generic
map
(
g_num_masters
=>
1
,
g_num_slaves
=>
9
,
g_num_slaves
=>
8
,
g_registered
=>
true
,
g_wraparound
=>
true
,
g_layout
=>
c_secbar_layout
,
...
...
@@ -934,42 +944,61 @@ begin
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
-- Master connections (INTERCON is a slave)
slave_i
(
0
)
=>
cbar_master_o
(
0
),
slave_o
(
0
)
=>
cbar_master_i
(
0
),
slave_i
(
0
)
=>
cbar_master_o
(
1
),
slave_o
(
0
)
=>
cbar_master_i
(
1
),
-- Slave connections (INTERCON is a master)
master_i
=>
secbar_master_i
,
master_o
=>
secbar_master_o
);
secbar_master_i
(
1
)
<=
minic_wb_out
;
minic_wb_in
<=
secbar_master_o
(
1
);
secbar_master_i
(
2
)
<=
ep_wb_out
;
ep_wb_in
<=
secbar_master_o
(
2
);
secbar_master_i
(
3
)
<=
spll_wb_out
;
spll_wb_in
<=
secbar_master_o
(
3
);
secbar_master_i
(
4
)
<=
ppsg_wb_out
;
ppsg_wb_in
<=
secbar_master_o
(
4
);
secbar_master_i
(
0
)
<=
minic_wb_out
;
minic_wb_in
<=
secbar_master_o
(
0
);
secbar_master_i
(
1
)
<=
ep_wb_out
;
ep_wb_in
<=
secbar_master_o
(
1
);
secbar_master_i
(
2
)
<=
spll_wb_out
;
spll_wb_in
<=
secbar_master_o
(
2
);
secbar_master_i
(
3
)
<=
ppsg_wb_out
;
ppsg_wb_in
<=
secbar_master_o
(
3
);
--peripherials
secbar_master_i
(
5
)
<=
periph_slave_o
(
0
);
secbar_master_i
(
6
)
<=
periph_slave_o
(
1
);
secbar_master_i
(
7
)
<=
periph_slave_o
(
2
);
periph_slave_i
(
0
)
<=
secbar_master_o
(
5
);
periph_slave_i
(
1
)
<=
secbar_master_o
(
6
);
periph_slave_i
(
2
)
<=
secbar_master_o
(
7
);
aux_adr_o
<=
secbar_master_o
(
8
)
.
adr
;
aux_dat_o
<=
secbar_master_o
(
8
)
.
dat
;
aux_sel_o
<=
secbar_master_o
(
8
)
.
sel
;
aux_cyc_o
<=
secbar_master_o
(
8
)
.
cyc
;
aux_stb_o
<=
secbar_master_o
(
8
)
.
stb
;
aux_we_o
<=
secbar_master_o
(
8
)
.
we
;
secbar_master_i
(
8
)
.
dat
<=
aux_dat_i
;
secbar_master_i
(
8
)
.
ack
<=
aux_ack_i
;
secbar_master_i
(
8
)
.
stall
<=
aux_stall_i
;
secbar_master_i
(
8
)
.
err
<=
'0'
;
secbar_master_i
(
8
)
.
rty
<=
'0'
;
secbar_master_i
(
4
)
<=
periph_slave_o
(
0
);
secbar_master_i
(
5
)
<=
periph_slave_o
(
1
);
secbar_master_i
(
6
)
<=
periph_slave_o
(
2
);
periph_slave_i
(
0
)
<=
secbar_master_o
(
4
);
periph_slave_i
(
1
)
<=
secbar_master_o
(
5
);
periph_slave_i
(
2
)
<=
secbar_master_o
(
6
);
aux_adr_o
<=
secbar_master_o
(
7
)
.
adr
;
aux_dat_o
<=
secbar_master_o
(
7
)
.
dat
;
aux_sel_o
<=
secbar_master_o
(
7
)
.
sel
;
aux_cyc_o
<=
secbar_master_o
(
7
)
.
cyc
;
aux_stb_o
<=
secbar_master_o
(
7
)
.
stb
;
aux_we_o
<=
secbar_master_o
(
7
)
.
we
;
secbar_master_i
(
7
)
.
dat
<=
aux_dat_i
;
secbar_master_i
(
7
)
.
ack
<=
aux_ack_i
;
secbar_master_i
(
7
)
.
stall
<=
aux_stall_i
;
secbar_master_i
(
7
)
.
err
<=
'0'
;
secbar_master_i
(
7
)
.
rty
<=
'0'
;
secbar_master_i
(
7
)
.
int
<=
'0'
;
--secbar_master_i(6).err <= '0';
--secbar_master_i(5).err <= '0';
--secbar_master_i(4).err <= '0';
--secbar_master_i(3).err <= '0';
--secbar_master_i(2).err <= '0';
--secbar_master_i(1).err <= '0';
--secbar_master_i(0).err <= '0';
--secbar_master_i(6).rty <= '0';
--secbar_master_i(5).rty <= '0';
--secbar_master_i(4).rty <= '0';
--secbar_master_i(3).rty <= '0';
--secbar_master_i(2).rty <= '0';
--secbar_master_i(1).rty <= '0';
--secbar_master_i(0).rty <= '0';
-----------------------------------------------------------------------------
-- WBP MUX
...
...
@@ -1002,6 +1031,7 @@ begin
mux_src_in
(
1
)
.
ack
<=
ext_src_ack_i
;
mux_src_in
(
1
)
.
stall
<=
ext_src_stall_i
;
mux_src_in
(
1
)
.
err
<=
ext_src_err_i
;
mux_src_in
(
1
)
.
rty
<=
'0'
;
mux_snk_in
(
1
)
.
adr
<=
ext_snk_adr_i
;
mux_snk_in
(
1
)
.
dat
<=
ext_snk_dat_i
;
...
...
modules/wrc_core/wrc_periph.vhd
View file @
fe045ba6
...
...
@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-04-04
-- Last update: 201
2-04-30
-- Last update: 201
7-02-03
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -164,7 +164,8 @@ begin
-------------------------------------
-- TIMER
-------------------------------------
sysc_regs_i
.
tvr_i
<=
std_logic_vector
(
cntr_tics
);
sysc_regs_i
.
tvr_i
<=
std_logic_vector
(
cntr_tics
);
sysc_regs_i
.
tcr_tdiv_i
<=
(
others
=>
'0'
);
process
(
clk_sys_i
)
begin
...
...
modules/wrc_core/wrcore_pkg.vhd
View file @
fe045ba6
...
...
@@ -287,7 +287,6 @@ package wrcore_pkg is
dac_out_load_o
:
out
std_logic
;
out_enable_i
:
in
std_logic_vector
(
g_num_outputs
-1
downto
0
);
out_locked_o
:
out
std_logic_vector
(
g_num_outputs
-1
downto
0
);
out_status_o
:
out
std_logic_vector
(
4
*
g_num_outputs
-1
downto
0
);
slave_i
:
in
t_wishbone_slave_in
;
slave_o
:
out
t_wishbone_slave_out
;
debug_o
:
out
std_logic_vector
(
5
downto
0
);
...
...
@@ -423,7 +422,6 @@ package wrcore_pkg is
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
dio_o
:
out
std_logic_vector
(
3
downto
0
);
rst_aux_n_o
:
out
std_logic
;
link_ok_o
:
out
std_logic
;
...
...
@@ -651,7 +649,6 @@ package wrcore_pkg is
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
dio_o
:
out
std_logic_vector
(
3
downto
0
);
rst_aux_n_o
:
out
std_logic
;
link_ok_o
:
out
std_logic
;
...
...
modules/wrc_core/xwr_core.vhd
View file @
fe045ba6
...
...
@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-02
-- Last update: 201
4-07-15
-- Last update: 201
7-02-01
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -243,7 +243,6 @@ entity xwr_core is
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
dio_o
:
out
std_logic_vector
(
3
downto
0
);
rst_aux_n_o
:
out
std_logic
;
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
...
...
@@ -409,7 +408,6 @@ begin
pps_p_o
=>
pps_p_o
,
pps_led_o
=>
pps_led_o
,
dio_o
=>
dio_o
,
rst_aux_n_o
=>
rst_aux_n_o
,
link_ok_o
=>
link_ok_o
,
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment