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White Rabbit core collection
Commit fdba4cfb authored by Maciej Lipinski's avatar Maciej Lipinski Committed by Grzegorz Daniluk
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added chopscope debugging for tx_pcs_fifo, small changes related to IFG in tx_header_processor

parent 49160eb0
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Showing with 40 additions and 23 deletions
modules/wr_endpoint/endpoint_pkg.vhd
View file @ fdba4cfb
......@@ -142,8 +142,8 @@ package endpoint_pkg is
link_kill_i : in std_logic := '0';
link_up_o : out std_logic;
dbg_o : out std_logic_vector(63 downto 0);
dbg_tx_pcs_wr_count_o : out std_logic_vector(5 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5 downto 0));
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0));
end component;
component wr_endpoint
......@@ -255,8 +255,8 @@ package endpoint_pkg is
link_kill_i : in std_logic := '0';
link_up_o : out std_logic;
dbg_o : out std_logic_vector(63 downto 0);
dbg_tx_pcs_wr_count_o : out std_logic_vector(5 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5 downto 0));
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0));
end component;
constant c_xwr_endpoint_sdb : t_sdb_device := (
......
modules/wr_endpoint/ep_1000basex_pcs.vhd
View file @ fdba4cfb
......@@ -179,8 +179,8 @@ entity ep_1000basex_pcs is
mdio_rw_i : in std_logic;
mdio_ready_o : out std_logic;
dbg_tx_pcs_wr_count_o : out std_logic_vector(5 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5 downto 0)
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0)
);
end ep_1000basex_pcs;
......@@ -227,8 +227,8 @@ architecture rtl of ep_1000basex_pcs is
phy_tx_k_o : out std_logic_vector(1 downto 0);
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
dbg_wr_count_o : out std_logic_vector(5 downto 0);
dbg_rd_count_o : out std_logic_vector(5 downto 0)
dbg_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_rd_count_o : out std_logic_vector(5+4 downto 0)
);
end component;
......
modules/wr_endpoint/ep_tx_header_processor.vhd
View file @ fdba4cfb
......@@ -133,7 +133,7 @@ end ep_tx_header_processor;
architecture behavioral of ep_tx_header_processor is
constant c_IFG_LENGTH : integer := 6;
constant c_IFG_LENGTH : integer := g_force_gap_length ;--6;
type t_tx_framer_state is (TXF_IDLE, TXF_DELAYED_SOF, TXF_ADDR, TXF_DATA, TXF_GAP, TXF_PAD, TXF_ABORT, TXF_STORE_TSTAMP);
......@@ -471,7 +471,8 @@ begin -- behavioral
src_fab_o.eof <= '1';
counter <= (others => '0');
if(g_force_gap_length = 0 and bitsel_d = '1') then
if(g_force_gap_length = 0 and bitsel_d = '1') then -- only for odd
-- if(g_force_gap_length = 0 ) then
-- Submit the TX timestamp to the TXTSU queue
if(oob.valid = '1' and oob.oob_type = c_WRF_OOB_TYPE_TX) then
if(pcs_busy_i = '0') then
......@@ -516,6 +517,7 @@ begin -- behavioral
src_fab_o.dvalid <= '0';
wb_out.err <= '0';
wb_out.rty <= '0';
src_fab_o.bytesel <= '0';
if(counter = c_IFG_LENGTH or g_force_gap_length = 0) then
......
modules/wr_endpoint/ep_tx_pcs_16bit.vhd
View file @ fdba4cfb
......@@ -109,8 +109,8 @@ entity ep_tx_pcs_16bit is
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
dbg_wr_count_o : out std_logic_vector(5 downto 0);
dbg_rd_count_o : out std_logic_vector(5 downto 0)
dbg_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_rd_count_o : out std_logic_vector(5+4 downto 0)
);
end ep_tx_pcs_16bit;
......@@ -151,8 +151,20 @@ architecture behavioral of ep_tx_pcs_16bit is
signal s_one : std_logic := '1';
signal an_tx_en_synced : std_logic;
signal wr_count : std_logic_vector(6 downto 0);
signal rd_count : std_logic_vector(6 downto 0);
constant tx_interframe_gap: unsigned(3 downto 0) := x"2"; --ML changed from "1000" to 0010
-- effectively it is 6 cycles for IFG:
-- last data (CRC) of the previous frame
-- -----------------------------------------
-- 3 cycles for count down (2 downto 0)
-- 1 cycle fifo_rd
-- 1 read SOF from FIFO
-- 1 cycle in TX_SPD_PREAMBLE
-- -----------------------------------------
-- just now we send Preamble
--
begin
U_sync_an_tx_en : gc_sync_ffs
......@@ -235,11 +247,11 @@ begin
U_TX_FIFO : generic_async_fifo
generic map (
g_data_width => 18,
g_size => 64,
g_size => 128,--64,
g_with_rd_empty => true,
g_with_rd_almost_empty => true,
g_with_wr_almost_full => true,
g_almost_empty_threshold => 20,
g_almost_empty_threshold => 40,
-- ML this is a hack: we have a problem, the native FIFO that was used here
-- is not working ocrrectly (probably something with full/empty/etc signals
......@@ -254,7 +266,7 @@ begin
g_with_rd_count => true, -- ML debug
g_with_wr_count => true, -- ML debug
g_almost_full_threshold => 50) -- fixme: make this a generic (or WB register)
g_almost_full_threshold => 100) -- fixme: make this a generic (or WB register)
port map (
rst_n_i => fifo_clear_n,
clk_wr_i => clk_sys_i,
......@@ -264,7 +276,7 @@ begin
wr_full_o => dbg_wr_count_o(1), --open,
wr_almost_empty_o => dbg_wr_count_o(2), --open,
wr_almost_full_o => fifo_almost_full,
wr_count_o => open, --dbg_wr_count_o,--open,
wr_count_o => wr_count,
clk_rd_i => phy_tx_clk_i,
q_o => fifo_packed_out,
rd_i => fifo_read_int,
......@@ -272,11 +284,14 @@ begin
rd_full_o => dbg_rd_count_o(1) ,--open,
rd_almost_empty_o => fifo_almost_empty,
rd_almost_full_o => dbg_rd_count_o(3),
rd_count_o => open);--dbg_rd_count_o); --open);
rd_count_o => rd_count); --rd_count);--dbg_rd_count_o); --open);
dbg_wr_count_o(3) <= fifo_almost_full;
dbg_rd_count_o(0) <= fifo_empty;
dbg_rd_count_o(2) <= fifo_almost_empty;
dbg_wr_count_o(9 downto 4) <= wr_count(5 downto 0);
dbg_rd_count_o(9 downto 4) <= rd_count(5 downto 0);
fifo_enough_data <= not fifo_almost_empty;
......
modules/wr_endpoint/wr_endpoint.vhd
View file @ fdba4cfb
......@@ -282,8 +282,8 @@ entity wr_endpoint is
-- (e.g.: cable disconnected)
link_up_o : out std_logic;
dbg_o : out std_logic_vector(63 downto 0);
dbg_tx_pcs_wr_count_o : out std_logic_vector(5 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5 downto 0)
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0)
);
end wr_endpoint;
......@@ -434,8 +434,8 @@ architecture syn of wr_endpoint is
mdio_stb_i : in std_logic;
mdio_rw_i : in std_logic;
mdio_ready_o : out std_logic;
dbg_tx_pcs_wr_count_o : out std_logic_vector(5 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5 downto 0));
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0));
end component;
component ep_timestamping_unit
......
modules/wr_endpoint/xwr_endpoint.vhd
View file @ fdba4cfb
......@@ -245,8 +245,8 @@ entity xwr_endpoint is
link_kill_i : in std_logic := '0';
link_up_o : out std_logic;
dbg_o : out std_logic_vector(63 downto 0);
dbg_tx_pcs_wr_count_o : out std_logic_vector(5 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5 downto 0)
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0)
);
end xwr_endpoint;
......
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