board: initial support for Xilinx ZCU106 devkit

fc94ea07 · Tomasz Wlostowski · f38234c0 · fc94ea07 · fc94ea07 · fc94ea07
Commit fc94ea07 authored Dec 06, 2019 by Tomasz Wlostowski
7 changed files
--- a/board/zcu106/Manifest.py
+++ b/board/zcu106/Manifest.py
+files = [
+    "xwrc_board_zcu106.vhd" 
+]
+
+modules = {
+    "local" : [
+        "../common",
+    ]
+}
--- a/board/zcu106/wrc_board_zcu106.vhd
+++ b/board/zcu106/wrc_board_zcu106.vhd
+-------------------------------------------------------------------------------
+-- Title      : WRPC Wrapper for SIS8300KU
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : wrc_board_sis8300ku.vhd
+-- Author(s)  : Tomasz Wlostowski
+-- Company    : CERN (BE-CO-HT)
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Top-level wrapper for WR PTP core including all the modules
+-- needed to operate the core on the SIS8300KU board.
+-- Version with no VHDL records on the top-level (mainly for Verilog
+-- instantiation and the F****ING Vivado schematic editor).
+-- http://www.ohwr.org/projects/fasec/
+-------------------------------------------------------------------------------
+-- Copyright (c) 2018 CERN
+-------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.wrcore_pkg.all;
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.streamers_pkg.all;
+use work.wr_xilinx_pkg.all;
+use work.wr_board_pkg.all;
+
+entity wrc_board_zcu106 is
+  generic(
+    -- set to 1 to speed up some initialization processes during simulation
+    g_simulation           : integer := 0;
+    -- Number of aux clocks syntonized by WRPC to WR timebase
+    g_aux_clks             : integer := 0;
+    -- "plainfbrc" = expose WRC fabric interface
+    -- "streamers" = attach WRC streamers to fabric interface
+    -- "etherbone" = attach Etherbone slave to fabric interface
+    g_fabric_iface         : string  := "plainfbrc";
+    -- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
+    --g_streamers_op_mode        : t_streamers_op_mode  := TX_AND_RX;
+    --g_tx_streamer_params       : t_tx_streamer_params := c_tx_streamer_params_defaut;
+    --g_rx_streamer_params       : t_rx_streamer_params := c_rx_streamer_params_defaut;
+    -- memory initialisation file for embedded CPU
+    g_dpram_initf          : string  := "../../../../bin/wrpc/wrc-bootloader.bram";
+    -- identification (id and ver) of the layout of words in the generic diag interface
+    g_diag_id              : integer := 0;
+    g_diag_ver             : integer := 0;
+    -- size the generic diag interface
+    g_diag_ro_vector_width : integer := 0;
+    g_diag_rw_vector_width : integer := 0
+    );
+  port (
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+    -- Reset from system fpga
+    areset_i       : in std_logic := '0';
+    -- Optional reset input active low with rising edge detection. Does not
+    -- reset PLLs.
+    --areset_edge_n_i     : in  std_logic := '1';
+    -- Clock inputs from the board
+    clk_20m_vcxo_i   : in std_logic;
+    clk_125m_pci_i   : in std_logic;
+
+    clk_125m_user_p_i : in std_logic;
+    clk_125m_user_n_i : in std_logic;
+ 
+    -- External PPS input (g_with_external_clock_input = TRUE)
+    pps_ext_i        : in  std_logic := '0';
+    -- 62.5MHz sys clock output
+    clk_sys_62m5_o   : out std_logic;
+    -- 125MHz ref clock output
+    clk_ref_125m_o   : out std_logic;
+    -- active low reset outputs, synchronous to 62m5 and 125m clocks
+    rst_sys_62m5_n_o : out std_logic;
+    rst_ref_125m_n_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Shared SPI interface to DACs
+    ---------------------------------------------------------------------------
+    plldac_sclk_o   : out std_logic;
+    plldac_din_o    : out std_logic;
+    pll25dac_cs_n_o : out std_logic;
+    pll20dac_cs_n_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- SFP I/O for transceiver and SFP management info
+    ---------------------------------------------------------------------------
+    sfp_tx_p_o        : out std_logic;
+    sfp_tx_n_o        : out std_logic;
+    sfp_rx_p_i        : in  std_logic;
+    sfp_rx_n_i        : in  std_logic;
+    sfp_det_i         : in  std_logic := '1';
+
+    sfp_sda_i         : in  std_logic;
+    sfp_sda_o         : out std_logic;
+    sfp_sda_t         : out std_logic;
+    sfp_scl_i         : in  std_logic;
+    sfp_scl_o         : out std_logic;
+    sfp_scl_t         : out std_logic;
+
+    sfp_rate_select_o : out std_logic;
+    sfp_tx_fault_i    : in  std_logic := '0';
+    sfp_tx_disable_n_o  : out std_logic;
+    sfp_los_i         : in  std_logic := '0';
+
+    uart_txd_o : out std_logic;
+    uart_rxd_i : in std_logic := '1';
+    
+    ---------------------------------------------------------------------------
+    -- Flash memory SPI interface
+    ---------------------------------------------------------------------------
+    flash_sclk_o : out std_logic;
+    flash_ncs_o  : out std_logic;
+    flash_mosi_o : out std_logic;
+    flash_miso_i : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- External WB interface
+    ---------------------------------------------------------------------------
+    --aux_master_adr_o   : out std_logic_vector(c_wishbone_address_width-1 downto 0);
+    --aux_master_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    --aux_master_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
+    --aux_master_sel_o   : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
+    --aux_master_we_o    : out std_logic;
+    --aux_master_cyc_o   : out std_logic;
+    --aux_master_stb_o   : out std_logic;
+    --aux_master_ack_i   : in  std_logic                                          := '0';
+    --aux_master_int_i   : in  std_logic                                          := '0';
+    --aux_master_err_i   : in  std_logic                                          := '0';
+    --aux_master_rty_i   : in  std_logic                                          := '0';
+    --aux_master_stall_i : in  std_logic                                          := '0';
+
+    ------------------------------------------
+    -- Axi Slave Bus Interface S00_AXI
+    ------------------------------------------
+    s00_axi_aclk_o  : out std_logic;
+    s00_axi_aresetn : in  std_logic                     := '1';
+    s00_axi_awaddr  : in  std_logic_vector(31 downto 0) := (others => '0');
+    --s00_axi_awprot  : in  std_logic_vector(2 downto 0);
+    s00_axi_awvalid : in  std_logic                     := '0';
+    s00_axi_awready : out std_logic;
+    s00_axi_wdata   : in  std_logic_vector(31 downto 0) := (others => '0');
+    s00_axi_wstrb   : in  std_logic_vector(3 downto 0)  := (others => '0');
+    s00_axi_wvalid  : in  std_logic                     := '0';
+    s00_axi_wready  : out std_logic;
+    s00_axi_bresp   : out std_logic_vector(1 downto 0);
+    s00_axi_bvalid  : out std_logic;
+    s00_axi_bready  : in  std_logic                     := '0';
+    s00_axi_araddr  : in  std_logic_vector(31 downto 0) := (others => '0');
+    --s00_axi_arprot  : in std_logic_vector(2 downto 0);
+    s00_axi_arvalid : in  std_logic                     := '0';
+    s00_axi_arready : out std_logic;
+    s00_axi_rdata   : out std_logic_vector(31 downto 0);
+    s00_axi_rresp   : out std_logic_vector(1 downto 0);
+    s00_axi_rvalid  : out std_logic;
+    s00_axi_rready  : in  std_logic                     := '0';
+    s00_axi_rlast   : out std_logic;
+    axi_int_o       : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- WR fabric interface (when g_fabric_iface = "plain")
+    ---------------------------------------------------------------------------
+    --wrf_src_adr_o   : out std_logic_vector(1 downto 0);
+    --wrf_src_dat_o   : out std_logic_vector(15 downto 0);
+    --wrf_src_cyc_o   : out std_logic;
+    --wrf_src_stb_o   : out std_logic;
+    --wrf_src_we_o    : out std_logic;
+    --wrf_src_sel_o   : out std_logic_vector(1 downto 0);
+    --wrf_src_ack_i   : in  std_logic;
+    --wrf_src_stall_i : in  std_logic;
+    --wrf_src_err_i   : in  std_logic;
+    --wrf_src_rty_i   : in  std_logic;
+    --wrf_snk_adr_i   : in  std_logic_vector(1 downto 0);
+    --wrf_snk_dat_i   : in  std_logic_vector(15 downto 0);
+    --wrf_snk_cyc_i   : in  std_logic;
+    --wrf_snk_stb_i   : in  std_logic;
+    --wrf_snk_we_i    : in  std_logic;
+    --wrf_snk_sel_i   : in  std_logic_vector(1 downto 0);
+    --wrf_snk_ack_o   : out std_logic;
+    --wrf_snk_stall_o : out std_logic;
+    --wrf_snk_err_o   : out std_logic;
+    --wrf_snk_rty_o   : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- WR streamers (when g_fabric_iface = "streamers")
+    ---------------------------------------------------------------------------
+    ----wrs_tx_data_i  : in  std_logic_vector(c_tx_streamer_params_defaut.data_width-1 downto 0) := (others => '0');
+    --wrs_tx_data_i  : in  std_logic_vector(31 downto 0) := (others => '0');
+    --wrs_tx_valid_i : in  std_logic                                        := '0';
+    --wrs_tx_dreq_o  : out std_logic;
+    --wrs_tx_last_i  : in  std_logic                                        := '1';
+    --wrs_tx_flush_i : in  std_logic                                        := '0';
+    --wrs_tx_cfg_mac_l_i : in  std_logic_vector(47 downto 0)                := x"000000000000";
+    --wrs_tx_cfg_mac_t_i : in  std_logic_vector(47 downto 0)                := x"ffffffffffff";
+    --wrs_tx_cfg_etype_i : in  std_logic_vector(15 downto 0)                := x"dbff";
+    --wrs_rx_first_o : out std_logic;
+    --wrs_rx_last_o  : out std_logic;
+    ----wrs_rx_data_o  : out std_logic_vector(c_rx_streamer_params_defaut.data_width-1 downto 0);
+    --wrs_rx_data_o  : out std_logic_vector(31 downto 0);
+    --wrs_rx_valid_o : out std_logic;
+    --wrs_rx_dreq_i  : in  std_logic                                        := '0';
+    --wrs_rx_cfg_mac_l_i : in std_logic_vector(47 downto 0)                 := x"000000000000";
+    --wrs_rx_cfg_mac_r_i : in std_logic_vector(47 downto 0)                 := x"000000000000";
+    --wrs_rx_cfg_etype_i : in std_logic_vector(15 downto 0)                 := x"dbff";
+    --wrs_rx_cfg_acc_b_i : in std_logic                                     := '1';
+    --wrs_rx_cfg_flt_r_i : in std_logic                                     := '0';
+    --wrs_rx_cfg_fix_l_i : in std_logic_vector(27 downto 0)                 := x"0000000";
+    ---------------------------------------------------------------------------
+    -- Etherbone WB master interface (when g_fabric_iface = "etherbone")
+    ---------------------------------------------------------------------------
+    --wb_eth_adr_o   : out std_logic_vector(c_wishbone_address_width-1 downto 0);
+    --wb_eth_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    --wb_eth_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
+    --wb_eth_sel_o   : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
+    --wb_eth_we_o    : out std_logic;
+    --wb_eth_cyc_o   : out std_logic;
+    --wb_eth_stb_o   : out std_logic;
+    --wb_eth_ack_i   : in  std_logic                                          := '0';
+    --wb_eth_int_i   : in  std_logic                                          := '0';
+    --wb_eth_err_i   : in  std_logic                                          := '0';
+    --wb_eth_rty_i   : in  std_logic                                          := '0';
+    --wb_eth_stall_i : in  std_logic                                          := '0';
+
+    ---------------------------------------------------------------------------
+    -- Generic diagnostics interface (access from WRPC via SNMP or uart console
+    ---------------------------------------------------------------------------
+    --aux_diag_i : in  std_logic_vector(g_diag_ro_vector_width - 1 downto 0) := (others => '0');
+    --aux_diag_o : out std_logic_vector(g_diag_rw_vector_width - 1 downto 0) := (others => '0');
+
+    ---------------------------------------------------------------------------
+    -- Aux clocks control
+    ---------------------------------------------------------------------------
+    --tm_dac_value_o       : out std_logic_vector(23 downto 0);
+    --tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+    --tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+    --tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- External Tx Timestamping I/F
+    ---------------------------------------------------------------------------
+    --tstamps_stb_o       : out std_logic;
+    --tstamps_tsval_o     : out std_logic_vector(31 downto 0);
+    --tstamps_port_id_o   : out std_logic_vector(5 downto 0);
+    --tstamps_frame_id_o  : out std_logic_vector(15 downto 0);
+    --tstamps_incorrect_o : out std_logic;
+    --tstamps_ack_i       : in  std_logic := '1';
+
+    -----------------------------------------
+    -- Timestamp helper signals, used for Absolute Calibration
+    -----------------------------------------
+    --abscal_txts_o       : out std_logic;
+    --abscal_rxts_o       : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Pause Frame Control
+    ---------------------------------------------------------------------------
+    --fc_tx_pause_req_i   : in  std_logic                     := '0';
+    --fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+    --fc_tx_pause_ready_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Timecode I/F
+    ---------------------------------------------------------------------------
+    --tm_link_up_o    : out std_logic;
+    --tm_time_valid_o : out std_logic;
+    --tm_tai_o        : out std_logic_vector(39 downto 0);
+    --tm_cycles_o     : out std_logic_vector(27 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- Buttons, LEDs and PPS output
+    ---------------------------------------------------------------------------
+
+    leds_i        : in  std_logic_vector(15 downto 0);
+    leds_serial_o : out std_logic;
+
+    -- 1PPS output
+    pps_p_o   : out std_logic;
+    link_ok_o : out std_logic
+    );
+
+end entity wrc_board_zcu106;
+
+
+architecture std_wrapper of wrc_board_zcu106 is
+
+  signal sfp_tx_disable : std_logic;
+  -----------------------------------------------------------------------------
+  -- Signals
+  -----------------------------------------------------------------------------
+signal areset_n : std_logic;
+  -- WR fabric interface
+  signal wrf_src_out : t_wrf_source_out;
+  signal wrf_src_in  : t_wrf_source_in;
+  signal wrf_snk_out : t_wrf_sink_out;
+  signal wrf_snk_in  : t_wrf_sink_in;
+
+  signal aux_master_out : t_wishbone_master_out;
+  signal aux_master_in  : t_wishbone_master_in;
+
+  -- Etherbone interface
+  signal wb_eth_master_out : t_wishbone_master_out;
+  signal wb_eth_master_in  : t_wishbone_master_in;
+
+  -- Aux diagnostics
+  constant c_diag_ro_size : integer := g_diag_ro_vector_width/32;
+  constant c_diag_rw_size : integer := g_diag_rw_vector_width/32;
+
+  signal aux_diag_in  : t_generic_word_array(c_diag_ro_size-1 downto 0);
+  signal aux_diag_out : t_generic_word_array(c_diag_rw_size-1 downto 0);
+
+  -- External Tx Timestamping I/F
+  signal timestamps_out : t_txtsu_timestamp;
+
+  -- streamers config
+  signal wrs_tx_cfg_in : t_tx_streamer_cfg;
+  signal wrs_rx_cfg_in : t_rx_streamer_cfg;
+
+  -- axi signals
+  signal s_axi_araddr : std_logic_vector(31 downto 0);
+  signal s_axi_awaddr : std_logic_vector(31 downto 0);
+
+  attribute X_INTERFACE_PARAMETER                    : string;
+  attribute X_INTERFACE_INFO                         : string;
+  attribute X_INTERFACE_PARAMETER of s00_axi_aresetn : signal is "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME s00_axi_aresetn, POLARITY ACTIVE_LOW";
+  attribute X_INTERFACE_INFO of s00_axi_aresetn      : signal is "xilinx.com:signal:reset:1.0 S00_AXI_RST RST, xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
+  attribute X_INTERFACE_PARAMETER of s00_axi_aclk_o  : signal is "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 62500000, PHASE 0.000, XIL_INTERFACENAME s00_axi_aclk_o, ASSOCIATED_RESET s00_axi_aresetn";
+  attribute X_INTERFACE_INFO of s00_axi_aclk_o       : signal is "xilinx.com:signal:clock:1.0 S01_AXI_CLK CLK, xilinx.com:signal:clock:1.0 s00_axi_aclk_o CLK";
+
+
+  attribute mark_debug : string;
+
+  attribute mark_debug of s00_axi_aresetn : signal is "TRUE";
+  attribute mark_debug of s00_axi_awaddr  : signal is "TRUE";
+  attribute mark_debug of s00_axi_awvalid : signal is "TRUE";
+  attribute mark_debug of s00_axi_awready : signal is "TRUE";
+  attribute mark_debug of s00_axi_wdata   : signal is "TRUE";
+  attribute mark_debug of s00_axi_wstrb   : signal is "TRUE";
+  attribute mark_debug of s00_axi_wvalid  : signal is "TRUE";
+  attribute mark_debug of s00_axi_wready  : signal is "TRUE";
+  attribute mark_debug of s00_axi_bresp   : signal is "TRUE";
+  attribute mark_debug of s00_axi_bvalid  : signal is "TRUE";
+  attribute mark_debug of s00_axi_bready  : signal is "TRUE";
+  attribute mark_debug of s00_axi_araddr  : signal is "TRUE";
+  attribute mark_debug of s00_axi_arvalid : signal is "TRUE";
+  attribute mark_debug of s00_axi_arready : signal is "TRUE";
+  attribute mark_debug of s00_axi_rdata   : signal is "TRUE";
+  attribute mark_debug of s00_axi_rresp   : signal is "TRUE";
+  attribute mark_debug of s00_axi_rvalid  : signal is "TRUE";
+  attribute mark_debug of s00_axi_rready  : signal is "TRUE";
+  attribute mark_debug of s00_axi_rlast   : signal is "TRUE";
+
+begin  -- architecture struct
+
+  areset_n <= not areset_i;
+  
+  -- Map top-level signals to internal records
+  --aux_master_adr_o <= aux_master_out.adr;
+  --aux_master_dat_o <= aux_master_out.dat;
+  --aux_master_cyc_o <= aux_master_out.cyc;
+  --aux_master_stb_o <= aux_master_out.stb;
+  --aux_master_sel_o <= aux_master_out.sel;
+  --aux_master_we_o  <= aux_master_out.we;
+
+  --aux_master_in.dat   <= aux_master_dat_i;
+  --aux_master_in.ack   <= aux_master_ack_i;
+  --aux_master_in.int   <= aux_master_int_i;
+  --aux_master_in.err   <= aux_master_err_i;
+  --aux_master_in.rty   <= aux_master_rty_i;
+  --aux_master_in.stall <= aux_master_stall_i;
+
+  --wrf_src_adr_o    <= wrf_src_out.adr;
+  --wrf_src_dat_o    <= wrf_src_out.dat;
+  --wrf_src_cyc_o    <= wrf_src_out.cyc;
+  --wrf_src_stb_o    <= wrf_src_out.stb;
+  --wrf_src_we_o     <= wrf_src_out.we;
+  --wrf_src_sel_o    <= wrf_src_out.sel;
+  --wrf_src_in.ack   <= wrf_src_ack_i;
+  --wrf_src_in.stall <= wrf_src_stall_i;
+  --wrf_src_in.err   <= wrf_src_err_i;
+  --wrf_src_in.rty   <= wrf_src_rty_i;
+
+  --wrf_snk_in.adr  <= wrf_snk_adr_i;
+  --wrf_snk_in.dat  <= wrf_snk_dat_i;
+  --wrf_snk_in.cyc  <= wrf_snk_cyc_i;
+  --wrf_snk_in.stb  <= wrf_snk_stb_i;
+  --wrf_snk_in.we   <= wrf_snk_we_i;
+  --wrf_snk_in.sel  <= wrf_snk_sel_i;
+  --wrf_snk_ack_o   <= wrf_snk_out.ack;
+  --wrf_snk_stall_o <= wrf_snk_out.stall;
+  --wrf_snk_err_o   <= wrf_snk_out.err;
+  --wrf_snk_rty_o   <= wrf_snk_out.rty;
+
+
+  --wb_eth_adr_o <= wb_eth_master_out.adr;
+  --wb_eth_dat_o <= wb_eth_master_out.dat;
+  --wb_eth_cyc_o <= wb_eth_master_out.cyc;
+  --wb_eth_stb_o <= wb_eth_master_out.stb;
+  --wb_eth_sel_o <= wb_eth_master_out.sel;
+  --wb_eth_we_o  <= wb_eth_master_out.we;
+
+  --wb_eth_master_in.dat   <= wb_eth_dat_i;
+  --wb_eth_master_in.ack   <= wb_eth_ack_i;
+  --wb_eth_master_in.int   <= wb_eth_int_i;
+  --wb_eth_master_in.err   <= wb_eth_err_i;
+  --wb_eth_master_in.rty   <= wb_eth_rty_i;
+  --wb_eth_master_in.stall <= wb_eth_stall_i;
+
+  --aux_diag_in <= f_de_vectorize_diag(aux_diag_i, g_diag_ro_vector_width);
+  --aux_diag_o  <= f_vectorize_diag(aux_diag_out, g_diag_rw_vector_width);
+
+  --tstamps_stb_o      <= timestamps_out.stb;
+  --tstamps_tsval_o    <= timestamps_out.tsval;
+  --tstamps_port_id_o  <= timestamps_out.port_id;
+  --tstamps_frame_id_o <= timestamps_out.frame_id;
+
+  --wrs_tx_cfg_in.mac_local         <= wrs_tx_cfg_mac_l_i;
+  --wrs_tx_cfg_in.mac_target        <= wrs_tx_cfg_mac_t_i;
+  --wrs_tx_cfg_in.ethertype         <= wrs_tx_cfg_etype_i;
+
+  --wrs_rx_cfg_in.mac_local         <= wrs_rx_cfg_mac_l_i;
+  --wrs_rx_cfg_in.mac_remote        <= wrs_rx_cfg_mac_r_i;
+  --wrs_rx_cfg_in.ethertype         <= wrs_rx_cfg_etype_i;
+  --wrs_rx_cfg_in.accept_broadcasts <= wrs_rx_cfg_acc_b_i;
+  --wrs_rx_cfg_in.filter_remote     <= wrs_rx_cfg_flt_r_i;
+  --wrs_rx_cfg_in.fixed_latency     <= wrs_rx_cfg_fix_l_i;
+
+  s_axi_araddr <= s00_axi_araddr(31 downto 0);
+  s_axi_awaddr <= s00_axi_awaddr(31 downto 0);
+  -- Instantiate the records-based module
+  cmp_xwrc_board_zcu106 : entity work.xwrc_board_zcu106
+    generic map (
+      g_simulation         => g_simulation,
+      g_aux_clks           => g_aux_clks,
+      g_fabric_iface       => f_str2iface_type(g_fabric_iface),
+      g_streamers_op_mode  => TX_AND_RX,
+      g_tx_streamer_params => c_tx_streamer_params_defaut,
+      g_rx_streamer_params => c_rx_streamer_params_defaut,
+      g_dpram_initf        => g_dpram_initf,
+      g_diag_id            => g_diag_id,
+      g_diag_ver           => g_diag_ver,
+      g_diag_ro_size       => c_diag_ro_size,
+      g_diag_rw_size       => c_diag_rw_size)
+    port map (
+      areset_n_i        => areset_n  ,
+      clk_20m_vcxo_i    => clk_20m_vcxo_i,
+      clk_125m_pci_i    => clk_125m_pci_i,
+      clk_125m_user_n_i => clk_125m_user_n_i,
+      clk_125m_user_p_i => clk_125m_user_p_i,
+      pps_ext_i         => pps_ext_i,
+      clk_sys_62m5_o    => clk_sys_62m5_o,
+      clk_ref_125m_o    => clk_ref_125m_o,
+      rst_sys_62m5_n_o  => rst_sys_62m5_n_o,
+      rst_ref_125m_n_o  => rst_ref_125m_n_o,
+      plldac_sclk_o     => plldac_sclk_o,
+      plldac_din_o      => plldac_din_o,
+      pll25dac_cs_n_o   => pll25dac_cs_n_o,
+      pll20dac_cs_n_o   => pll20dac_cs_n_o,
+      sfp_txp_o         => sfp_tx_p_o,
+      sfp_txn_o         => sfp_tx_n_o,
+      sfp_rxp_i         => sfp_rx_p_i,
+      sfp_rxn_i         => sfp_rx_n_i,
+      sfp_det_i         => sfp_det_i,
+      sfp_sda_i         => sfp_sda_i,
+      sfp_sda_o         => sfp_sda_o,
+      sfp_sda_t         => sfp_sda_t,
+      sfp_scl_i         => sfp_scl_i,
+      sfp_scl_o         => sfp_scl_o,
+      sfp_scl_t         => sfp_scl_t,
+      sfp_rate_select_o => sfp_rate_select_o,
+      sfp_tx_fault_i    => sfp_tx_fault_i,
+      sfp_tx_disable_o  => sfp_tx_disable,
+      sfp_los_i         => sfp_los_i,
+      flash_sclk_o      => flash_sclk_o,
+      flash_ncs_o       => flash_ncs_o,
+      flash_mosi_o      => flash_mosi_o,
+      flash_miso_i      => flash_miso_i,
+      s00_axi_aclk_o    => s00_axi_aclk_o,
+      s00_axi_aresetn   => s00_axi_aresetn,
+      s00_axi_awaddr    => s00_axi_awaddr,
+      s00_axi_awprot    => (others => '0'), 
+      s00_axi_awvalid   => s00_axi_awvalid,
+      s00_axi_awready   => s00_axi_awready,
+      s00_axi_wdata     => s00_axi_wdata,
+      s00_axi_wstrb     => s00_axi_wstrb,
+      s00_axi_wvalid    => s00_axi_wvalid,
+      s00_axi_wready    => s00_axi_wready,
+      s00_axi_bresp     => s00_axi_bresp,
+      s00_axi_bvalid    => s00_axi_bvalid,
+      s00_axi_bready    => s00_axi_bready,
+      s00_axi_araddr    => s00_axi_araddr,
+      s00_axi_arprot    => (others => '0'), 
+      s00_axi_arvalid   => s00_axi_arvalid,
+      s00_axi_arready   => s00_axi_arready,
+      s00_axi_rdata     => s00_axi_rdata,
+      s00_axi_rresp     => s00_axi_rresp,
+      s00_axi_rvalid    => s00_axi_rvalid,
+      s00_axi_rready    => s00_axi_rready,
+      s00_axi_rlast     => s00_axi_rlast,
+      axi_int_o         => axi_int_o,
+      pps_p_o           => pps_p_o,
+      link_ok_o         => link_ok_o,
+      uart_rxd_i => uart_rxd_i,
+      uart_txd_o => uart_txd_o );
+
+--uart_txd_o <= uart_rxd_i;
+
+  sfp_tx_disable_n_o <= not sfp_tx_disable;
+  
+end architecture std_wrapper;
+
--- a/board/zcu106/xwrc_board_zcu106.vhd
+++ b/board/zcu106/xwrc_board_zcu106.vhd
+-------------------------------------------------------------------------------
+-- Title      : WRPC Wrapper for ZCU106 devkit
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : xwrc_board_zcu106.vhd
+-- Author(s)  : Tomasz Wlostowski
+-- Company    : CERN (BE-CO-HT)
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Top-level wrapper for WR PTP core including all the modules
+-- needed to operate the core on the Zynq Ultrascale+ devkit ZCU106 board.
+-- http://www.ohwr.org/projects/fasec/
+-------------------------------------------------------------------------------
+-- Copyright (c) 2018 CERN
+-------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the sLicense, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.wrcore_pkg.all;
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.streamers_pkg.all;
+use work.wr_xilinx_pkg.all;
+use work.wr_board_pkg.all;
+use work.axi4_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity xwrc_board_zcu106 is
+  generic(
+    -- set to 1 to speed up some initialization processes during simulation
+    g_simulation                : integer              := 0;
+--    g_with_external_clock_input : boolean              := TRUE;
+    -- Number of aux clocks syntonized by WRPC to WR timebase
+    g_aux_clks                  : integer              := 0;
+    -- plain     = expose WRC fabric interface
+    -- streamers = attach WRC streamers to fabric interface
+    -- etherbone = attach Etherbone slave to fabric interface
+    g_fabric_iface              : t_board_fabric_iface := plain;
+    -- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
+    g_streamers_op_mode        : t_streamers_op_mode  := TX_AND_RX;
+    g_tx_streamer_params       : t_tx_streamer_params := c_tx_streamer_params_defaut;
+    g_rx_streamer_params       : t_rx_streamer_params := c_rx_streamer_params_defaut;
+    -- memory initialisation file for embedded CPU
+    g_dpram_initf               : string               := "../../bin/wrpc/wrc_phy16.bram";
+    -- identification (id and ver) of the layout of words in the generic diag interface
+    g_diag_id                   : integer              := 0;
+    g_diag_ver                  : integer              := 0;
+    -- size the generic diag interface
+    g_diag_ro_size              : integer              := 0;
+    g_diag_rw_size              : integer              := 0
+    );
+  port (
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+    -- Reset input (active low, can be async)
+    areset_n_i          : in  std_logic;
+    -- Optional reset input active low with rising edge detection. Does not
+    -- reset PLLs.
+    areset_edge_n_i     : in  std_logic := '1';
+    -- Clock inputs from the board
+    clk_20m_vcxo_i      : in  std_logic;
+    clk_125m_pci_i      : in std_logic;
+    clk_125m_gth_n_i    : in  std_logic := '0';
+    clk_125m_gth_p_i    : in  std_logic := '0';
+
+    clk_125m_user_p_i : in std_logic;
+    clk_125m_user_n_i : in std_logic;
+
+    -- Aux clocks, which can be disciplined by the WR Core
+    clk_aux_i           : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+    -- External PPS input (g_with_external_clock_input = TRUE)
+    pps_ext_i           : in  std_logic                               := '0';
+    -- 62.5MHz sys clock output
+    clk_sys_62m5_o      : out std_logic;
+    -- 125MHz ref clock output
+    clk_ref_125m_o      : out std_logic;
+    -- active low reset outputs, synchronous to 62m5 and 125m clocks
+    rst_sys_62m5_n_o    : out std_logic;
+    rst_ref_125m_n_o    : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Shared SPI interface to DACs
+    ---------------------------------------------------------------------------
+    plldac_sclk_o   : out std_logic;
+    plldac_din_o    : out std_logic;
+    pll25dac_cs_n_o : out std_logic;
+    pll20dac_cs_n_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- SFP I/O for transceiver and SFP management info
+    ---------------------------------------------------------------------------
+    sfp_txp_o         : out std_logic;
+    sfp_txn_o         : out std_logic;
+    sfp_rxp_i         : in  std_logic;
+    sfp_rxn_i         : in  std_logic;
+    sfp_det_i         : in  std_logic := '1';
+    sfp_sda_i         : in  std_logic;
+    sfp_sda_o         : out std_logic;
+    sfp_sda_t         : out std_logic;
+    sfp_scl_i         : in  std_logic;
+    sfp_scl_o         : out std_logic;
+    sfp_scl_t         : out std_logic;
+    sfp_rate_select_o : out std_logic;
+    sfp_tx_fault_i    : in  std_logic := '0';
+    sfp_tx_disable_o  : out std_logic;
+    sfp_los_i         : in  std_logic := '0';
+
+    ---------------------------------------------------------------------------
+    -- Flash memory SPI interface
+    ---------------------------------------------------------------------------
+    flash_sclk_o : out std_logic;
+    flash_ncs_o  : out std_logic;
+    flash_mosi_o : out std_logic;
+    flash_miso_i : in  std_logic := '0';
+
+    ---------------------------------------------------------------------------
+    -- External WB interface
+    ---------------------------------------------------------------------------
+    aux_master_o : out t_wishbone_master_out;
+    aux_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+
+    ------------------------------------------
+    -- Axi Slave Bus Interface S00_AXI
+    ------------------------------------------
+    -- aclk provided by this IP, wire to master!
+    s00_axi_aclk_o  : out std_logic;
+    s00_axi_aresetn : in  std_logic;
+    s00_axi_awaddr  : in std_logic_vector(31 downto 0);
+    s00_axi_awprot  : in  std_logic_vector(2 downto 0);
+    s00_axi_awvalid : in  std_logic;
+    s00_axi_awready : out std_logic;
+    s00_axi_wdata   : in std_logic_vector(31 downto 0);
+    s00_axi_wstrb   : in std_logic_vector(3 downto 0);
+    s00_axi_wvalid  : in  std_logic;
+    s00_axi_wready  : out std_logic;
+    s00_axi_bresp   : out std_logic_vector(1 downto 0);
+    s00_axi_bvalid  : out std_logic;
+    s00_axi_bready  : in std_logic;
+    s00_axi_araddr  : in std_logic_vector(31 downto 0);
+    s00_axi_arprot  : in std_logic_vector(2 downto 0);
+    s00_axi_arvalid : in std_logic;
+    s00_axi_arready : out std_logic;
+    s00_axi_rdata   : out std_logic_vector(31 downto 0);
+    s00_axi_rresp   : out std_logic_vector(1 downto 0);
+    s00_axi_rvalid  : out std_logic;
+    s00_axi_rready  : in std_logic;
+    s00_axi_rlast   : out std_logic;
+    axi_int_o       : out std_logic;  -- axi interrupt signal
+
+    ---------------------------------------------------------------------------
+    -- WR fabric interface (when g_fabric_iface = "plainfbrc")
+    ---------------------------------------------------------------------------
+    wrf_src_o : out t_wrf_source_out;
+    wrf_src_i : in  t_wrf_source_in := c_dummy_src_in;
+    wrf_snk_o : out t_wrf_sink_out;
+    wrf_snk_i : in  t_wrf_sink_in   := c_dummy_snk_in;
+
+    ---------------------------------------------------------------------------
+    -- WR streamers (when g_fabric_iface = "streamers")
+    ---------------------------------------------------------------------------
+    wrs_tx_data_i  : in  std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
+    wrs_tx_valid_i : in  std_logic                                        := '0';
+    wrs_tx_dreq_o  : out std_logic;
+    wrs_tx_last_i  : in  std_logic                                        := '1';
+    wrs_tx_flush_i : in  std_logic                                        := '0';
+    wrs_tx_cfg_i   : in  t_tx_streamer_cfg                                := c_tx_streamer_cfg_default;
+    wrs_rx_first_o : out std_logic;
+    wrs_rx_last_o  : out std_logic;
+    wrs_rx_data_o  : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
+    wrs_rx_valid_o : out std_logic;
+    wrs_rx_dreq_i  : in  std_logic                                        := '0';
+    wrs_rx_cfg_i   : in t_rx_streamer_cfg                                 := c_rx_streamer_cfg_default;
+    ---------------------------------------------------------------------------
+    -- Etherbone WB master interface (when g_fabric_iface = "etherbone")
+    ---------------------------------------------------------------------------
+    wb_eth_master_o : out t_wishbone_master_out;
+    wb_eth_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+
+    ---------------------------------------------------------------------------
+    -- Generic diagnostics interface (access from WRPC via SNMP or uart console
+    ---------------------------------------------------------------------------
+    aux_diag_i : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
+    aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- Aux clocks control
+    ---------------------------------------------------------------------------
+    tm_dac_value_o       : out std_logic_vector(23 downto 0);
+    tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+    tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+    tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- External Tx Timestamping I/F
+    ---------------------------------------------------------------------------
+    timestamps_o     : out t_txtsu_timestamp;
+    timestamps_ack_i : in  std_logic := '1';
+
+    -----------------------------------------
+    -- Timestamp helper signals, used for Absolute Calibration
+    -----------------------------------------
+    abscal_txts_o       : out std_logic;
+    abscal_rxts_o       : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Pause Frame Control
+    ---------------------------------------------------------------------------
+    fc_tx_pause_req_i   : in  std_logic                     := '0';
+    fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+    fc_tx_pause_ready_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Timecode I/F
+    ---------------------------------------------------------------------------
+    tm_link_up_o    : out std_logic;
+    tm_time_valid_o : out std_logic;
+    tm_tai_o        : out std_logic_vector(39 downto 0);
+    tm_cycles_o     : out std_logic_vector(27 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- Buttons, LEDs and PPS output
+    ---------------------------------------------------------------------------
+
+    -- 1PPS output
+    pps_p_o    : out std_logic;
+    link_ok_o  : out std_logic;
+
+    uart_txd_o : out std_logic;
+    uart_rxd_i : in std_logic := '1'
+
+    
+    );
+
+end entity xwrc_board_zcu106;
+
+
+architecture struct of xwrc_board_zcu106 is
+
+  -----------------------------------------------------------------------------
+  -- Signals
+  -----------------------------------------------------------------------------
+
+
+  -- PLLs, clocks
+  signal clk_pll_62m5 : std_logic;
+  signal clk_pll_125m : std_logic;
+  signal clk_pll_dmtd : std_logic;
+  signal pll_locked   : std_logic;
+
+  -- Reset logic
+  signal areset_edge_ppulse : std_logic;
+  signal rst_62m5_n         : std_logic;
+  signal rst_62m5         : std_logic;
+  signal rstlogic_arst_n    : std_logic;
+  signal rstlogic_clk_in    : std_logic_vector(1 downto 0);
+  signal rstlogic_rst_out   : std_logic_vector(1 downto 0);
+
+  -- PLL DAC ARB
+  signal dac_hpll_load_p1 : std_logic;
+  signal dac_hpll_data    : std_logic_vector(15 downto 0);
+  signal dac_dpll_load_p1 : std_logic;
+  signal dac_dpll_data    : std_logic_vector(15 downto 0);
+
+  -- PHY
+  signal phy16_to_wrc   : t_phy_16bits_to_wrc;
+  signal phy16_from_wrc : t_phy_16bits_from_wrc;
+
+  -- WRC WB Slave interface
+  signal wb_slave_out : t_wishbone_slave_out;
+  signal wb_slave_in  : t_wishbone_slave_in;
+
+  signal led_link, led_act, pps_led : std_logic;
+
+  signal clk_125m_user : std_logic;
+  
+begin  -- architecture struct
+
+   U_Buf : IBUFGDS
+    generic map (
+      IOSTANDARD => "DEFAULT",
+      DIFF_TERM => TRUE)
+    port map (
+      O  => clk_125m_user,
+      I  => clk_125m_user_p_i,
+      IB => clk_125m_user_n_i);
+
+  -----------------------------------------------------------------------------
+  -- Platform-dependent part (PHY, PLLs, buffers, etc)
+  -----------------------------------------------------------------------------
+
+
+  cmp_xwrc_platform : xwrc_platform_xilinx
+    generic map (
+      g_fpga_family               => "zynqultrascaleplus",
+      g_with_external_clock_input => FALSE,
+      g_use_default_plls          => TRUE,
+      g_simulation                => g_simulation)
+    port map (
+      areset_n_i            => areset_n_i,
+      clk_20m_vcxo_i        => clk_20m_vcxo_i,
+      clk_125m_pci_i        => clk_125m_user,
+      clk_125m_gtp_p_i      => clk_125m_gth_p_i,
+      clk_125m_gtp_n_i      => clk_125m_gth_n_i,
+      sfp_txn_o             => sfp_txn_o,
+      sfp_txp_o             => sfp_txp_o,
+      sfp_rxn_i             => sfp_rxn_i,
+      sfp_rxp_i             => sfp_rxp_i,
+      sfp_tx_fault_i        => sfp_tx_fault_i,
+      sfp_los_i             => sfp_los_i,
+      sfp_tx_disable_o      => sfp_tx_disable_o,
+      clk_62m5_sys_o        => clk_pll_62m5,
+      clk_125m_ref_o        => clk_pll_125m,
+      clk_62m5_dmtd_o       => clk_pll_dmtd,
+      pll_locked_o          => pll_locked,
+      phy16_o               => phy16_to_wrc,
+      phy16_i               => phy16_from_wrc,
+      ext_ref_rst_i         => '0');
+
+  clk_sys_62m5_o <= clk_pll_62m5;
+  clk_ref_125m_o <= clk_pll_125m;
+
+  -----------------------------------------------------------------------------
+  -- Reset logic
+  -----------------------------------------------------------------------------
+  -- Detect when areset_edge_n_i goes high (end of reset) and use this edge to
+  -- generate rstlogic_arst_n. This is needed to connect optional reset like PCIe
+  -- reset. When baord runs standalone, we need to ignore PCIe reset being
+  -- constantly low.
+  cmp_arst_edge: gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_pll_62m5,
+      rst_n_i  => '1',
+      data_i   => areset_edge_n_i,
+      ppulse_o => areset_edge_ppulse);
+
+  -- logic AND of all async reset sources (active low)
+  rstlogic_arst_n <= pll_locked and areset_n_i and (not areset_edge_ppulse);
+
+  -- concatenation of all clocks required to have synced resets
+  rstlogic_clk_in(0) <= clk_pll_62m5;
+  rstlogic_clk_in(1) <= clk_pll_125m;
+
+  cmp_rstlogic_reset : gc_reset
+    generic map (
+      g_clocks    => 2,                           -- 62.5MHz, 125MHz
+      g_logdelay  => 4,                           -- 16 clock cycles
+      g_syncdepth => 3)                           -- length of sync chains
+    port map (
+      free_clk_i => clk_125m_user,
+      locked_i   => rstlogic_arst_n,
+      clks_i     => rstlogic_clk_in,
+      rstn_o     => rstlogic_rst_out);
+
+  -- distribution of resets (already synchronized to their clock domains)
+  rst_62m5_n <= rstlogic_rst_out(0);
+
+  rst_sys_62m5_n_o <= rst_62m5_n;
+  rst_ref_125m_n_o <= rstlogic_rst_out(1);
+
+  -----------------------------------------------------------------------------
+  -- 2x SPI DAC
+  -----------------------------------------------------------------------------
+
+  cmp_dac_arb : spec_serial_dac_arb
+    generic map (
+      g_invert_sclk    => FALSE,
+      g_num_extra_bits => 8)
+    port map (
+      clk_i         => clk_pll_62m5,
+      rst_n_i       => rst_62m5_n,
+      val1_i        => dac_dpll_data,
+      load1_i       => dac_dpll_load_p1,
+      val2_i        => dac_hpll_data,
+      load2_i       => dac_hpll_load_p1,
+      dac_cs_n_o(0) => pll25dac_cs_n_o,
+      dac_cs_n_o(1) => pll20dac_cs_n_o,
+      dac_sclk_o    => plldac_sclk_o,
+      dac_din_o     => plldac_din_o);
+
+  -----------------------------------------------------------------------------
+  -- The WR PTP core with optional fabric interface attached
+  -----------------------------------------------------------------------------
+
+  cmp_board_common : xwrc_board_common
+    generic map (
+      g_simulation                => g_simulation,
+      g_with_external_clock_input => FALSE,
+      g_board_name                => "ZUSD",
+      g_phys_uart                 => TRUE,
+      g_virtual_uart              => TRUE,
+      g_aux_clks                  => g_aux_clks,
+      g_ep_rxbuf_size             => 1024,
+      g_tx_runt_padding           => TRUE,
+      g_dpram_initf               => g_dpram_initf,
+      g_dpram_size                => (131072)/4,
+      g_interface_mode            => PIPELINED,
+      g_address_granularity       => BYTE,
+      g_aux_sdb                   => c_wrc_periph3_sdb,
+      g_softpll_enable_debugger   => FALSE,
+      g_vuart_fifo_size           => 1024,
+      g_pcs_16bit                 => TRUE,
+      g_diag_id                   => g_diag_id,
+      g_diag_ver                  => g_diag_ver,
+      g_diag_ro_size              => g_diag_ro_size,
+      g_diag_rw_size              => g_diag_rw_size,
+      g_streamers_op_mode         => g_streamers_op_mode,
+      g_tx_streamer_params        => g_tx_streamer_params,
+      g_rx_streamer_params        => g_rx_streamer_params,
+      g_fabric_iface              => g_fabric_iface
+      )
+    port map (
+      clk_sys_i            => clk_pll_62m5,
+      clk_dmtd_i           => clk_pll_dmtd,
+      clk_ref_i            => phy16_to_wrc.ref_clk,
+      clk_aux_i            => clk_aux_i,
+      clk_10m_ext_i        => '0',
+      clk_ext_mul_i        => '0',
+      clk_ext_mul_locked_i => '0',
+      clk_ext_stopped_i    => '0',
+      clk_ext_rst_o        => open,
+      pps_ext_i            => pps_ext_i,
+      rst_n_i              => rst_62m5_n,
+      dac_hpll_load_p1_o   => dac_hpll_load_p1,
+      dac_hpll_data_o      => dac_hpll_data,
+      dac_dpll_load_p1_o   => dac_dpll_load_p1,
+      dac_dpll_data_o      => dac_dpll_data,
+      phy16_o              => phy16_from_wrc,
+      phy16_i              => phy16_to_wrc,
+      sfp_scl_o            => sfp_scl_t,
+      sfp_scl_i            => sfp_scl_i,
+      sfp_sda_o            => sfp_sda_t,
+      sfp_sda_i            => sfp_sda_i,
+      sfp_det_i            => sfp_det_i,
+      spi_sclk_o           => flash_sclk_o,
+      spi_ncs_o            => flash_ncs_o,
+      spi_mosi_o           => flash_mosi_o,
+      spi_miso_i           => flash_miso_i,
+      wb_slave_i           => wb_slave_in,
+      wb_slave_o           => wb_slave_out,
+      aux_master_o         => aux_master_o,
+      aux_master_i         => aux_master_i,
+      wrf_src_o            => wrf_src_o,
+      wrf_src_i            => wrf_src_i,
+      wrf_snk_o            => wrf_snk_o,
+      wrf_snk_i            => wrf_snk_i,
+      wrs_tx_data_i        => wrs_tx_data_i,
+      wrs_tx_valid_i       => wrs_tx_valid_i,
+      wrs_tx_dreq_o        => wrs_tx_dreq_o,
+      wrs_tx_last_i        => wrs_tx_last_i,
+      wrs_tx_flush_i       => wrs_tx_flush_i,
+      wrs_tx_cfg_i         => wrs_tx_cfg_i,
+      wrs_rx_first_o       => wrs_rx_first_o,
+      wrs_rx_last_o        => wrs_rx_last_o,
+      wrs_rx_data_o        => wrs_rx_data_o,
+      wrs_rx_valid_o       => wrs_rx_valid_o,
+      wrs_rx_dreq_i        => wrs_rx_dreq_i,
+      wrs_rx_cfg_i         => wrs_rx_cfg_i,
+      wb_eth_master_o      => wb_eth_master_o,
+      wb_eth_master_i      => wb_eth_master_i,
+      aux_diag_i           => aux_diag_i,
+      aux_diag_o           => aux_diag_o,
+      tm_dac_value_o       => tm_dac_value_o,
+      tm_dac_wr_o          => tm_dac_wr_o,
+      tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
+      tm_clk_aux_locked_o  => tm_clk_aux_locked_o,
+      timestamps_o         => timestamps_o,
+      timestamps_ack_i     => timestamps_ack_i,
+      abscal_txts_o        => abscal_txts_o,
+      abscal_rxts_o        => abscal_rxts_o,
+      fc_tx_pause_req_i    => fc_tx_pause_req_i,
+      fc_tx_pause_delay_i  => fc_tx_pause_delay_i,
+      fc_tx_pause_ready_o  => fc_tx_pause_ready_o,
+      tm_link_up_o         => tm_link_up_o,
+      tm_time_valid_o      => tm_time_valid_o,
+      tm_tai_o             => tm_tai_o,
+      tm_cycles_o          => tm_cycles_o,
+      led_act_o            => led_act,
+      led_link_o           => led_link,
+      pps_p_o              => pps_p_o,
+      pps_led_o            => pps_led,
+      link_ok_o            => link_ok_o,
+      uart_rxd_i => uart_rxd_i,
+      uart_txd_o => uart_txd_o
+
+      );
+
+  sfp_rate_select_o <= '1';
+
+  sfp_sda_o    <= '0';
+  sfp_scl_o    <= '0';
+
+  s00_axi_aclk_o <= clk_pll_62m5;
+
+  cmp_axi4lite_wbm: wb_axi4lite_bridge
+    port map (
+      clk_sys_i => clk_pll_62m5,
+      rst_n_i   => s00_axi_aresetn,
+
+      AWADDR  => s00_axi_awaddr, 
+      AWVALID => s00_axi_awvalid,
+      AWREADY => s00_axi_awready,
+      WDATA   => s00_axi_wdata,
+      WSTRB   => s00_axi_wstrb,
+      WVALID  => s00_axi_wvalid,
+      WREADY  => s00_axi_wready,
+      WLAST   => '0',
+      BRESP   => s00_axi_bresp,
+      BVALID  => s00_axi_bvalid,
+      BREADY  => s00_axi_bready,
+      ARADDR  => s00_axi_araddr,
+      ARVALID => s00_axi_arvalid,
+      ARREADY => s00_axi_arready,
+      RDATA   => s00_axi_rdata,
+      RRESP   => s00_axi_rresp,
+      RVALID  => s00_axi_rvalid,
+      RREADY  => s00_axi_rready,
+      RLAST   => s00_axi_rlast,
+
+      wb_adr  => wb_slave_in.adr,
+      wb_dat_m2s => wb_slave_in.dat,
+      wb_sel => wb_slave_in.sel,
+      wb_cyc => wb_slave_in.cyc,
+      wb_stb => wb_slave_in.stb,
+      wb_we  => wb_slave_in.we,
+
+      wb_dat_s2m => wb_slave_out.dat,
+      wb_err     => wb_slave_out.err,
+      wb_rty     => wb_slave_out.rty,
+      wb_ack     => wb_slave_out.ack,
+      wb_stall   => wb_slave_out.stall
+
+    );
+  
+
+  axi_int_o <= '0';
+  rst_62m5 <= not rst_62m5_n;
+
+ 
+  
+end architecture struct;
--- a/platform/xilinx/xwrc_platform_xilinx.vhd
+++ b/platform/xilinx/xwrc_platform_xilinx.vhd
@@ -153,12 +153,18 @@ architecture rtl of xwrc_platform_xilinx is
  signal clk_125m_pllref_buf : std_logic;
  signal clk_62m5_sys : std_logic;

+  attribute mark_debug : string;
+  attribute mark_debug of pll_locked_o : signal is "TRUE";
+  attribute mark_debug of pll_arst : signal is "TRUE";
+  
+  signal clk_125m_gth_gclk, clk_125m_gth_prebuf : std_logic;
+  
 begin  -- architecture rtl

  -----------------------------------------------------------------------------
  -- Check for unsupported features and/or misconfiguration
  -----------------------------------------------------------------------------
-  gen_unknown_fpga : if (g_fpga_family /= "spartan6" and g_fpga_family /= "kintex7" and g_fpga_family /= "artix7" and g_fpga_family /= "kintexultrascale") generate
+  gen_unknown_fpga : if (g_fpga_family /= "spartan6" and g_fpga_family /= "kintex7" and g_fpga_family /= "artix7" and g_fpga_family /= "kintexultrascale" and g_fpga_family /= "zynqultrascaleplus") generate
    assert FALSE
      report "Xilinx FPGA family [" & g_fpga_family & "] is not supported"
      severity ERROR;
@@ -596,7 +602,7 @@ begin  -- architecture rtl
      signal mmcm_sys_clk_fb : std_logic;

    begin
-      -- System PLL (100 MHz -> 62.5 MHz)
+      -- System PLL (125 MHz -> 62.5 MHz)
      cmp_sys_clk_pll : MMCME3_ADV
        generic map (
          BANDWIDTH            => "OPTIMIZED", -- Jitter programming (HIGH, LOW, OPTIMIZED)
@@ -727,6 +733,172 @@ begin  -- architecture rtl
    end generate gen_kintexultrascale_default_plls;


+    ---------------------------------------------------------------------------
+    -- Zynq Ultrascale+ PLLs
+    ---------------------------------------------------------------------------
+
+    gen_zynqultrascaleplus_default_plls : if (g_fpga_family = "zynqultrascaleplus") generate
+
+      signal clk_sys          : std_logic;
+      signal clk_sys_out      : std_logic;
+      signal clk_sys_fb       : std_logic;
+      signal pll_sys_locked   : std_logic;
+      signal clk_dmtd         : std_logic;
+      signal clk_dmtd_fb      : std_logic;
+      signal pll_dmtd_locked  : std_logic;
+      signal clk_20m_vcxo_buf : std_logic;
+      signal mmcm_sys_clk_fb_prebuf : std_logic;
+      signal mmcm_sys_clk_fb : std_logic;
+
+    begin
+      -- System PLL (100 MHz -> 62.5 MHz)
+      cmp_sys_clk_pll : MMCME4_ADV
+        generic map (
+          BANDWIDTH            => "OPTIMIZED", -- Jitter programming (HIGH, LOW, OPTIMIZED)
+          COMPENSATION         => "AUTO",      -- AUTO, BUF_IN, EXTERNAL, INTERNAL, ZHOLD
+          STARTUP_WAIT         => "FALSE",     -- Delays DONE until MMCM is locked (FALSE, TRUE)
+          CLKOUT4_CASCADE      => "FALSE",
+          -- CLKIN_PERIOD: Input clock period in ns units, ps resolution (i.e. 33.333 is 30 MHz).
+          CLKIN1_PERIOD        => 8.0,
+          CLKFBOUT_MULT_F      => 8.0,        -- Multiply value for all CLKOUT (2.000-64.000)
+          DIVCLK_DIVIDE        => 1,           -- Master division value (1-106)
+          CLKFBOUT_PHASE       => 0.0,         -- Phase offset in degrees of CLKFB (-360.000-360.000)
+          CLKFBOUT_USE_FINE_PS => "FALSE",
+          CLKOUT0_DIVIDE_F     => 16.0,         -- clk_sys: 100 MHz * 10 / 16 = 62.5 MHz
+          CLKOUT0_DUTY_CYCLE   => 0.5,
+          CLKOUT0_PHASE        => 0.0,
+          CLKOUT0_USE_FINE_PS  => "FALSE",
+
+          CLKOUT1_DIVIDE       => 8  ,    
+          CLKOUT1_DUTY_CYCLE   => 0.5,
+          CLKOUT1_PHASE        => 0.0,
+          CLKOUT1_USE_FINE_PS  => "FALSE"
+
+          )
+        port map (
+          -- Clock Inputs inputs: Clock inputs
+          CLKIN1       => clk_125m_pci_i,
+          CLKIN2       => '0',
+          -- Clock Outputs outputs: User configurable clock outputs
+          CLKOUT0      => clk_sys,
+          CLKOUT1 => clk_125m_gth_prebuf,
+          -- Feedback
+          CLKFBOUT     => mmcm_sys_clk_fb,
+          CLKFBIN      => mmcm_sys_clk_fb,
+          -- Status Ports outputs: MMCM status ports
+          LOCKED       => pll_sys_locked,
+          CDDCREQ      => '0',
+          -- Control Ports inputs: MMCM control ports
+          CLKINSEL     => '1',
+          PWRDWN       => '0',
+          RST          => pll_arst,
+          -- DRP Ports inputs: Dynamic reconfiguration ports
+          DADDR        => (others => '0'),
+          DCLK         => '0',
+          DEN          => '0',
+          DI           => (others => '0'),
+          DWE          => '0',
+          -- Dynamic Phase Shift Ports inputs: Ports used for dynamic phase shifting of the outputs
+          PSCLK        => '0',
+          PSEN         => '0',
+          PSINCDEC     => '0'
+          );
+
+      clk_125m_ref_o <= clk_sys_out;
+      
+--      clk_125m_ref_o <= clk_125m_gth_gclk;
+      
+      -- cmp_buf_mmcm_sys_fb : BUFG
+      --   port map (
+      --     I => mmcm_sys_clk_fb_prebuf,
+      --     O => mmcm_sys_clk_fb);
+
+      -- System PLL output clock buffer
+      cmp_clk_sys_buf_o : BUFG
+      port map (
+        I => clk_sys,
+        O => clk_sys_out);
+      -- System PLL output clock buffer
+      cmp_clk_gth_buf_o : BUFG
+      port map (
+        I => clk_125m_gth_prebuf,
+        O => clk_125m_gth_gclk);
+
+      clk_62m5_sys_o <= clk_sys_out;
+      clk_62m5_sys <= clk_sys_out;
+
+    -- fixme : no dmtd clock for the moment
+      pll_locked_o   <=                     pll_sys_locked;
+
+      -- DMTD PLL (20 MHz -> ~62,5 MHz)
+      cmp_dmtd_clk_pll : MMCME4_ADV
+        generic map (
+          BANDWIDTH            => "OPTIMIZED",
+          CLKOUT4_CASCADE      => "FALSE",
+          COMPENSATION         => "ZHOLD",
+          STARTUP_WAIT         => "FALSE",
+          DIVCLK_DIVIDE        => 1,
+          CLKFBOUT_MULT_F      => 50.000,    -- 20 MHz -> 1 GHz
+          CLKFBOUT_PHASE       => 0.000,
+          CLKFBOUT_USE_FINE_PS => "FALSE",
+          CLKOUT0_DIVIDE_F     => 16.000,    -- 1GHz/16 -> 62.5 MHz
+          CLKOUT0_PHASE        => 0.000,
+          CLKOUT0_DUTY_CYCLE   => 0.500,
+          CLKOUT0_USE_FINE_PS  => "FALSE",
+          CLKIN1_PERIOD        => 50.000,    -- 50ns for 20 MHz
+          REF_JITTER1          => 0.010)
+        port map (
+          -- Output clocks
+          CLKFBOUT     => clk_dmtd_fb,
+          CLKOUT0      => clk_dmtd,
+          -- Input clock control
+          CLKFBIN      => clk_dmtd_fb,
+          CLKIN1       => clk_20m_vcxo_buf,
+          CLKIN2       => '0',
+          -- Tied to always select the primary input clock
+          CLKINSEL     => '1',
+          CDDCREQ      => '0',
+          -- Ports for dynamic reconfiguration
+          DADDR        => (others => '0'),
+          DCLK         => '0',
+          DEN          => '0',
+          DI           => (others => '0'),
+          DO           => open,
+          DRDY         => open,
+          DWE          => '0',
+          -- Ports for dynamic phase shift
+          PSCLK        => '0',
+          PSEN         => '0',
+          PSINCDEC     => '0',
+          PSDONE       => open,
+          -- Other control and status signals
+          LOCKED       => pll_dmtd_locked,
+          CLKINSTOPPED => open,
+          CLKFBSTOPPED => open,
+          PWRDWN       => '0',
+          RST          => pll_arst);
+
+      -- DMTD PLL input clock buffer
+      cmp_clk_dmtd_buf_i : BUFG
+        port map (
+          O => clk_20m_vcxo_buf,
+          I => clk_20m_vcxo_i);
+
+      -- DMTD PLL output clock buffer
+      cmp_clk_dmtd_buf_o : BUFG
+        port map (
+          O => clk_62m5_dmtd_o,
+          I => clk_dmtd);
+
+      -- External 10MHz reference PLL for Kintex Ultrascale
+      gen_zynqultrascaleplus_ext_ref_plls : if (g_with_external_clock_input = TRUE) generate
+        assert false report "External clock inputs not supported yet for Zynq Ultrascale+ family" severity FAILURE;
+      end generate gen_zynqultrascaleplus_ext_ref_plls;
+
+    end generate gen_zynqultrascaleplus_default_plls;
+
+    
+    
    ---------------------------------------------------------------------------
    --   Artix7 PLLs
    ---------------------------------------------------------------------------
@@ -973,7 +1145,7 @@ begin  -- architecture rtl

    clk_62m5_sys_o  <= clk_62m5_sys_i;
    clk_62m5_dmtd_o <= clk_62m5_dmtd_i;
-    clk_125m_ref_o  <= clk_125m_ref_i;
+--    clk_125m_ref_o  <= clk_125m_ref_i;

    pll_locked_o     <= clk_sys_locked_i and clk_dmtd_locked_i;
    clk_ref_locked_o <= clk_ref_locked_i;
@@ -1142,6 +1314,60 @@ begin  -- architecture rtl

  end generate gen_phy_kintexultrascale;

+
+  ---------------------------------------------------------------------------
+  -- Zynq Ultrascale+ PHY
+  ---------------------------------------------------------------------------
+
+  gen_phy_zynqultrascaleplus : if (g_fpga_family = "zynqultrascaleplus") generate
+
+ 
+  begin
+    
+    cmp_gthe4 : entity work.wr_gthe4_phy_family7
+      generic map (
+        g_simulation => g_simulation,
+        g_use_gclk_as_refclk => true)
+      port map (
+        clk_gth_p_i    => clk_125m_gtp_p_i,
+        clk_gth_n_i    => clk_125m_gtp_n_i,
+        clk_gth_gclk_i => clk_125m_gth_gclk,
+        clk_freerun_i  => clk_62m5_sys,
+        tx_out_clk_o   => phy16_o.ref_clk,
+        tx_data_i      => phy16_i.tx_data,
+        tx_k_i         => phy16_i.tx_k,
+        tx_disparity_o => phy16_o.tx_disparity,
+        tx_enc_err_o   => phy16_o.tx_enc_err,
+        rx_rbclk_o     => phy16_o.rx_clk,
+        rx_data_o      => phy16_o.rx_data,
+        rx_k_o         => phy16_o.rx_k,
+        rx_enc_err_o   => phy16_o.rx_enc_err,
+        rx_bitslide_o  => phy16_o.rx_bitslide,
+        rst_i          => phy16_i.rst,
+
+        loopen_i       => phy16_i.loopen_vec,
+--        tx_prbs_sel_i  => phy16_i.tx_prbs_sel,
+        rdy_o          => phy16_o.rdy,
+        pad_txn_o => sfp_txn_o,
+        pad_txp_o => sfp_txp_o,
+        pad_rxn_i => sfp_rxn_i,
+        pad_rxp_i => sfp_rxp_i,
+        tx_locked_o   => open,
+        debug_i => x"0000");
+
+
+--  clk_125m_ref_o       <= clk_ref;
+    clk_ref_locked_o     <= '1'; --clk_ref_locked;
+--    phy16_o.ref_clk      <= clk_ref;
+    phy16_o.sfp_tx_fault <= sfp_tx_fault_i;
+    phy16_o.sfp_los      <= sfp_los_i;
+    sfp_tx_disable_o     <= phy16_i.sfp_tx_disable;
+
+    phy8_o <= c_dummy_phy8_to_wrc;
+
+  end generate gen_phy_zynqultrascaleplus;
+
+  
  ---------------------------------------------------------------------------
  --   Kintex7 PHY
  ---------------------------------------------------------------------------

--- a/top/zcu106_ref_design/bitstream.xdc
+++ b/top/zcu106_ref_design/bitstream.xdc
+# SPI Flash Programming
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]
+set_property CONFIG_MODE SPIx1 [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
+set_property CONFIG_VOLTAGE 2.5 [current_design]
+set_property CFGBVS VCCO [current_design]
+set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+
+
--- a/top/zcu106_ref_design/clock_reset_gen.vhd
+++ b/top/zcu106_ref_design/clock_reset_gen.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity clock_reset_gen is
+  port (
+    clk_i : in std_logic;
+    gpio_o : out std_logic_vector(7 downto 0)
+    );
+
+end entity;
+
+architecture rtl of clock_reset_gen is
+
+  signal cnt      : unsigned(23 downto 0);
+
+
+begin
+
+
+  process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      cnt <= cnt + 1;
+
+      case cnt(23 downto 21) is
+        when "000"  => gpio_o <= "10000000";
+        when "001"  => gpio_o <= "01000000";
+        when "010"  => gpio_o <= "00100000";
+        when "011"  => gpio_o <= "00010000";
+        when "100"  => gpio_o <= "00001000";
+        when "101"  => gpio_o <= "00000100";
+        when "110"  => gpio_o <= "00000010";
+        when others => gpio_o <= "00000001";
+      end case;
+    end if;
+  end process;
+
+
+end rtl;
--- a/top/zcu106_ref_design/clocks.xdc
+++ b/top/zcu106_ref_design/clocks.xdc
+#create_clock -period 8.000 -name clk_125m_pci -waveform {0.000 4.000} [get_pins ]
+#create_clock -period 8.000 -name clk_125m_gth -waveform {0.000 4.000} [get_ports clk_125m_gtp_p_i]
+#create_clock -period 16.000 -name clk_gtx_rx -waveform {0.000 8.000} [get_pins cmp_xwrc_board_sis8300ku/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/RXOUTCLK]
+#create_generated_clock -name clk_gtx_tx -source [get_pins cmp_xwrc_board_sis8300ku/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtp_dedicated_clk/O] -divide_by 2 [get_pins cmp_xwrc_board_sis8300ku/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/TXOUTCLK]
+
+#set_clock_groups -asynchronous -group [get_clocks clk_gtx_rx] -group [get_clocks [get_clocks -of_objects [get_pins cmp_xwrc_board_sis8300ku/cmp_xwrc_platform/gen_default_plls.gen_kintexultrascale_default_plls.cmp_dmtd_clk_pll/CLKOUT0]]]
+#set_clock_groups -asynchronous -group [get_clocks clk_gtx_tx] -group [get_clocks [get_clocks -of_objects [get_pins cmp_xwrc_board_sis8300ku/cmp_xwrc_platform/gen_default_plls.gen_kintexultrascale_default_plls.cmp_dmtd_clk_pll/CLKOUT0]]]
+#set_clock_groups -asynchronous -group [get_clocks clk_sys] -group [get_clocks clk_gtx_rx]
+
+
+
+
+set_property ASYNC_REG true [get_cells {sis8300ku_wr_ref_design_i/wrc_board_sis8300ku_0/U0/cmp_xwrc_board_sis8300ku/cmp_board_common/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/gen_straight.clk_i_d0_reg}]
+set_property ASYNC_REG true [get_cells {sis8300ku_wr_ref_design_i/wrc_board_sis8300ku_0/U0/cmp_xwrc_board_sis8300ku/cmp_board_common/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/gen_straight.clk_i_d3_reg}]
+set_property ASYNC_REG true [get_cells {sis8300ku_wr_ref_design_i/wrc_board_sis8300ku_0/U0/cmp_xwrc_board_sis8300ku/cmp_board_common/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_straight.clk_i_d0_reg}]
+set_property ASYNC_REG true [get_cells {sis8300ku_wr_ref_design_i/wrc_board_sis8300ku_0/U0/cmp_xwrc_board_sis8300ku/cmp_board_common/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_straight.clk_i_d3_reg}]
+create_clock -period 50.000 -name clk_20m_vcxo -waveform {0.000 25.000} [get_ports clk_20m_vcxo_i]
+create_clock -period 10.000 -name clk_mtca_p -waveform {0.000 5.000} [get_ports clk_mtca_p]
+create_clock -period 8.000 -name mgtclk1_224_p_i -waveform {0.000 4.000} [get_ports mgtclk1_224_p_i]
+set_clock_groups -asynchronous -group [get_clocks RXOUTCLK] -group [get_clocks clk_dmtd]
+set_clock_groups -asynchronous -group [get_clocks clk_ref_125m_o] -group [get_clocks clk_dmtd]
+set_false_path -from [get_clocks clk_dmtd] -to [get_clocks clk_sys]
+
+
+
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list sis8300ku_wr_ref_design_i/axi_pcie3_0/inst/pcie3_ip_i/U0/gt_top_i/phy_clk_i/PHY_USERCLK]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 8 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WSTRB[0]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WSTRB[1]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WSTRB[2]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WSTRB[3]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WSTRB[4]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WSTRB[5]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WSTRB[6]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WSTRB[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 3 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWSIZE[0]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWSIZE[1]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWSIZE[2]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 64 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[0]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[1]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[2]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[3]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[4]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[5]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[6]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[7]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[8]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[9]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[10]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[11]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[12]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[13]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[14]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[15]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[16]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[17]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[18]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[19]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[20]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[21]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[22]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[23]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[24]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[25]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[26]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[27]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[28]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[29]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[30]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[31]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[32]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[33]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[34]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[35]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[36]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[37]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[38]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[39]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[40]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[41]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[42]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[43]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[44]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[45]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[46]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[47]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[48]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[49]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[50]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[51]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[52]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[53]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[54]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[55]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[56]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[57]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[58]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[59]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[60]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[61]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[62]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WDATA[63]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 64 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[0]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[1]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[2]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[3]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[4]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[5]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[6]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[7]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[8]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[9]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[10]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[11]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[12]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[13]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[14]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[15]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[16]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[17]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[18]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[19]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[20]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[21]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[22]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[23]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[24]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[25]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[26]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[27]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[28]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[29]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[30]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[31]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[32]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[33]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[34]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[35]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[36]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[37]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[38]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[39]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[40]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[41]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[42]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[43]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[44]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[45]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[46]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[47]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[48]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[49]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[50]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[51]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[52]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[53]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[54]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[55]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[56]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[57]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[58]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[59]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[60]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[61]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[62]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RDATA[63]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 32 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[0]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[1]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[2]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[3]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[4]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[5]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[6]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[7]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[8]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[9]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[10]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[11]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[12]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[13]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[14]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[15]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[16]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[17]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[18]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[19]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[20]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[21]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[22]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[23]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[24]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[25]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[26]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[27]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[28]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[29]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[30]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWADDR[31]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 3 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_BID[0]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_BID[1]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_BID[2]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 32 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[0]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[1]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[2]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[3]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[4]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[5]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[6]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[7]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[8]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[9]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[10]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[11]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[12]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[13]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[14]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[15]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[16]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[17]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[18]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[19]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[20]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[21]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[22]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[23]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[24]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[25]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[26]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[27]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[28]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[29]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[30]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARADDR[31]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+set_property port_width 3 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWPROT[0]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWPROT[1]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWPROT[2]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+set_property port_width 2 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_BRESP[0]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_BRESP[1]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+set_property port_width 3 [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RID[0]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RID[1]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RID[2]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+set_property port_width 8 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARLEN[0]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARLEN[1]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARLEN[2]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARLEN[3]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARLEN[4]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARLEN[5]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARLEN[6]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARLEN[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+set_property port_width 2 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARSIZE[0]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARSIZE[1]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+set_property port_width 1 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARPROT[1]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+set_property port_width 8 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWLEN[0]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWLEN[1]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWLEN[2]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWLEN[3]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWLEN[4]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWLEN[5]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWLEN[6]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWLEN[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
+set_property port_width 2 [get_debug_ports u_ila_0/probe14]
+connect_debug_port u_ila_0/probe14 [get_nets [list {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RRESP[0]} {sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RRESP[1]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
+set_property port_width 1 [get_debug_ports u_ila_0/probe15]
+connect_debug_port u_ila_0/probe15 [get_nets [list sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARREADY]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
+set_property port_width 1 [get_debug_ports u_ila_0/probe16]
+connect_debug_port u_ila_0/probe16 [get_nets [list sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_ARVALID]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
+set_property port_width 1 [get_debug_ports u_ila_0/probe17]
+connect_debug_port u_ila_0/probe17 [get_nets [list sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWREADY]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
+set_property port_width 1 [get_debug_ports u_ila_0/probe18]
+connect_debug_port u_ila_0/probe18 [get_nets [list sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_AWVALID]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
+set_property port_width 1 [get_debug_ports u_ila_0/probe19]
+connect_debug_port u_ila_0/probe19 [get_nets [list sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_BREADY]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
+set_property port_width 1 [get_debug_ports u_ila_0/probe20]
+connect_debug_port u_ila_0/probe20 [get_nets [list sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_BVALID]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
+set_property port_width 1 [get_debug_ports u_ila_0/probe21]
+connect_debug_port u_ila_0/probe21 [get_nets [list sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RLAST]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
+set_property port_width 1 [get_debug_ports u_ila_0/probe22]
+connect_debug_port u_ila_0/probe22 [get_nets [list sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RREADY]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
+set_property port_width 1 [get_debug_ports u_ila_0/probe23]
+connect_debug_port u_ila_0/probe23 [get_nets [list sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_RVALID]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
+set_property port_width 1 [get_debug_ports u_ila_0/probe24]
+connect_debug_port u_ila_0/probe24 [get_nets [list sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WLAST]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
+set_property port_width 1 [get_debug_ports u_ila_0/probe25]
+connect_debug_port u_ila_0/probe25 [get_nets [list sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WREADY]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
+set_property port_width 1 [get_debug_ports u_ila_0/probe26]
+connect_debug_port u_ila_0/probe26 [get_nets [list sis8300ku_wr_ref_design_i/axi_interconnect_0/axi_interconnect_0_to_s00_couplers_WVALID]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets u_ila_0_PHY_USERCLK]