platform/xilinx: output clk_ext after BUFG for WRPC

f34a7968 · Grzegorz Daniluk · 621486b8 · f34a7968 · f34a7968
Commit f34a7968 authored Feb 21, 2017 by Grzegorz Daniluk
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Showing with 7 additions and 3 deletions

wr_xilinx_pkg.vhd platform/xilinx/wr_xilinx_pkg.vhd +1 -0

xwrc_platform_xilinx.vhd platform/xilinx/xwrc_platform_xilinx.vhd +6 -3

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--- a/platform/xilinx/wr_xilinx_pkg.vhd
+++ b/platform/xilinx/wr_xilinx_pkg.vhd
@@ -39,6 +39,7 @@ package wr_xilinx_pkg is
      clk_125m_ref_o        : out std_logic;
      clk_62m5_dmtd_o       : out std_logic;
      pll_locked_o          : out std_logic;
+      clk_10m_ext_o         : out std_logic;
      phy8_o                : out t_phy_8bits_to_wrc;
      phy8_i                : in  t_phy_8bits_from_wrc  := c_dummy_phy8_from_wrc;
      phy16_o               : out t_phy_16bits_to_wrc;

--- a/platform/xilinx/xwrc_platform_xilinx.vhd
+++ b/platform/xilinx/xwrc_platform_xilinx.vhd
@@ -119,6 +119,7 @@ entity xwrc_platform_xilinx is
    clk_125m_ref_o        : out std_logic;
    clk_62m5_dmtd_o       : out std_logic;
    pll_locked_o          : out std_logic;
+    clk_10m_ext_o         : out std_logic;
    -- PHY
    phy8_o                : out t_phy_8bits_to_wrc;
    phy8_i                : in  t_phy_8bits_from_wrc  := c_dummy_phy8_from_wrc;
@@ -261,7 +262,7 @@ begin  -- architecture rtl

        signal clk_ext_fbi  : std_logic;
        signal clk_ext_fbo  : std_logic;
-        signal clk_ext_in   : std_logic;
+        signal clk_ext_buf  : std_logic;
        signal clk_ext      : std_logic;
        signal clk_ext_stat : std_logic_vector(7 downto 0);
        signal pll_ext_rst  : std_logic;
@@ -283,7 +284,7 @@ begin  -- architecture rtl
           STARTUP_WAIT       => FALSE)
          port map
          -- Input clock
-          (CLKIN    => clk_ext_in,
+          (CLKIN    => clk_ext_buf,
           CLKFB    => clk_ext_fbi,
           -- Output clocks
           CLK0     => clk_ext_fbo,
@@ -305,9 +306,11 @@ begin  -- architecture rtl
        -- External reference input buffer
        cmp_clk_ext_buf_i : BUFG
          port map
-          (O => clk_ext_in,
+          (O => clk_ext_buf,
           I => clk_10m_ext_i);

+        clk_10m_ext_o <= clk_ext_buf;
+
        -- External reference feedback buffer
        cmp_clk_ext_buf_fb : BUFG
          port map