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White Rabbit core collection
Commit f267c217 authored by Maciej Lipinski's avatar Maciej Lipinski
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[streamers] update wrappers used in simulation to match the newest 

rx/tx streamers generics/ports
parent e4fd8b63
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Showing with 52 additions and 58 deletions
modules/wr_streamers/rx_streamer.vhd
View file @ f267c217
......@@ -6,13 +6,15 @@ use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.streamers_pkg.all;
entity rx_streamer is
generic (
g_data_width : integer := 32;
g_buffer_size : integer := 128;
g_filter_remote_mac : boolean := false
g_data_width : integer := 32;
g_buffer_size : integer := 128;
g_escape_code_disable : boolean := FALSE;
g_expected_words_number : integer := 0
);
port (
......@@ -36,63 +38,43 @@ entity rx_streamer is
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
rx_first_p1_o : out std_logic;
rx_last_p1_o : out std_logic;
rx_data_o : out std_logic_vector(g_data_width-1 downto 0);
rx_valid_o : out std_logic;
rx_dreq_i : in std_logic;
rx_lost_p1_o : out std_logic := '0';
rx_latency_o : out std_logic_vector(27 downto 0);
rx_latency_valid_o : out std_logic;
rx_first_p1_o : out std_logic;
rx_last_p1_o : out std_logic;
rx_data_o : out std_logic_vector(g_data_width-1 downto 0);
rx_valid_o : out std_logic;
rx_dreq_i : in std_logic;
rx_lost_p1_o : out std_logic := '0';
rx_lost_blocks_p1_o : out std_logic := '0';
rx_lost_frames_p1_o : out std_logic := '0';
rx_lost_frames_cnt_o : out std_logic_vector(14 downto 0);
rx_latency_o : out std_logic_vector(27 downto 0);
rx_latency_valid_o : out std_logic;
rx_frame_p1_o : out std_logic;
cfg_mac_local_i : in std_logic_vector(47 downto 0);
cfg_mac_remote_i : in std_logic_vector(47 downto 0);
cfg_ethertype_i : in std_logic_vector(15 downto 0) := x"dbff";
cfg_accept_broadcasts_i : in std_logic := '1'
cfg_accept_broadcasts_i : in std_logic := '1';
cfg_filter_remote_i : in std_logic := '0';
cfg_fixed_latency_i : in std_logic_vector(27 downto 0) := x"0000000"
);
end rx_streamer;
architecture wrapper of rx_streamer is
component xrx_streamer
generic (
g_data_width : integer;
g_buffer_size : integer;
g_filter_remote_mac : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
clk_ref_i : in std_logic := '0';
tm_time_valid_i : in std_logic := '0';
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
rx_first_p1_o : out std_logic;
rx_last_p1_o : out std_logic;
rx_data_o : out std_logic_vector(g_data_width-1 downto 0);
rx_valid_o : out std_logic;
rx_dreq_i : in std_logic;
rx_lost_p1_o : out std_logic := '0';
rx_latency_o : out std_logic_vector(27 downto 0);
rx_latency_valid_o : out std_logic;
cfg_mac_local_i : in std_logic_vector(47 downto 0);
cfg_mac_remote_i : in std_logic_vector(47 downto 0);
cfg_ethertype_i : in std_logic_vector(15 downto 0) := x"dbff";
cfg_accept_broadcasts_i : in std_logic := '1');
end component;
signal snk_in : t_wrf_sink_in;
signal snk_out : t_wrf_sink_out;
begin -- rtl
U_Wrapped_Streamer : xrx_streamer
generic map (
g_data_width => g_data_width,
g_filter_remote_mac => g_filter_remote_mac,
g_buffer_size => g_buffer_size)
g_data_width => g_data_width,
g_buffer_size => g_buffer_size,
g_escape_code_disable => g_escape_code_disable,
g_expected_words_number => g_expected_words_number)
port map (
clk_sys_i => clk_sys_i,
clk_ref_i => clk_ref_i,
......@@ -102,18 +84,24 @@ begin -- rtl
rst_n_i => rst_n_i,
snk_i => snk_in,
snk_o => snk_out,
rx_first_p1_o => rx_first_p1_o,
rx_last_p1_o => rx_last_p1_o,
rx_data_o => rx_data_o,
rx_valid_o => rx_valid_o,
rx_dreq_i => rx_dreq_i,
rx_lost_p1_o => rx_lost_p1_o,
rx_first_p1_o => rx_first_p1_o,
rx_last_p1_o => rx_last_p1_o,
rx_lost_blocks_p1_o => rx_lost_blocks_p1_o,
rx_lost_frames_p1_o => rx_lost_frames_p1_o,
rx_lost_frames_cnt_o => rx_lost_frames_cnt_o,
rx_latency_valid_o => rx_latency_valid_o,
rx_latency_o => rx_latency_o,
rx_frame_p1_o => rx_frame_p1_o,
cfg_mac_local_i => cfg_mac_local_i,
cfg_mac_remote_i => cfg_mac_remote_i,
cfg_ethertype_i => cfg_ethertype_i,
cfg_accept_broadcasts_i => cfg_accept_broadcasts_i);
cfg_accept_broadcasts_i => cfg_accept_broadcasts_i,
cfg_filter_remote_i => cfg_filter_remote_i,
cfg_fixed_latency_i => cfg_fixed_latency_i);
snk_in.dat <= snk_dat_i;
snk_in.adr <= snk_adr_i;
......@@ -126,5 +114,4 @@ begin -- rtl
snk_err_o <= snk_out.err;
snk_rty_o <= snk_out.rty;
end wrapper;
modules/wr_streamers/tx_streamer.vhd
View file @ f267c217
......@@ -14,7 +14,8 @@ entity tx_streamer is
g_data_width : integer := 32;
g_tx_threshold : integer := 16;
g_tx_max_words_per_frame : integer := 128;
g_tx_timeout : integer := 1024
g_tx_timeout : integer := 1024;
g_escape_code_disable : boolean := FALSE
);
port (
......@@ -37,12 +38,13 @@ entity tx_streamer is
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
tx_flush_p1_i : in std_logic := '0';
tx_last_p1_i : in std_logic := '1';
tx_data_i : in std_logic_vector(g_data_width-1 downto 0);
tx_reset_seq_i : in std_logic := '0';
tx_valid_i : in std_logic;
tx_dreq_o : out std_logic;
tx_last_p1_i : in std_logic := '1';
tx_flush_p1_i : in std_logic := '0';
tx_reset_seq_i : in std_logic := '0';
tx_frame_p1_o : out std_logic;
-- MAC address
cfg_mac_local_i : in std_logic_vector(47 downto 0) := x"000000000000";
......@@ -64,22 +66,27 @@ begin -- rtl
g_data_width => g_data_width,
g_tx_threshold => g_tx_threshold,
g_tx_max_words_per_frame => g_tx_max_words_per_frame,
g_tx_timeout => g_tx_timeout)
g_tx_timeout => g_tx_timeout,
g_escape_code_disable => g_escape_code_disable)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
src_i => src_in,
src_o => src_out,
tx_last_p1_i => tx_last_p1_i,
tx_data_i => tx_data_i,
tx_reset_seq_i => tx_reset_seq_i,
tx_valid_i => tx_valid_i,
tx_dreq_o => tx_dreq_o,
tx_flush_p1_i => tx_flush_p1_i,
clk_ref_i => clk_ref_i,
tm_time_valid_i => tm_time_valid_i,
tm_tai_i => tm_tai_i,
tm_cycles_i => tm_cycles_i,
tx_data_i => tx_data_i,
tx_valid_i => tx_valid_i,
tx_dreq_o => tx_dreq_o,
tx_last_p1_i => tx_last_p1_i,
tx_flush_p1_i => tx_flush_p1_i,
tx_reset_seq_i => tx_reset_seq_i,
tx_frame_p1_o => tx_frame_p1_o,
cfg_mac_local_i => cfg_mac_local_i,
cfg_mac_target_i => cfg_mac_target_i,
cfg_ethertype_i => cfg_ethertype_i);
......
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