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White Rabbit core collection
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White Rabbit core collection
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eac0e30a
Commit
eac0e30a
authored
Sep 09, 2020
by
Nayib Boukadida
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Splitted the tx_timestamp signal in two clock domains; refclk for phys output, sysclk for lm32
parent
cba31e06
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17 additions
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4 deletions
+17
-4
ep_timestamping_unit.vhd
modules/wr_endpoint/ep_timestamping_unit.vhd
+17
-4
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modules/wr_endpoint/ep_timestamping_unit.vhd
View file @
eac0e30a
...
...
@@ -167,8 +167,9 @@ architecture syn of ep_timestamping_unit is
signal
tx_sync_delay
:
std_logic_vector
(
4
downto
0
);
signal
rx_sync_delay
:
std_logic_vector
(
4
downto
0
);
signal
rx_ts_done
:
std_logic
;
signal
tx_ts_done
:
std_logic
;
signal
rx_ts_done
:
std_logic
;
signal
tx_ts_done
:
std_logic
;
signal
txts
:
std_logic
;
signal
got_tx_oob
:
std_logic
;
signal
tx_oob_reg
:
std_logic_vector
(
15
downto
0
);
...
...
@@ -361,6 +362,18 @@ begin -- syn
-- timestamping "done" signals sync chains (clk_ref -> clk_sys)
tx_done_gen
:
gc_sync_ffs
generic
map
(
g_sync_edge
=>
"positive"
)
port
map
(
clk_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_sys_i
,
data_i
=>
tx_sync_delay
(
0
),
synced_o
=>
open
,
npulse_o
=>
tx_ts_done
,
ppulse_o
=>
open
);
-- timestamping "out" signals sync chains (clk_ref -> clk_ref)
tx_out_gen
:
gc_sync_ffs
generic
map
(
g_sync_edge
=>
"positive"
)
port
map
(
...
...
@@ -368,7 +381,7 @@ begin -- syn
rst_n_i
=>
rst_n_ref_i
,
data_i
=>
tx_sync_delay
(
0
),
synced_o
=>
open
,
npulse_o
=>
tx
_ts_done
,
npulse_o
=>
tx
ts
,
ppulse_o
=>
open
);
-- timestamping "done" signals sync chains (clk_rx -> clk_sys)
...
...
@@ -383,7 +396,7 @@ begin -- syn
npulse_o
=>
rx_ts_done
,
ppulse_o
=>
open
);
txts_o
<=
tx
_ts_done
;
-- 2013-Nov-28 peterj added for debugging/calibration
txts_o
<=
tx
ts
;
-- 2013-Nov-28 peterj added for debugging/calibration
rxts_o
<=
rx_ts_done
;
-- 2013-Nov-28 peterj added for debugging/calibration
p_output_rx_ts
:
process
(
clk_rx_i
)
...
...
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