Skip to content

W
White Rabbit core collection
Commit db907e76 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

wr_gthe3_phy_family7: reset RX PCS after link loss to ensure reset of the bitslide counter

parent 0d7bcaac
Pipeline #277 failed with stages
      in 10 seconds
      Hide whitespace changes
      Inline Side-by-side
      Showing with 18 additions and 6 deletions
      platform/xilinx/wr_gtp_phy/family7-gthe3/wr_gthe3_phy_family7.vhd
      View file @ db907e76
      ...@@ -191,7 +191,8 @@ architecture rtl of wr_gthe3_phy_family7 is ...@@ -191,7 +191,8 @@ architecture rtl of wr_gthe3_phy_family7 is
      attribute mark_debug of RXPMARESETDONE : signal is "TRUE"; attribute mark_debug of RXPMARESETDONE : signal is "TRUE";
      attribute mark_debug of serdes_ready : signal is "TRUE"; attribute mark_debug of serdes_ready : signal is "TRUE";
      signal rx_pcs_reset : std_logic;
      begin begin
      ...@@ -212,7 +213,7 @@ begin ...@@ -212,7 +213,7 @@ begin
      U_Bitslide : entity work.gtp_bitslide U_Bitslide : entity work.gtp_bitslide
      generic map ( generic map (
      g_simulation => g_simulation, g_simulation => g_simulation,
      g_target => "virtex6") g_target => "ultrascale")
      port map ( port map (
      gtp_rst_i => rst_i, gtp_rst_i => rst_i,
      gtp_rx_clk_i => RXUSRCLK2, gtp_rx_clk_i => RXUSRCLK2,
      ...@@ -220,7 +221,7 @@ begin ...@@ -220,7 +221,7 @@ begin
      gtp_rx_byte_is_aligned_i => RXBYTEISALIGNED, gtp_rx_byte_is_aligned_i => RXBYTEISALIGNED,
      serdes_ready_i => serdes_ready_rxusrclk, serdes_ready_i => serdes_ready_rxusrclk,
      gtp_rx_slide_o => RXSLIDE, gtp_rx_slide_o => RXSLIDE,
      gtp_rx_cdr_rst_o => open, gtp_rx_cdr_rst_o => rx_pcs_reset,
      bitslide_o => rx_bitslide_o, bitslide_o => rx_bitslide_o,
      synced_o => rx_synced); synced_o => rx_synced);
      ...@@ -367,6 +368,7 @@ begin ...@@ -367,6 +368,7 @@ begin
      RXBYTEISALIGNED => RXBYTEISALIGNED, RXBYTEISALIGNED => RXBYTEISALIGNED,
      RXCOMMADET => RXCOMMADET, RXCOMMADET => RXCOMMADET,
      RXCTRL0 => RXCTRL0, RXCTRL0 => RXCTRL0,
      RXPCSRESET => rx_pcs_reset,
      rxctrl3 => rxctrl3, rxctrl3 => rxctrl3,
      RXDATA => RXDATA, RXDATA => RXDATA,
      RXOUTCLK => RXOUTCLK, RXOUTCLK => RXOUTCLK,
      ......
      platform/xilinx/wr_gtp_phy/family7-gthe3/wr_gthe3_wrapper.vhd
      View file @ db907e76
      ...@@ -15,6 +15,8 @@ entity wr_gthe3_wrapper is ...@@ -15,6 +15,8 @@ entity wr_gthe3_wrapper is
      TXRESETDONE : out std_logic; TXRESETDONE : out std_logic;
      TXPROGDIVRESET : in std_logic; TXPROGDIVRESET : in std_logic;
      RXPCSRESET : in std_logic;
      GTHTXN : out std_logic; GTHTXN : out std_logic;
      GTHTXP : out std_logic; GTHTXP : out std_logic;
      ...@@ -1404,7 +1406,7 @@ begin ...@@ -1404,7 +1406,7 @@ begin
      RXOSOVRDEN => '0', RXOSOVRDEN => '0',
      RXOUTCLKSEL => "010", RXOUTCLKSEL => "010",
      RXPCOMMAALIGNEN => '0', RXPCOMMAALIGNEN => '0',
      RXPCSRESET => '0', RXPCSRESET => RXPCSRESET,
      RXPD => "00", RXPD => "00",
      RXPHALIGN => '0', RXPHALIGN => '0',
      RXPHALIGNEN => '0', RXPHALIGNEN => '0',
      ......
      platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
      View file @ db907e76
      ...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
      -- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
      -- Company : CERN BE-CO-HT -- Company : CERN BE-CO-HT
      -- Created : 2010-11-18 -- Created : 2010-11-18
      -- Last update: 2013-12-20 -- Last update: 2020-07-03
      -- Platform : FPGA-generic -- Platform : FPGA-generic
      -- Standard : VHDL'93 -- Standard : VHDL'93
      ------------------------------------------------------------------------------- -------------------------------------------------------------------------------
      ...@@ -201,7 +201,15 @@ begin -- behavioral ...@@ -201,7 +201,15 @@ begin -- behavioral
      when S_PAUSE => when S_PAUSE =>
      counter <= counter + 1; counter <= counter + 1;
      gtp_rx_slide_o <= '0'; if g_target = "ultrascale" then
      if counter = 1 then
      gtp_rx_slide_o <= '0'; -- ultrascale requires 2 RXUSRCLK2 ticks
      -- for slide pulse
      end if;
      else
      gtp_rx_slide_o <= '0';
      end if;
      if(counter = to_unsigned(c_pause_tics, counter'length)) then if(counter = to_unsigned(c_pause_tics, counter'length)) then
      ......
      Markdown is supported
      0% or
      You are about to add 0 people to the discussion. Proceed with caution.
      Finish editing this message first!
      Please register or to comment