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Commit d5952890 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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platform/xilinx/wr_gtp_phy: added Vivado-generated wrapper files for GTHE3

parent 28191b5a
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    platform/xilinx/wr_gtp_phy/Manifest.py
    View file @ d5952890
    ......@@ -2,6 +2,55 @@ files = [
    "gtp_bitslide.vhd",
    ];
    xilinx_ip_gthe3 = [
    "xilinx-ip/gthe3/gtwizard_ultrascale_v1_6_gthe3_channel.v",
    "xilinx-ip/gthe3/wr_gth_wrapper_gthe3_channel_wrapper.v",
    "xilinx-ip/gthe3/wr_gth_wrapper_example_wrapper.v",
    "xilinx-ip/gthe3/wr_gth_wrapper_example_bit_sync.v",
    "xilinx-ip/gthe3/wr_gth_wrapper_example_wrapper_functions.v",
    "xilinx-ip/gthe3/wr_gth_wrapper.v",
    "xilinx-ip/gthe3/wr_gth_wrapper_gtwizard_top.v",
    "xilinx-ip/gthe3/wr_gth_wrapper_example_top.v",
    "xilinx-ip/gthe3/wr_gth_wrapper_gtwizard_gthe3.v",
    "xilinx-ip/gthe3/wr_gth_wrapper_example_reset_sync.v",
    "xilinx-ip/gthe3/wr_gth_wrapper_example_gtwiz_userclk_tx.v",
    "xilinx-ip/gthe3/wr_gth_wrapper_example_init.v",
    "xilinx-ip/gthe3/wr_gth_wrapper_example_gtwiz_userclk_rx.v"
    ];
    xilinx_ip_gthe4 = [
    "xilinx-ip/gthe4/gtwizard_ultrascale_2.v",
    "xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_top.v",
    "xilinx-ip/gthe4/gtwizard_ultrascale_2.xdc",
    "xilinx-ip/gthe4/gtwizard_ultrascale_2_gthe4_channel_wrapper.v",
    "xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_gthe4.v",
    "xilinx-ip/gthe4/gtwizard_ultrascale_2_ooc.xdc",
    "xilinx-ip/gthe4/gtwizard_ultrascale_v1_7_gthe4_channel.v"
    ];
    xilinx_ip_common = [
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_bit_sync.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_reset.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gte4_drp_arb.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_reset_inv_sync.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_reset_sync.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v"
    ];
    if (syn_device[0:4].upper()=="XC6S"): # Spartan6
    files.extend(["spartan6/wr_gtp_phy_spartan6.vhd",
    "spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd",
    ......@@ -49,7 +98,9 @@ elif (syn_device[0:4].upper()=="XCKU"): # Kintex Ultrascale GTH
    "family7-gthe3/wr_gthe3_rx_buffer_bypass.vhd",
    "family7-gthe3/wr_gthe3_tx_buffer_bypass.vhd",
    "family7-gthe3/wr_gthe3_wrapper.vhd",
    "family7-gthe3/gc_reset_synchronizer.vhd" ]);
    "family7-gthe3/gc_reset_synchronizer.vhd" ])
    files.extend( xilinx_ip_gthe3 );
    files.extend( xilinx_ip_common );
    elif (syn_device[0:4].upper()=="XCZU"): # Zynq Ultrascale GTH
    files.extend(["family7-gthe4/wr_gthe4_phy_family7.vhd",
    "family7-gthe4/wr_gthe4_phy_family7_xilinx_ip.vhd",
    ......@@ -58,27 +109,6 @@ elif (syn_device[0:4].upper()=="XCZU"): # Zynq Ultrascale GTH
    "family7-gthe4/wr_gthe4_tx_buffer_bypass.vhd",
    "family7-gthe4/wr_gthe4_wrapper.vhd",
    "family7-gthe4/gc_reset_synchronizer.vhd",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_bit_sync.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_reset.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gte4_drp_arb.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_reset_inv_sync.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_reset_sync.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v",
    "family7-gthe4/gthe4/synth/gtwizard_ultrascale_2.v",
    "family7-gthe4/gthe4/synth/gtwizard_ultrascale_2_gtwizard_top.v",
    "family7-gthe4/gthe4/synth/gtwizard_ultrascale_2_gthe4_channel_wrapper.v",
    "family7-gthe4/gthe4/synth/gtwizard_ultrascale_2_gtwizard_gthe4.v",
    "family7-gthe4/gthe4/synth/gtwizard_ultrascale_v1_7_gthe4_channel.v"
    ]);
    files.extend( xilinx_ip_gthe4 );
    files.extend( xilinx_ip_common );
    platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/Manifest.py deleted 100644 → 0
    View file @ 28191b5a
    files = ["common/gtwizard_ultrascale_v1_7_bit_sync.v",
    "common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v",
    "common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v",
    "common/gtwizard_ultrascale_v1_7_gtwiz_reset.v",
    "common/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v",
    "common/gtwizard_ultrascale_v1_7_gte4_drp_arb.v",
    "common/gtwizard_ultrascale_v1_7_reset_inv_sync.v",
    "common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v",
    "common/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v",
    "common/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v",
    "common/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v",
    "common/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v",
    "common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v",
    "common/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v",
    "common/gtwizard_ultrascale_v1_7_reset_sync.v",
    "common/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v",
    "common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v",
    "common/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v",
    "synth/gtwizard_ultrascale_2.v",
    "synth/gtwizard_ultrascale_2_gtwizard_top.v",
    "synth/gtwizard_ultrascale_2_gthe4_channel_wrapper.v",
    "synth/gtwizard_ultrascale_2_gtwizard_gthe4.v",
    "synth/gtwizard_ultrascale_v1_7_gthe4_channel.v"];
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/gtwizard_ultrascale_v1_6_gthe3_channel.v 0 → 100755
    View file @ d5952890
    This source diff could not be displayed because it is too large. You can view the blob instead.
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper.v 0 → 100644
    View file @ d5952890
    // (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
    //
    // This file contains confidential and proprietary information
    // of Xilinx, Inc. and is protected under U.S. and
    // international copyright and other intellectual property
    // laws.
    //
    // DISCLAIMER
    // This disclaimer is not a license and does not grant any
    // rights to the materials distributed herewith. Except as
    // otherwise provided in a valid license issued to you by
    // Xilinx, and to the maximum extent permitted by applicable
    // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
    // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
    // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
    // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
    // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
    // (2) Xilinx shall not be liable (whether in contract or tort,
    // including negligence, or under any other theory of
    // liability) for any loss or damage of any kind or nature
    // related to, arising under or in connection with these
    // materials, including for any direct, or any indirect,
    // special, incidental, or consequential loss or damage
    // (including loss of data, profits, goodwill, or any type of
    // loss or damage suffered as a result of any action brought
    // by a third party) even if such damage or loss was
    // reasonably foreseeable or Xilinx had been advised of the
    // possibility of the same.
    //
    // CRITICAL APPLICATIONS
    // Xilinx products are not designed or intended to be fail-
    // safe, or for use in any application requiring fail-safe
    // performance, such as life-support or safety devices or
    // systems, Class III medical devices, nuclear facilities,
    // applications related to the deployment of airbags, or any
    // other applications that could lead to death, personal
    // injury, or severe property or environmental damage
    // (individually and collectively, "Critical
    // Applications"). Customer assumes the sole risk and
    // liability of any use of Xilinx products in Critical
    // Applications, subject only to applicable laws and
    // regulations governing limitations on product liability.
    //
    // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
    // PART OF THIS FILE AT ALL TIMES.
    //
    // DO NOT MODIFY THIS FILE.
    // IP VLNV: xilinx.com:ip:gtwizard_ultrascale:1.6
    // IP Revision: 5
    (* X_CORE_INFO = "wr_gth_wrapper_gtwizard_top,Vivado 2016.4" *)
    (* CHECK_LICENSE_TYPE = "wr_gth_wrapper,wr_gth_wrapper_gtwizard_top,{}" *)
    (* CORE_GENERATION_INFO = "wr_gth_wrapper,wr_gth_wrapper_gtwizard_top,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=gtwizard_ultrascale,x_ipVersion=1.6,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_CHANNEL_ENABLE=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000,C_PCIE_ENABLE=0,C_PCIE_CORECLK_FREQ=250,C_COMMON_SCALING_FACTOR=1,C_CPLL_VCO\
    _FREQUENCY=2500.0,C_FORCE_COMMONS=0,C_FREERUN_FREQUENCY=62.5,C_GT_TYPE=0,C_GT_REV=17,C_INCLUDE_CPLL_CAL=2,C_SIM_CPLL_CAL_BYPASS=0,C_LOCATE_COMMON=0,C_LOCATE_RESET_CONTROLLER=0,C_LOCATE_USER_DATA_WIDTH_SIZING=0,C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER=0,C_LOCATE_IN_SYSTEM_IBERT_CORE=2,C_LOCATE_RX_USER_CLOCKING=1,C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER=0,C_LOCATE_TX_USER_CLOCKING=1,C_RESET_CONTROLLER_INSTANCE_CTRL=0,C_RX_BUFFBYPASS_MODE=0,C_RX_BUFFER_BYPASS_INSTANCE_CTRL=0,C_RX_BUFFER_MODE=0,C_RX_CB_DISP\
    =00000000,C_RX_CB_K=00000000,C_RX_CB_MAX_LEVEL=1,C_RX_CB_LEN_SEQ=1,C_RX_CB_NUM_SEQ=0,C_RX_CB_VAL=00000000000000000000000000000000000000000000000000000000000000000000000000000000,C_RX_CC_DISP=00000000,C_RX_CC_ENABLE=0,C_RESET_SEQUENCE_INTERVAL=0,C_RX_CC_K=00000000,C_RX_CC_LEN_SEQ=1,C_RX_CC_NUM_SEQ=0,C_RX_CC_PERIODICITY=5000,C_RX_CC_VAL=00000000000000000000000000000000000000000000000000000000000000000000000000000000,C_RX_COMMA_M_ENABLE=1,C_RX_COMMA_M_VAL=1010000011,C_RX_COMMA_P_ENABLE=1,C_RX_COMMA\
    _P_VAL=0101111100,C_RX_DATA_DECODING=1,C_RX_ENABLE=1,C_RX_INT_DATA_WIDTH=20,C_RX_LINE_RATE=1.25,C_RX_MASTER_CHANNEL_IDX=8,C_RX_OUTCLK_BUFG_GT_DIV=1,C_RX_OUTCLK_FREQUENCY=62.5000000,C_RX_OUTCLK_SOURCE=1,C_RX_PLL_TYPE=2,C_RX_RECCLK_OUTPUT=0x000000000000000000000000000000000000000000000000,C_RX_REFCLK_FREQUENCY=125,C_RX_SLIDE_MODE=1,C_RX_USER_CLOCKING_CONTENTS=0,C_RX_USER_CLOCKING_INSTANCE_CTRL=0,C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK=1,C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2=1,C_RX_USER_CLOCKING_\
    SOURCE=0,C_RX_USER_DATA_WIDTH=16,C_RX_USRCLK_FREQUENCY=62.5000000,C_RX_USRCLK2_FREQUENCY=62.5000000,C_SECONDARY_QPLL_ENABLE=0,C_SECONDARY_QPLL_REFCLK_FREQUENCY=257.8125,C_TOTAL_NUM_CHANNELS=1,C_TOTAL_NUM_COMMONS=0,C_TOTAL_NUM_COMMONS_EXAMPLE=0,C_TXPROGDIV_FREQ_ENABLE=0,C_TXPROGDIV_FREQ_SOURCE=2,C_TXPROGDIV_FREQ_VAL=62.5,C_TX_BUFFBYPASS_MODE=0,C_TX_BUFFER_BYPASS_INSTANCE_CTRL=0,C_TX_BUFFER_MODE=0,C_TX_DATA_ENCODING=1,C_TX_ENABLE=1,C_TX_INT_DATA_WIDTH=20,C_TX_LINE_RATE=1.25,C_TX_MASTER_CHANNEL_IDX\
    =8,C_TX_OUTCLK_BUFG_GT_DIV=2,C_TX_OUTCLK_FREQUENCY=125.0000000,C_TX_OUTCLK_SOURCE=2,C_TX_PLL_TYPE=2,C_TX_REFCLK_FREQUENCY=125,C_TX_USER_CLOCKING_CONTENTS=0,C_TX_USER_CLOCKING_INSTANCE_CTRL=0,C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK=2,C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2=1,C_TX_USER_CLOCKING_SOURCE=0,C_TX_USER_DATA_WIDTH=16,C_TX_USRCLK_FREQUENCY=62.5000000,C_TX_USRCLK2_FREQUENCY=62.5000000}" *)
    (* DowngradeIPIdentifiedWarnings = "yes" *)
    module wr_gth_wrapper (
    gtwiz_userclk_tx_active_in,
    gtwiz_userclk_rx_active_in,
    gtwiz_buffbypass_tx_reset_in,
    gtwiz_buffbypass_tx_start_user_in,
    gtwiz_buffbypass_tx_done_out,
    gtwiz_buffbypass_tx_error_out,
    gtwiz_buffbypass_rx_reset_in,
    gtwiz_buffbypass_rx_start_user_in,
    gtwiz_buffbypass_rx_done_out,
    gtwiz_buffbypass_rx_error_out,
    gtwiz_reset_clk_freerun_in,
    gtwiz_reset_all_in,
    gtwiz_reset_tx_pll_and_datapath_in,
    gtwiz_reset_tx_datapath_in,
    gtwiz_reset_rx_pll_and_datapath_in,
    gtwiz_reset_rx_datapath_in,
    gtwiz_reset_rx_cdr_stable_out,
    gtwiz_reset_tx_done_out,
    gtwiz_reset_rx_done_out,
    gtwiz_userdata_tx_in,
    gtwiz_userdata_rx_out,
    drpclk_in,
    gthrxn_in,
    gthrxp_in,
    gtrefclk0_in,
    rx8b10ben_in,
    rxcommadeten_in,
    rxmcommaalignen_in,
    rxpcommaalignen_in,
    rxslide_in,
    rxusrclk_in,
    rxusrclk2_in,
    tx8b10ben_in,
    txctrl0_in,
    txctrl1_in,
    txctrl2_in,
    txusrclk_in,
    txusrclk2_in,
    gthtxn_out,
    gthtxp_out,
    rxbyteisaligned_out,
    rxbyterealign_out,
    rxcommadet_out,
    rxctrl0_out,
    rxctrl1_out,
    rxctrl2_out,
    rxctrl3_out,
    rxoutclk_out,
    rxpmaresetdone_out,
    txoutclk_out,
    txpmaresetdone_out
    );
    input wire [0 : 0] gtwiz_userclk_tx_active_in;
    input wire [0 : 0] gtwiz_userclk_rx_active_in;
    input wire [0 : 0] gtwiz_buffbypass_tx_reset_in;
    input wire [0 : 0] gtwiz_buffbypass_tx_start_user_in;
    output wire [0 : 0] gtwiz_buffbypass_tx_done_out;
    output wire [0 : 0] gtwiz_buffbypass_tx_error_out;
    input wire [0 : 0] gtwiz_buffbypass_rx_reset_in;
    input wire [0 : 0] gtwiz_buffbypass_rx_start_user_in;
    output wire [0 : 0] gtwiz_buffbypass_rx_done_out;
    output wire [0 : 0] gtwiz_buffbypass_rx_error_out;
    input wire [0 : 0] gtwiz_reset_clk_freerun_in;
    input wire [0 : 0] gtwiz_reset_all_in;
    input wire [0 : 0] gtwiz_reset_tx_pll_and_datapath_in;
    input wire [0 : 0] gtwiz_reset_tx_datapath_in;
    input wire [0 : 0] gtwiz_reset_rx_pll_and_datapath_in;
    input wire [0 : 0] gtwiz_reset_rx_datapath_in;
    output wire [0 : 0] gtwiz_reset_rx_cdr_stable_out;
    output wire [0 : 0] gtwiz_reset_tx_done_out;
    output wire [0 : 0] gtwiz_reset_rx_done_out;
    input wire [15 : 0] gtwiz_userdata_tx_in;
    output wire [15 : 0] gtwiz_userdata_rx_out;
    input wire [0 : 0] drpclk_in;
    input wire [0 : 0] gthrxn_in;
    input wire [0 : 0] gthrxp_in;
    input wire [0 : 0] gtrefclk0_in;
    input wire [0 : 0] rx8b10ben_in;
    input wire [0 : 0] rxcommadeten_in;
    input wire [0 : 0] rxmcommaalignen_in;
    input wire [0 : 0] rxpcommaalignen_in;
    input wire [0 : 0] rxslide_in;
    input wire [0 : 0] rxusrclk_in;
    input wire [0 : 0] rxusrclk2_in;
    input wire [0 : 0] tx8b10ben_in;
    input wire [15 : 0] txctrl0_in;
    input wire [15 : 0] txctrl1_in;
    input wire [7 : 0] txctrl2_in;
    input wire [0 : 0] txusrclk_in;
    input wire [0 : 0] txusrclk2_in;
    output wire [0 : 0] gthtxn_out;
    output wire [0 : 0] gthtxp_out;
    output wire [0 : 0] rxbyteisaligned_out;
    output wire [0 : 0] rxbyterealign_out;
    output wire [0 : 0] rxcommadet_out;
    output wire [15 : 0] rxctrl0_out;
    output wire [15 : 0] rxctrl1_out;
    output wire [7 : 0] rxctrl2_out;
    output wire [7 : 0] rxctrl3_out;
    output wire [0 : 0] rxoutclk_out;
    output wire [0 : 0] rxpmaresetdone_out;
    output wire [0 : 0] txoutclk_out;
    output wire [0 : 0] txpmaresetdone_out;
    wr_gth_wrapper_gtwizard_top #(
    .C_CHANNEL_ENABLE(192'B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000),
    .C_PCIE_ENABLE(0),
    .C_PCIE_CORECLK_FREQ(250),
    .C_COMMON_SCALING_FACTOR(1),
    .C_CPLL_VCO_FREQUENCY(2500.0),
    .C_FORCE_COMMONS(0),
    .C_FREERUN_FREQUENCY(62.5),
    .C_GT_TYPE(0),
    .C_GT_REV(17),
    .C_INCLUDE_CPLL_CAL(2),
    .C_SIM_CPLL_CAL_BYPASS(1'B0),
    .C_LOCATE_COMMON(0),
    .C_LOCATE_RESET_CONTROLLER(0),
    .C_LOCATE_USER_DATA_WIDTH_SIZING(0),
    .C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER(0),
    .C_LOCATE_IN_SYSTEM_IBERT_CORE(2),
    .C_LOCATE_RX_USER_CLOCKING(1),
    .C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER(0),
    .C_LOCATE_TX_USER_CLOCKING(1),
    .C_RESET_CONTROLLER_INSTANCE_CTRL(0),
    .C_RX_BUFFBYPASS_MODE(0),
    .C_RX_BUFFER_BYPASS_INSTANCE_CTRL(0),
    .C_RX_BUFFER_MODE(0),
    .C_RX_CB_DISP(8'B00000000),
    .C_RX_CB_K(8'B00000000),
    .C_RX_CB_MAX_LEVEL(1),
    .C_RX_CB_LEN_SEQ(1),
    .C_RX_CB_NUM_SEQ(0),
    .C_RX_CB_VAL(80'B00000000000000000000000000000000000000000000000000000000000000000000000000000000),
    .C_RX_CC_DISP(8'B00000000),
    .C_RX_CC_ENABLE(0),
    .C_RESET_SEQUENCE_INTERVAL(0),
    .C_RX_CC_K(8'B00000000),
    .C_RX_CC_LEN_SEQ(1),
    .C_RX_CC_NUM_SEQ(0),
    .C_RX_CC_PERIODICITY(5000),
    .C_RX_CC_VAL(80'B00000000000000000000000000000000000000000000000000000000000000000000000000000000),
    .C_RX_COMMA_M_ENABLE(1),
    .C_RX_COMMA_M_VAL(10'B1010000011),
    .C_RX_COMMA_P_ENABLE(1),
    .C_RX_COMMA_P_VAL(10'B0101111100),
    .C_RX_DATA_DECODING(1),
    .C_RX_ENABLE(1),
    .C_RX_INT_DATA_WIDTH(20),
    .C_RX_LINE_RATE(1.25),
    .C_RX_MASTER_CHANNEL_IDX(8),
    .C_RX_OUTCLK_BUFG_GT_DIV(1),
    .C_RX_OUTCLK_FREQUENCY(62.5000000),
    .C_RX_OUTCLK_SOURCE(1),
    .C_RX_PLL_TYPE(2),
    .C_RX_RECCLK_OUTPUT(192'H000000000000000000000000000000000000000000000000),
    .C_RX_REFCLK_FREQUENCY(125),
    .C_RX_SLIDE_MODE(1),
    .C_RX_USER_CLOCKING_CONTENTS(0),
    .C_RX_USER_CLOCKING_INSTANCE_CTRL(0),
    .C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK(1),
    .C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2(1),
    .C_RX_USER_CLOCKING_SOURCE(0),
    .C_RX_USER_DATA_WIDTH(16),
    .C_RX_USRCLK_FREQUENCY(62.5000000),
    .C_RX_USRCLK2_FREQUENCY(62.5000000),
    .C_SECONDARY_QPLL_ENABLE(0),
    .C_SECONDARY_QPLL_REFCLK_FREQUENCY(257.8125),
    .C_TOTAL_NUM_CHANNELS(1),
    .C_TOTAL_NUM_COMMONS(0),
    .C_TOTAL_NUM_COMMONS_EXAMPLE(0),
    .C_TXPROGDIV_FREQ_ENABLE(0),
    .C_TXPROGDIV_FREQ_SOURCE(2),
    .C_TXPROGDIV_FREQ_VAL(62.5),
    .C_TX_BUFFBYPASS_MODE(0),
    .C_TX_BUFFER_BYPASS_INSTANCE_CTRL(0),
    .C_TX_BUFFER_MODE(0),
    .C_TX_DATA_ENCODING(1),
    .C_TX_ENABLE(1),
    .C_TX_INT_DATA_WIDTH(20),
    .C_TX_LINE_RATE(1.25),
    .C_TX_MASTER_CHANNEL_IDX(8),
    .C_TX_OUTCLK_BUFG_GT_DIV(2),
    .C_TX_OUTCLK_FREQUENCY(125.0000000),
    .C_TX_OUTCLK_SOURCE(2),
    .C_TX_PLL_TYPE(2),
    .C_TX_REFCLK_FREQUENCY(125),
    .C_TX_USER_CLOCKING_CONTENTS(0),
    .C_TX_USER_CLOCKING_INSTANCE_CTRL(0),
    .C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK(2),
    .C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2(1),
    .C_TX_USER_CLOCKING_SOURCE(0),
    .C_TX_USER_DATA_WIDTH(16),
    .C_TX_USRCLK_FREQUENCY(62.5000000),
    .C_TX_USRCLK2_FREQUENCY(62.5000000)
    ) inst (
    .gtwiz_userclk_tx_reset_in(1'B0),
    .gtwiz_userclk_tx_active_in(gtwiz_userclk_tx_active_in),
    .gtwiz_userclk_tx_srcclk_out(),
    .gtwiz_userclk_tx_usrclk_out(),
    .gtwiz_userclk_tx_usrclk2_out(),
    .gtwiz_userclk_tx_active_out(),
    .gtwiz_userclk_rx_reset_in(1'B0),
    .gtwiz_userclk_rx_active_in(gtwiz_userclk_rx_active_in),
    .gtwiz_userclk_rx_srcclk_out(),
    .gtwiz_userclk_rx_usrclk_out(),
    .gtwiz_userclk_rx_usrclk2_out(),
    .gtwiz_userclk_rx_active_out(),
    .gtwiz_buffbypass_tx_reset_in(gtwiz_buffbypass_tx_reset_in),
    .gtwiz_buffbypass_tx_start_user_in(gtwiz_buffbypass_tx_start_user_in),
    .gtwiz_buffbypass_tx_done_out(gtwiz_buffbypass_tx_done_out),
    .gtwiz_buffbypass_tx_error_out(gtwiz_buffbypass_tx_error_out),
    .gtwiz_buffbypass_rx_reset_in(gtwiz_buffbypass_rx_reset_in),
    .gtwiz_buffbypass_rx_start_user_in(gtwiz_buffbypass_rx_start_user_in),
    .gtwiz_buffbypass_rx_done_out(gtwiz_buffbypass_rx_done_out),
    .gtwiz_buffbypass_rx_error_out(gtwiz_buffbypass_rx_error_out),
    .gtwiz_reset_clk_freerun_in(gtwiz_reset_clk_freerun_in),
    .gtwiz_reset_all_in(gtwiz_reset_all_in),
    .gtwiz_reset_tx_pll_and_datapath_in(gtwiz_reset_tx_pll_and_datapath_in),
    .gtwiz_reset_tx_datapath_in(gtwiz_reset_tx_datapath_in),
    .gtwiz_reset_rx_pll_and_datapath_in(gtwiz_reset_rx_pll_and_datapath_in),
    .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_datapath_in),
    .gtwiz_reset_tx_done_in(1'B0),
    .gtwiz_reset_rx_done_in(1'B0),
    .gtwiz_reset_qpll0lock_in(1'B0),
    .gtwiz_reset_qpll1lock_in(1'B0),
    .gtwiz_reset_rx_cdr_stable_out(gtwiz_reset_rx_cdr_stable_out),
    .gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out),
    .gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out),
    .gtwiz_reset_qpll0reset_out(),
    .gtwiz_reset_qpll1reset_out(),
    .gtwiz_gthe3_cpll_cal_txoutclk_period_in(18'B0),
    .gtwiz_gthe3_cpll_cal_cnt_tol_in(18'B0),
    .gtwiz_gthe3_cpll_cal_bufg_ce_in(1'B0),
    .gtwiz_gthe4_cpll_cal_txoutclk_period_in(18'B0),
    .gtwiz_gthe4_cpll_cal_cnt_tol_in(18'B0),
    .gtwiz_gthe4_cpll_cal_bufg_ce_in(1'B0),
    .gtwiz_gtye4_cpll_cal_txoutclk_period_in(18'B0),
    .gtwiz_gtye4_cpll_cal_cnt_tol_in(18'B0),
    .gtwiz_gtye4_cpll_cal_bufg_ce_in(1'B0),
    .gtwiz_userdata_tx_in(gtwiz_userdata_tx_in),
    .gtwiz_userdata_rx_out(gtwiz_userdata_rx_out),
    .bgbypassb_in(1'H1),
    .bgmonitorenb_in(1'H1),
    .bgpdb_in(1'H1),
    .bgrcalovrd_in(5'H1F),
    .bgrcalovrdenb_in(1'H1),
    .drpaddr_common_in(9'H000),
    .drpclk_common_in(1'H0),
    .drpdi_common_in(16'H0000),
    .drpen_common_in(1'H0),
    .drpwe_common_in(1'H0),
    .gtgrefclk0_in(1'H0),
    .gtgrefclk1_in(1'H0),
    .gtnorthrefclk00_in(1'H0),
    .gtnorthrefclk01_in(1'H0),
    .gtnorthrefclk10_in(1'H0),
    .gtnorthrefclk11_in(1'H0),
    .gtrefclk00_in(1'H0),
    .gtrefclk01_in(1'H0),
    .gtrefclk10_in(1'H0),
    .gtrefclk11_in(1'H0),
    .gtsouthrefclk00_in(1'H0),
    .gtsouthrefclk01_in(1'H0),
    .gtsouthrefclk10_in(1'H0),
    .gtsouthrefclk11_in(1'H0),
    .pcierateqpll0_in(1'B0),
    .pcierateqpll1_in(1'B0),
    .pmarsvd0_in(8'H00),
    .pmarsvd1_in(8'H00),
    .qpll0clkrsvd0_in(1'H0),
    .qpll0clkrsvd1_in(1'H0),
    .qpll0fbdiv_in(1'B0),
    .qpll0lockdetclk_in(1'H0),
    .qpll0locken_in(1'H0),
    .qpll0pd_in(1'H1),
    .qpll0refclksel_in(3'H1),
    .qpll0reset_in(1'H1),
    .qpll1clkrsvd0_in(1'H0),
    .qpll1clkrsvd1_in(1'H0),
    .qpll1fbdiv_in(1'B0),
    .qpll1lockdetclk_in(1'H0),
    .qpll1locken_in(1'H0),
    .qpll1pd_in(1'H1),
    .qpll1refclksel_in(3'H1),
    .qpll1reset_in(1'H1),
    .qpllrsvd1_in(8'H00),
    .qpllrsvd2_in(5'H00),
    .qpllrsvd3_in(5'H00),
    .qpllrsvd4_in(8'H00),
    .rcalenb_in(1'H1),
    .sdm0data_in(1'B0),
    .sdm0reset_in(1'B0),
    .sdm0toggle_in(1'B0),
    .sdm0width_in(1'B0),
    .sdm1data_in(1'B0),
    .sdm1reset_in(1'B0),
    .sdm1toggle_in(1'B0),
    .sdm1width_in(1'B0),
    .tcongpi_in(1'B0),
    .tconpowerup_in(1'B0),
    .tconreset_in(1'B0),
    .tconrsvdin1_in(1'B0),
    .ubcfgstreamen_in(1'B0),
    .ubdo_in(1'B0),
    .ubdrdy_in(1'B0),
    .ubenable_in(1'B0),
    .ubgpi_in(1'B0),
    .ubintr_in(1'B0),
    .ubiolmbrst_in(1'B0),
    .ubmbrst_in(1'B0),
    .ubmdmcapture_in(1'B0),
    .ubmdmdbgrst_in(1'B0),
    .ubmdmdbgupdate_in(1'B0),
    .ubmdmregen_in(1'B0),
    .ubmdmshift_in(1'B0),
    .ubmdmsysrst_in(1'B0),
    .ubmdmtck_in(1'B0),
    .ubmdmtdi_in(1'B0),
    .drpdo_common_out(),
    .drprdy_common_out(),
    .pmarsvdout0_out(),
    .pmarsvdout1_out(),
    .qpll0fbclklost_out(),
    .qpll0lock_out(),
    .qpll0outclk_out(),
    .qpll0outrefclk_out(),
    .qpll0refclklost_out(),
    .qpll1fbclklost_out(),
    .qpll1lock_out(),
    .qpll1outclk_out(),
    .qpll1outrefclk_out(),
    .qpll1refclklost_out(),
    .qplldmonitor0_out(),
    .qplldmonitor1_out(),
    .refclkoutmonitor0_out(),
    .refclkoutmonitor1_out(),
    .rxrecclk0_sel_out(),
    .rxrecclk1_sel_out(),
    .rxrecclk0sel_out(),
    .rxrecclk1sel_out(),
    .sdm0finalout_out(),
    .sdm0testdata_out(),
    .sdm1finalout_out(),
    .sdm1testdata_out(),
    .tcongpo_out(),
    .tconrsvdout0_out(),
    .ubdaddr_out(),
    .ubden_out(),
    .ubdi_out(),
    .ubdwe_out(),
    .ubmdmtdo_out(),
    .ubrsvdout_out(),
    .ubtxuart_out(),
    .cdrstepdir_in(1'B0),
    .cdrstepsq_in(1'B0),
    .cdrstepsx_in(1'B0),
    .cfgreset_in(1'H0),
    .clkrsvd0_in(1'H0),
    .clkrsvd1_in(1'H0),
    .cpllfreqlock_in(1'B0),
    .cplllockdetclk_in(1'H0),
    .cplllocken_in(1'H1),
    .cpllpd_in(1'H0),
    .cpllrefclksel_in(3'H1),
    .cpllreset_in(1'H0),
    .dmonfiforeset_in(1'H0),
    .dmonitorclk_in(1'H0),
    .drpaddr_in(9'H000),
    .drpclk_in(drpclk_in),
    .drpdi_in(16'H0000),
    .drpen_in(1'H0),
    .drprst_in(1'B0),
    .drpwe_in(1'H0),
    .elpcaldvorwren_in(1'B0),
    .elpcalpaorwren_in(1'B0),
    .evoddphicaldone_in(1'H0),
    .evoddphicalstart_in(1'H0),
    .evoddphidrden_in(1'H0),
    .evoddphidwren_in(1'H0),
    .evoddphixrden_in(1'H0),
    .evoddphixwren_in(1'H0),
    .eyescanmode_in(1'H0),
    .eyescanreset_in(1'H0),
    .eyescantrigger_in(1'H0),
    .freqos_in(1'B0),
    .gtgrefclk_in(1'H0),
    .gthrxn_in(gthrxn_in),
    .gthrxp_in(gthrxp_in),
    .gtnorthrefclk0_in(1'H0),
    .gtnorthrefclk1_in(1'H0),
    .gtrefclk0_in(gtrefclk0_in),
    .gtrefclk1_in(1'H0),
    .gtresetsel_in(1'H0),
    .gtrsvd_in(16'H0000),
    .gtrxreset_in(1'H0),
    .gtrxresetsel_in(1'B0),
    .gtsouthrefclk0_in(1'H0),
    .gtsouthrefclk1_in(1'H0),
    .gttxreset_in(1'H0),
    .gttxresetsel_in(1'B0),
    .incpctrl_in(1'B0),
    .gtyrxn_in(1'B0),
    .gtyrxp_in(1'B0),
    .loopback_in(3'H0),
    .looprsvd_in(1'B0),
    .lpbkrxtxseren_in(1'H0),
    .lpbktxrxseren_in(1'H0),
    .pcieeqrxeqadaptdone_in(1'H0),
    .pcierstidle_in(1'H0),
    .pciersttxsyncstart_in(1'H0),
    .pcieuserratedone_in(1'H0),
    .pcsrsvdin_in(16'H0000),
    .pcsrsvdin2_in(5'H00),
    .pmarsvdin_in(5'H00),
    .qpll0clk_in(1'H0),
    .qpll0freqlock_in(1'B0),
    .qpll0refclk_in(1'H0),
    .qpll1clk_in(1'H0),
    .qpll1freqlock_in(1'B0),
    .qpll1refclk_in(1'H0),
    .resetovrd_in(1'H0),
    .rstclkentx_in(1'H0),
    .rx8b10ben_in(rx8b10ben_in),
    .rxafecfoken_in(1'B0),
    .rxbufreset_in(1'H0),
    .rxcdrfreqreset_in(1'H0),
    .rxcdrhold_in(1'H0),
    .rxcdrovrden_in(1'H0),
    .rxcdrreset_in(1'H0),
    .rxcdrresetrsv_in(1'H0),
    .rxchbonden_in(1'H0),
    .rxchbondi_in(5'H00),
    .rxchbondlevel_in(3'H0),
    .rxchbondmaster_in(1'H0),
    .rxchbondslave_in(1'H0),
    .rxckcalreset_in(1'B0),
    .rxckcalstart_in(1'B0),
    .rxcommadeten_in(rxcommadeten_in),
    .rxdfeagcctrl_in(2'H1),
    .rxdccforcestart_in(1'B0),
    .rxdfeagchold_in(1'H0),
    .rxdfeagcovrden_in(1'H0),
    .rxdfecfokfcnum_in(1'B0),
    .rxdfecfokfen_in(1'B0),
    .rxdfecfokfpulse_in(1'B0),
    .rxdfecfokhold_in(1'B0),
    .rxdfecfokovren_in(1'B0),
    .rxdfekhhold_in(1'B0),
    .rxdfekhovrden_in(1'B0),
    .rxdfelfhold_in(1'H0),
    .rxdfelfovrden_in(1'H0),
    .rxdfelpmreset_in(1'H0),
    .rxdfetap10hold_in(1'H0),
    .rxdfetap10ovrden_in(1'H0),
    .rxdfetap11hold_in(1'H0),
    .rxdfetap11ovrden_in(1'H0),
    .rxdfetap12hold_in(1'H0),
    .rxdfetap12ovrden_in(1'H0),
    .rxdfetap13hold_in(1'H0),
    .rxdfetap13ovrden_in(1'H0),
    .rxdfetap14hold_in(1'H0),
    .rxdfetap14ovrden_in(1'H0),
    .rxdfetap15hold_in(1'H0),
    .rxdfetap15ovrden_in(1'H0),
    .rxdfetap2hold_in(1'H0),
    .rxdfetap2ovrden_in(1'H0),
    .rxdfetap3hold_in(1'H0),
    .rxdfetap3ovrden_in(1'H0),
    .rxdfetap4hold_in(1'H0),
    .rxdfetap4ovrden_in(1'H0),
    .rxdfetap5hold_in(1'H0),
    .rxdfetap5ovrden_in(1'H0),
    .rxdfetap6hold_in(1'H0),
    .rxdfetap6ovrden_in(1'H0),
    .rxdfetap7hold_in(1'H0),
    .rxdfetap7ovrden_in(1'H0),
    .rxdfetap8hold_in(1'H0),
    .rxdfetap8ovrden_in(1'H0),
    .rxdfetap9hold_in(1'H0),
    .rxdfetap9ovrden_in(1'H0),
    .rxdfeuthold_in(1'H0),
    .rxdfeutovrden_in(1'H0),
    .rxdfevphold_in(1'H0),
    .rxdfevpovrden_in(1'H0),
    .rxdfevsen_in(1'H0),
    .rxdfexyden_in(1'H1),
    .rxdlybypass_in(1'H0),
    .rxdlyen_in(1'H0),
    .rxdlyovrden_in(1'H0),
    .rxdlysreset_in(1'H0),
    .rxelecidlemode_in(2'H3),
    .rxeqtraining_in(1'B0),
    .rxgearboxslip_in(1'H0),
    .rxlatclk_in(1'H0),
    .rxlpmen_in(1'H1),
    .rxlpmgchold_in(1'H0),
    .rxlpmgcovrden_in(1'H0),
    .rxlpmhfhold_in(1'H0),
    .rxlpmhfovrden_in(1'H0),
    .rxlpmlfhold_in(1'H0),
    .rxlpmlfklovrden_in(1'H0),
    .rxlpmoshold_in(1'H0),
    .rxlpmosovrden_in(1'H0),
    .rxmcommaalignen_in(rxmcommaalignen_in),
    .rxmonitorsel_in(2'H0),
    .rxoobreset_in(1'H0),
    .rxoscalreset_in(1'H0),
    .rxoshold_in(1'H0),
    .rxosintcfg_in(4'HD),
    .rxosinten_in(1'H1),
    .rxosinthold_in(1'H0),
    .rxosintovrden_in(1'H0),
    .rxosintstrobe_in(1'H0),
    .rxosinttestovrden_in(1'H0),
    .rxosovrden_in(1'H0),
    .rxoutclksel_in(3'H2),
    .rxpcommaalignen_in(rxpcommaalignen_in),
    .rxpcsreset_in(1'H0),
    .rxpd_in(2'H0),
    .rxphalign_in(1'H0),
    .rxphalignen_in(1'H0),
    .rxphdlypd_in(1'H0),
    .rxphdlyreset_in(1'H0),
    .rxphovrden_in(1'H0),
    .rxpllclksel_in(2'H0),
    .rxpmareset_in(1'H0),
    .rxpolarity_in(1'H0),
    .rxprbscntreset_in(1'H0),
    .rxprbssel_in(4'H0),
    .rxprogdivreset_in(1'H0),
    .rxqpien_in(1'H0),
    .rxrate_in(3'H0),
    .rxratemode_in(1'H0),
    .rxslide_in(rxslide_in),
    .rxslipoutclk_in(1'H0),
    .rxslippma_in(1'H0),
    .rxsyncallin_in(1'H0),
    .rxsyncin_in(1'H0),
    .rxsyncmode_in(1'H0),
    .rxsysclksel_in(2'H0),
    .rxtermination_in(1'B0),
    .rxuserrdy_in(1'H1),
    .rxusrclk_in(rxusrclk_in),
    .rxusrclk2_in(rxusrclk2_in),
    .sigvalidclk_in(1'H0),
    .tstin_in(20'H00000),
    .tx8b10bbypass_in(8'H00),
    .tx8b10ben_in(tx8b10ben_in),
    .txbufdiffctrl_in(3'H0),
    .txcominit_in(1'H0),
    .txcomsas_in(1'H0),
    .txcomwake_in(1'H0),
    .txctrl0_in(txctrl0_in),
    .txctrl1_in(txctrl1_in),
    .txctrl2_in(txctrl2_in),
    .txdata_in(128'B0),
    .txdataextendrsvd_in(8'H00),
    .txdccforcestart_in(1'B0),
    .txdccreset_in(1'B0),
    .txdeemph_in(1'H0),
    .txdetectrx_in(1'H0),
    .txdiffctrl_in(4'HC),
    .txdiffpd_in(1'H0),
    .txdlybypass_in(1'H0),
    .txdlyen_in(1'H0),
    .txdlyhold_in(1'H0),
    .txdlyovrden_in(1'H0),
    .txdlysreset_in(1'H0),
    .txdlyupdown_in(1'H0),
    .txelecidle_in(1'H0),
    .txelforcestart_in(1'B0),
    .txheader_in(6'H00),
    .txinhibit_in(1'H0),
    .txlatclk_in(1'H0),
    .txlfpstreset_in(1'B0),
    .txlfpsu2lpexit_in(1'B0),
    .txlfpsu3wake_in(1'B0),
    .txmaincursor_in(7'H40),
    .txmargin_in(3'H0),
    .txmuxdcdexhold_in(1'B0),
    .txmuxdcdorwren_in(1'B0),
    .txoneszeros_in(1'B0),
    .txoutclksel_in(3'H3),
    .txpcsreset_in(1'H0),
    .txpd_in(2'H0),
    .txpdelecidlemode_in(1'H0),
    .txphalign_in(1'H0),
    .txphalignen_in(1'H0),
    .txphdlypd_in(1'H0),
    .txphdlyreset_in(1'H0),
    .txphdlytstclk_in(1'H0),
    .txphinit_in(1'H0),
    .txphovrden_in(1'H0),
    .txpippmen_in(1'H0),
    .txpippmovrden_in(1'H0),
    .txpippmpd_in(1'H0),
    .txpippmsel_in(1'H0),
    .txpippmstepsize_in(5'H00),
    .txpisopd_in(1'H0),
    .txpllclksel_in(2'H0),
    .txpmareset_in(1'H0),
    .txpolarity_in(1'H0),
    .txpostcursor_in(5'H00),
    .txpostcursorinv_in(1'H0),
    .txprbsforceerr_in(1'H0),
    .txprbssel_in(4'H0),
    .txprecursor_in(5'H00),
    .txprecursorinv_in(1'H0),
    .txprogdivreset_in(1'H0),
    .txqpibiasen_in(1'H0),
    .txqpistrongpdown_in(1'H0),
    .txqpiweakpup_in(1'H0),
    .txrate_in(3'H0),
    .txratemode_in(1'H0),
    .txsequence_in(7'H00),
    .txswing_in(1'H0),
    .txsyncallin_in(1'H0),
    .txsyncin_in(1'H0),
    .txsyncmode_in(1'H0),
    .txsysclksel_in(2'H0),
    .txuserrdy_in(1'H1),
    .txusrclk_in(txusrclk_in),
    .txusrclk2_in(txusrclk2_in),
    .bufgtce_out(),
    .bufgtcemask_out(),
    .bufgtdiv_out(),
    .bufgtreset_out(),
    .bufgtrstmask_out(),
    .cpllfbclklost_out(),
    .cplllock_out(),
    .cpllrefclklost_out(),
    .dmonitorout_out(),
    .dmonitoroutclk_out(),
    .drpdo_out(),
    .drprdy_out(),
    .eyescandataerror_out(),
    .gthtxn_out(gthtxn_out),
    .gthtxp_out(gthtxp_out),
    .gtpowergood_out(),
    .gtrefclkmonitor_out(),
    .gtytxn_out(),
    .gtytxp_out(),
    .pcierategen3_out(),
    .pcierateidle_out(),
    .pcierateqpllpd_out(),
    .pcierateqpllreset_out(),
    .pciesynctxsyncdone_out(),
    .pcieusergen3rdy_out(),
    .pcieuserphystatusrst_out(),
    .pcieuserratestart_out(),
    .pcsrsvdout_out(),
    .phystatus_out(),
    .pinrsrvdas_out(),
    .powerpresent_out(),
    .resetexception_out(),
    .rxbufstatus_out(),
    .rxbyteisaligned_out(rxbyteisaligned_out),
    .rxbyterealign_out(rxbyterealign_out),
    .rxcdrlock_out(),
    .rxcdrphdone_out(),
    .rxchanbondseq_out(),
    .rxchanisaligned_out(),
    .rxchanrealign_out(),
    .rxchbondo_out(),
    .rxckcaldone_out(),
    .rxclkcorcnt_out(),
    .rxcominitdet_out(),
    .rxcommadet_out(rxcommadet_out),
    .rxcomsasdet_out(),
    .rxcomwakedet_out(),
    .rxctrl0_out(rxctrl0_out),
    .rxctrl1_out(rxctrl1_out),
    .rxctrl2_out(rxctrl2_out),
    .rxctrl3_out(rxctrl3_out),
    .rxdata_out(),
    .rxdataextendrsvd_out(),
    .rxdatavalid_out(),
    .rxdlysresetdone_out(),
    .rxelecidle_out(),
    .rxheader_out(),
    .rxheadervalid_out(),
    .rxlfpstresetdet_out(),
    .rxlfpsu2lpexitdet_out(),
    .rxlfpsu3wakedet_out(),
    .rxmonitorout_out(),
    .rxosintdone_out(),
    .rxosintstarted_out(),
    .rxosintstrobedone_out(),
    .rxosintstrobestarted_out(),
    .rxoutclk_out(rxoutclk_out),
    .rxoutclkfabric_out(),
    .rxoutclkpcs_out(),
    .rxphaligndone_out(),
    .rxphalignerr_out(),
    .rxpmaresetdone_out(rxpmaresetdone_out),
    .rxprbserr_out(),
    .rxprbslocked_out(),
    .rxprgdivresetdone_out(),
    .rxqpisenn_out(),
    .rxqpisenp_out(),
    .rxratedone_out(),
    .rxrecclkout_out(),
    .rxresetdone_out(),
    .rxsliderdy_out(),
    .rxslipdone_out(),
    .rxslipoutclkrdy_out(),
    .rxslippmardy_out(),
    .rxstartofseq_out(),
    .rxstatus_out(),
    .rxsyncdone_out(),
    .rxsyncout_out(),
    .rxvalid_out(),
    .txbufstatus_out(),
    .txcomfinish_out(),
    .txdccdone_out(),
    .txdlysresetdone_out(),
    .txoutclk_out(txoutclk_out),
    .txoutclkfabric_out(),
    .txoutclkpcs_out(),
    .txphaligndone_out(),
    .txphinitdone_out(),
    .txpmaresetdone_out(txpmaresetdone_out),
    .txprgdivresetdone_out(),
    .txqpisenn_out(),
    .txqpisenp_out(),
    .txratedone_out(),
    .txresetdone_out(),
    .txsyncdone_out(),
    .txsyncout_out()
    );
    endmodule
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_bit_sync.v 0 → 100644
    View file @ d5952890
    //------------------------------------------------------------------------------
    // (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
    //
    // This file contains confidential and proprietary information
    // of Xilinx, Inc. and is protected under U.S. and
    // international copyright and other intellectual property
    // laws.
    //
    // DISCLAIMER
    // This disclaimer is not a license and does not grant any
    // rights to the materials distributed herewith. Except as
    // otherwise provided in a valid license issued to you by
    // Xilinx, and to the maximum extent permitted by applicable
    // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
    // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
    // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
    // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
    // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
    // (2) Xilinx shall not be liable (whether in contract or tort,
    // including negligence, or under any other theory of
    // liability) for any loss or damage of any kind or nature
    // related to, arising under or in connection with these
    // materials, including for any direct, or any indirect,
    // special, incidental, or consequential loss or damage
    // (including loss of data, profits, goodwill, or any type of
    // loss or damage suffered as a result of any action brought
    // by a third party) even if such damage or loss was
    // reasonably foreseeable or Xilinx had been advised of the
    // possibility of the same.
    //
    // CRITICAL APPLICATIONS
    // Xilinx products are not designed or intended to be fail-
    // safe, or for use in any application requiring fail-safe
    // performance, such as life-support or safety devices or
    // systems, Class III medical devices, nuclear facilities,
    // applications related to the deployment of airbags, or any
    // other applications that could lead to death, personal
    // injury, or severe property or environmental damage
    // (individually and collectively, "Critical
    // Applications"). Customer assumes the sole risk and
    // liability of any use of Xilinx products in Critical
    // Applications, subject only to applicable laws and
    // regulations governing limitations on product liability.
    //
    // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
    // PART OF THIS FILE AT ALL TIMES.
    //------------------------------------------------------------------------------
    `timescale 1ps/1ps
    // *********************************************************************************************************************
    // IMPORTANT
    // This block is delivered within the example design. If you wish to modify its behavior, be careful to understand the
    // existing behavior and the effects of any modifications you may choose to make.
    // *********************************************************************************************************************
    module wr_gth_wrapper_example_bit_synchronizer # (
    parameter INITIALIZE = 5'b00000,
    parameter FREQUENCY = 512
    )(
    input wire clk_in,
    input wire i_in,
    output wire o_out
    );
    // Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to
    // enable clustering. Their GSR default values are provided by the INITIALIZE parameter.
    (* ASYNC_REG = "TRUE" *) reg i_in_meta = INITIALIZE[0];
    (* ASYNC_REG = "TRUE" *) reg i_in_sync1 = INITIALIZE[1];
    (* ASYNC_REG = "TRUE" *) reg i_in_sync2 = INITIALIZE[2];
    (* ASYNC_REG = "TRUE" *) reg i_in_sync3 = INITIALIZE[3];
    reg i_in_out = INITIALIZE[4];
    always @(posedge clk_in) begin
    i_in_meta <= i_in;
    i_in_sync1 <= i_in_meta;
    i_in_sync2 <= i_in_sync1;
    i_in_sync3 <= i_in_sync2;
    i_in_out <= i_in_sync3;
    end
    assign o_out = i_in_out;
    endmodule
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_gtwiz_userclk_rx.v 0 → 100644
    View file @ d5952890
    //------------------------------------------------------------------------------
    // (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
    //
    // This file contains confidential and proprietary information
    // of Xilinx, Inc. and is protected under U.S. and
    // international copyright and other intellectual property
    // laws.
    //
    // DISCLAIMER
    // This disclaimer is not a license and does not grant any
    // rights to the materials distributed herewith. Except as
    // otherwise provided in a valid license issued to you by
    // Xilinx, and to the maximum extent permitted by applicable
    // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
    // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
    // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
    // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
    // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
    // (2) Xilinx shall not be liable (whether in contract or tort,
    // including negligence, or under any other theory of
    // liability) for any loss or damage of any kind or nature
    // related to, arising under or in connection with these
    // materials, including for any direct, or any indirect,
    // special, incidental, or consequential loss or damage
    // (including loss of data, profits, goodwill, or any type of
    // loss or damage suffered as a result of any action brought
    // by a third party) even if such damage or loss was
    // reasonably foreseeable or Xilinx had been advised of the
    // possibility of the same.
    //
    // CRITICAL APPLICATIONS
    // Xilinx products are not designed or intended to be fail-
    // safe, or for use in any application requiring fail-safe
    // performance, such as life-support or safety devices or
    // systems, Class III medical devices, nuclear facilities,
    // applications related to the deployment of airbags, or any
    // other applications that could lead to death, personal
    // injury, or severe property or environmental damage
    // (individually and collectively, "Critical
    // Applications"). Customer assumes the sole risk and
    // liability of any use of Xilinx products in Critical
    // Applications, subject only to applicable laws and
    // regulations governing limitations on product liability.
    //
    // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
    // PART OF THIS FILE AT ALL TIMES.
    //------------------------------------------------------------------------------
    `timescale 1ps/1ps
    // *********************************************************************************************************************
    // IMPORTANT
    // This helper block was chosen for exclusion from the IP core, and is therefore delivered within the example design.
    // However, it is still customized for the chosen core configuration. If you wish to modify its behavior, refer to this
    // core's Product Guide for possible guidance and be careful to understand the existing behavior and the effects of any
    // modifications you may choose to make.
    // *********************************************************************************************************************
    module wr_gth_wrapper_example_gtwiz_userclk_rx #(
    parameter integer P_CONTENTS = 0,
    parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK = 1,
    parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK2 = 1
    )(
    input wire gtwiz_userclk_rx_srcclk_in,
    input wire gtwiz_userclk_rx_reset_in,
    output wire gtwiz_userclk_rx_usrclk_out,
    output wire gtwiz_userclk_rx_usrclk2_out,
    output wire gtwiz_userclk_rx_active_out
    );
    // -------------------------------------------------------------------------------------------------------------------
    // Local parameters
    // -------------------------------------------------------------------------------------------------------------------
    // Convert integer parameters with known, limited legal range to a 3-bit local parameter values
    localparam integer P_USRCLK_INT_DIV = P_FREQ_RATIO_SOURCE_TO_USRCLK - 1;
    localparam [2:0] P_USRCLK_DIV = P_USRCLK_INT_DIV[2:0];
    localparam integer P_USRCLK2_INT_DIV = (P_FREQ_RATIO_SOURCE_TO_USRCLK * P_FREQ_RATIO_USRCLK_TO_USRCLK2) - 1;
    localparam [2:0] P_USRCLK2_DIV = P_USRCLK2_INT_DIV[2:0];
    // -------------------------------------------------------------------------------------------------------------------
    // Receiver user clocking network conditional generation, based on parameter values in module instantiation
    // -------------------------------------------------------------------------------------------------------------------
    generate if (1) begin: gen_gtwiz_userclk_rx_main
    // Use BUFG_GT instance(s) to drive RXUSRCLK and RXUSRCLK2, inferred for integral source to RXUSRCLK frequency ratio
    if (P_CONTENTS == 0) begin
    // Drive RXUSRCLK with BUFG_GT-buffered source clock, dividing the input by the integral source clock to RXUSRCLK
    // frequency ratio
    BUFG_GT bufg_gt_usrclk_inst (
    .CE (1'b1),
    .CEMASK (1'b0),
    .CLR (gtwiz_userclk_rx_reset_in),
    .CLRMASK (1'b0),
    .DIV (P_USRCLK_DIV),
    .I (gtwiz_userclk_rx_srcclk_in),
    .O (gtwiz_userclk_rx_usrclk_out)
    );
    // If RXUSRCLK and RXUSRCLK2 frequencies are identical, drive both from the same BUFG_GT. Otherwise, drive
    // RXUSRCLK2 from a second BUFG_GT instance, dividing the source clock down to the RXUSRCLK2 frequency.
    if (P_FREQ_RATIO_USRCLK_TO_USRCLK2 == 1)
    assign gtwiz_userclk_rx_usrclk2_out = gtwiz_userclk_rx_usrclk_out;
    else begin
    BUFG_GT bufg_gt_usrclk2_inst (
    .CE (1'b1),
    .CEMASK (1'b0),
    .CLR (gtwiz_userclk_rx_reset_in),
    .CLRMASK (1'b0),
    .DIV (P_USRCLK2_DIV),
    .I (gtwiz_userclk_rx_srcclk_in),
    .O (gtwiz_userclk_rx_usrclk2_out)
    );
    end
    // Indicate active helper block functionality when the BUFG_GT divider is not held in reset
    (* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_rx_active_meta = 1'b0;
    (* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_rx_active_sync = 1'b0;
    always @(posedge gtwiz_userclk_rx_usrclk2_out, posedge gtwiz_userclk_rx_reset_in) begin
    if (gtwiz_userclk_rx_reset_in) begin
    gtwiz_userclk_rx_active_meta <= 1'b0;
    gtwiz_userclk_rx_active_sync <= 1'b0;
    end
    else begin
    gtwiz_userclk_rx_active_meta <= 1'b1;
    gtwiz_userclk_rx_active_sync <= gtwiz_userclk_rx_active_meta;
    end
    end
    assign gtwiz_userclk_rx_active_out = gtwiz_userclk_rx_active_sync;
    end
    end
    endgenerate
    endmodule
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_gtwiz_userclk_tx.v 0 → 100644
    View file @ d5952890
    //------------------------------------------------------------------------------
    // (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
    //
    // This file contains confidential and proprietary information
    // of Xilinx, Inc. and is protected under U.S. and
    // international copyright and other intellectual property
    // laws.
    //
    // DISCLAIMER
    // This disclaimer is not a license and does not grant any
    // rights to the materials distributed herewith. Except as
    // otherwise provided in a valid license issued to you by
    // Xilinx, and to the maximum extent permitted by applicable
    // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
    // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
    // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
    // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
    // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
    // (2) Xilinx shall not be liable (whether in contract or tort,
    // including negligence, or under any other theory of
    // liability) for any loss or damage of any kind or nature
    // related to, arising under or in connection with these
    // materials, including for any direct, or any indirect,
    // special, incidental, or consequential loss or damage
    // (including loss of data, profits, goodwill, or any type of
    // loss or damage suffered as a result of any action brought
    // by a third party) even if such damage or loss was
    // reasonably foreseeable or Xilinx had been advised of the
    // possibility of the same.
    //
    // CRITICAL APPLICATIONS
    // Xilinx products are not designed or intended to be fail-
    // safe, or for use in any application requiring fail-safe
    // performance, such as life-support or safety devices or
    // systems, Class III medical devices, nuclear facilities,
    // applications related to the deployment of airbags, or any
    // other applications that could lead to death, personal
    // injury, or severe property or environmental damage
    // (individually and collectively, "Critical
    // Applications"). Customer assumes the sole risk and
    // liability of any use of Xilinx products in Critical
    // Applications, subject only to applicable laws and
    // regulations governing limitations on product liability.
    //
    // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
    // PART OF THIS FILE AT ALL TIMES.
    //------------------------------------------------------------------------------
    `timescale 1ps/1ps
    // *********************************************************************************************************************
    // IMPORTANT
    // This helper block was chosen for exclusion from the IP core, and is therefore delivered within the example design.
    // However, it is still customized for the chosen core configuration. If you wish to modify its behavior, refer to this
    // core's Product Guide for possible guidance and be careful to understand the existing behavior and the effects of any
    // modifications you may choose to make.
    // *********************************************************************************************************************
    module wr_gth_wrapper_example_gtwiz_userclk_tx #(
    parameter integer P_CONTENTS = 0,
    parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK = 2,
    parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK2 = 1
    )(
    input wire gtwiz_userclk_tx_srcclk_in,
    input wire gtwiz_userclk_tx_reset_in,
    output wire gtwiz_userclk_tx_usrclk_out,
    output wire gtwiz_userclk_tx_usrclk2_out,
    output wire gtwiz_userclk_tx_active_out
    );
    // -------------------------------------------------------------------------------------------------------------------
    // Local parameters
    // -------------------------------------------------------------------------------------------------------------------
    // Convert integer parameters with known, limited legal range to a 3-bit local parameter values
    localparam integer P_USRCLK_INT_DIV = P_FREQ_RATIO_SOURCE_TO_USRCLK - 1;
    localparam [2:0] P_USRCLK_DIV = P_USRCLK_INT_DIV[2:0];
    localparam integer P_USRCLK2_INT_DIV = (P_FREQ_RATIO_SOURCE_TO_USRCLK * P_FREQ_RATIO_USRCLK_TO_USRCLK2) - 1;
    localparam [2:0] P_USRCLK2_DIV = P_USRCLK2_INT_DIV[2:0];
    // -------------------------------------------------------------------------------------------------------------------
    // Transmitter user clocking network conditional generation, based on parameter values in module instantiation
    // -------------------------------------------------------------------------------------------------------------------
    generate if (1) begin: gen_gtwiz_userclk_tx_main
    // Use BUFG_GT instance(s) to drive TXUSRCLK and TXUSRCLK2, inferred for integral source to TXUSRCLK frequency ratio
    if (P_CONTENTS == 0) begin
    // Drive TXUSRCLK with BUFG_GT-buffered source clock, dividing the input by the integral source clock to TXUSRCLK
    // frequency ratio
    BUFG_GT bufg_gt_usrclk_inst (
    .CE (1'b1),
    .CEMASK (1'b0),
    .CLR (gtwiz_userclk_tx_reset_in),
    .CLRMASK (1'b0),
    .DIV (P_USRCLK_DIV),
    .I (gtwiz_userclk_tx_srcclk_in),
    .O (gtwiz_userclk_tx_usrclk_out)
    );
    // If TXUSRCLK and TXUSRCLK2 frequencies are identical, drive both from the same BUFG_GT. Otherwise, drive
    // TXUSRCLK2 from a second BUFG_GT instance, dividing the source clock down to the TXUSRCLK2 frequency.
    if (P_FREQ_RATIO_USRCLK_TO_USRCLK2 == 1)
    assign gtwiz_userclk_tx_usrclk2_out = gtwiz_userclk_tx_usrclk_out;
    else begin
    BUFG_GT bufg_gt_usrclk2_inst (
    .CE (1'b1),
    .CEMASK (1'b0),
    .CLR (gtwiz_userclk_tx_reset_in),
    .CLRMASK (1'b0),
    .DIV (P_USRCLK2_DIV),
    .I (gtwiz_userclk_tx_srcclk_in),
    .O (gtwiz_userclk_tx_usrclk2_out)
    );
    end
    // Indicate active helper block functionality when the BUFG_GT divider is not held in reset
    (* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_tx_active_meta = 1'b0;
    (* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_tx_active_sync = 1'b0;
    always @(posedge gtwiz_userclk_tx_usrclk2_out, posedge gtwiz_userclk_tx_reset_in) begin
    if (gtwiz_userclk_tx_reset_in) begin
    gtwiz_userclk_tx_active_meta <= 1'b0;
    gtwiz_userclk_tx_active_sync <= 1'b0;
    end
    else begin
    gtwiz_userclk_tx_active_meta <= 1'b1;
    gtwiz_userclk_tx_active_sync <= gtwiz_userclk_tx_active_meta;
    end
    end
    assign gtwiz_userclk_tx_active_out = gtwiz_userclk_tx_active_sync;
    end
    end
    endgenerate
    endmodule
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_init.v 0 → 100644
    View file @ d5952890
    //------------------------------------------------------------------------------
    // (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
    //
    // This file contains confidential and proprietary information
    // of Xilinx, Inc. and is protected under U.S. and
    // international copyright and other intellectual property
    // laws.
    //
    // DISCLAIMER
    // This disclaimer is not a license and does not grant any
    // rights to the materials distributed herewith. Except as
    // otherwise provided in a valid license issued to you by
    // Xilinx, and to the maximum extent permitted by applicable
    // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
    // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
    // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
    // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
    // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
    // (2) Xilinx shall not be liable (whether in contract or tort,
    // including negligence, or under any other theory of
    // liability) for any loss or damage of any kind or nature
    // related to, arising under or in connection with these
    // materials, including for any direct, or any indirect,
    // special, incidental, or consequential loss or damage
    // (including loss of data, profits, goodwill, or any type of
    // loss or damage suffered as a result of any action brought
    // by a third party) even if such damage or loss was
    // reasonably foreseeable or Xilinx had been advised of the
    // possibility of the same.
    //
    // CRITICAL APPLICATIONS
    // Xilinx products are not designed or intended to be fail-
    // safe, or for use in any application requiring fail-safe
    // performance, such as life-support or safety devices or
    // systems, Class III medical devices, nuclear facilities,
    // applications related to the deployment of airbags, or any
    // other applications that could lead to death, personal
    // injury, or severe property or environmental damage
    // (individually and collectively, "Critical
    // Applications"). Customer assumes the sole risk and
    // liability of any use of Xilinx products in Critical
    // Applications, subject only to applicable laws and
    // regulations governing limitations on product liability.
    //
    // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
    // PART OF THIS FILE AT ALL TIMES.
    //------------------------------------------------------------------------------
    `timescale 1ps/1ps
    // =====================================================================================================================
    // This example design initialization module provides a demonstration of how initialization logic can be constructed to
    // interact with and enhance the reset controller helper block in order to assist with successful system bring-up. This
    // example initialization logic monitors for timely reset completion, retrying resets as necessary to mitigate problems
    // with system bring-up such as clock or data connection readiness. This is an example and can be modified as necessary.
    // =====================================================================================================================
    module wr_gth_wrapper_example_init # (
    parameter real P_FREERUN_FREQUENCY = 62.5,
    parameter real P_TX_TIMER_DURATION_US = 300,
    parameter real P_RX_TIMER_DURATION_US = 300
    )(
    input wire clk_freerun_in,
    input wire reset_all_in,
    input wire tx_init_done_in,
    input wire rx_init_done_in,
    input wire rx_data_good_in,
    output reg reset_all_out = 1'b0,
    output reg reset_rx_out = 1'b0,
    output reg init_done_out = 1'b0,
    output reg [3:0] retry_ctr_out = 4'd0
    );
    // -------------------------------------------------------------------------------------------------------------------
    // Synchronizers
    // -------------------------------------------------------------------------------------------------------------------
    // Synchronize the "reset all" input signal into the free-running clock domain
    // The reset_all_in input should be driven by the master "reset all" example design input
    wire reset_all_sync;
    (* DONT_TOUCH = "TRUE" *)
    wr_gth_wrapper_example_reset_synchronizer reset_synchronizer_reset_all_inst (
    .clk_in (clk_freerun_in),
    .rst_in (reset_all_in),
    .rst_out (reset_all_sync)
    );
    // Synchronize the TX initialization done indicator into the free-running clock domain
    // The tx_init_done_in input should be driven by the signal or logical combination of signals that represents a
    // completed TX initialization process; for example, the reset helper block gtwiz_reset_tx_done_out signal, or the
    // logical AND of gtwiz_reset_tx_done_out with gtwiz_buffbypass_tx_done_out if the TX buffer is bypassed.
    wire tx_init_done_sync;
    (* DONT_TOUCH = "TRUE" *)
    wr_gth_wrapper_example_bit_synchronizer bit_synchronizer_tx_init_done_inst (
    .clk_in (clk_freerun_in),
    .i_in (tx_init_done_in),
    .o_out (tx_init_done_sync)
    );
    // Synchronize the RX initialization done indicator into the free-running clock domain
    // The rx_init_done_in input should be driven by the signal or logical combination of signals that represents a
    // completed RX initialization process; for example, the reset helper block gtwiz_reset_rx_done_out signal, or the
    // logical AND of gtwiz_reset_rx_done_out with gtwiz_buffbypass_rx_done_out if the RX elastic buffer is bypassed.
    wire rx_init_done_sync;
    (* DONT_TOUCH = "TRUE" *)
    wr_gth_wrapper_example_bit_synchronizer bit_synchronizer_rx_init_done_inst (
    .clk_in (clk_freerun_in),
    .i_in (rx_init_done_in),
    .o_out (rx_init_done_sync)
    );
    // Synchronize the RX data good indicator into the free-running clock domain
    // The rx_data_good_in input should be driven the user application's indication of continual good data reception.
    // The example design drives rx_data_good_in high when no PRBS checker errors are seen in the 8 most recent
    // consecutive clock cycles of data reception.
    wire rx_data_good_sync;
    (* DONT_TOUCH = "TRUE" *)
    wr_gth_wrapper_example_bit_synchronizer bit_synchronizer_rx_data_good_inst (
    .clk_in (clk_freerun_in),
    .i_in (rx_data_good_in),
    .o_out (rx_data_good_sync)
    );
    // -------------------------------------------------------------------------------------------------------------------
    // Timer
    // -------------------------------------------------------------------------------------------------------------------
    // Declare registers and local parameters used for the shared TX and RX initialization timer
    // The free-running clock frequency is specified by the P_FREERUN_FREQUENCY parameter. The TX initialization timer
    // duration is specified by the P_TX_TIMER_DURATION_US parameter (default 30,000us), and the resulting terminal count
    // is assigned to p_tx_timer_term_cyc_int. The RX initialization timer duration is specified by the
    // P_RX_TIMER_DURATION_US parameter (default 130,000us), and the resulting terminal count is assigned to
    // p_rx_timer_term_cyc_int.
    reg timer_clr = 1'b1;
    reg [24:0] timer_ctr = 25'd0;
    reg tx_timer_sat = 1'b0;
    reg rx_timer_sat = 1'b0;
    wire [24:0] p_tx_timer_term_cyc_int = P_TX_TIMER_DURATION_US * P_FREERUN_FREQUENCY;
    wire [24:0] p_rx_timer_term_cyc_int = P_RX_TIMER_DURATION_US * P_FREERUN_FREQUENCY;
    // When the timer is enabled by the initialization state machine, increment the timer_ctr counter until its value
    // reaches p_rx_timer_term_cyc_int RX terminal count and rx_timer_sat is asserted. Assert tx_timer_sat when the
    // counter value reaches the p_tx_timer_term_cyc_int TX terminal count. Clear the timer and remove assertions when the
    // timer is disabled by the initialization state machine.
    always @(posedge clk_freerun_in) begin
    if (timer_clr) begin
    timer_ctr <= 25'd0;
    tx_timer_sat <= 1'b0;
    rx_timer_sat <= 1'b0;
    end
    else begin
    if (timer_ctr == p_tx_timer_term_cyc_int)
    tx_timer_sat <= 1'b1;
    if (timer_ctr == p_rx_timer_term_cyc_int)
    rx_timer_sat <= 1'b1;
    else
    timer_ctr <= timer_ctr + 25'd1;
    end
    end
    // -------------------------------------------------------------------------------------------------------------------
    // Retry counter
    // -------------------------------------------------------------------------------------------------------------------
    // Increment the retry_ctr_out register for each TX or RX reset asserted by the initialization state machine until the
    // register saturates at 4'd15. This value, which is initialized on device programming and is never reset, could be
    // useful for debugging purposes. The initialization state machine will continue to retry as needed beyond the retry
    // register saturation point indicated, so 4'd15 should be interpreted as "15 or more attempts since programming."
    reg retry_ctr_incr = 1'b0;
    always @(posedge clk_freerun_in) begin
    if ((retry_ctr_incr == 1'b1) && (retry_ctr_out != 4'd15))
    retry_ctr_out <= retry_ctr_out + 4'd1;
    end
    // -------------------------------------------------------------------------------------------------------------------
    // Initialization state machine
    // -------------------------------------------------------------------------------------------------------------------
    // Declare local parameters and state register for the initialization state machine
    localparam [1:0] ST_START = 2'd0;
    localparam [1:0] ST_TX_WAIT = 2'd1;
    localparam [1:0] ST_RX_WAIT = 2'd2;
    localparam [1:0] ST_MONITOR = 2'd3;
    reg [1:0] sm_init = ST_START;
    reg sm_init_active = 1'b0;
    // Implement the initialization state machine control and its outputs as a single sequential process. The state
    // machine is reset by the synchronized reset_all_in input, and does not begin operating until its first use. Note
    // that this state machine is designed to interact with and enhance the reset controller helper block.
    always @(posedge clk_freerun_in) begin
    if (reset_all_sync) begin
    timer_clr <= 1'b1;
    reset_all_out <= 1'b0;
    reset_rx_out <= 1'b0;
    retry_ctr_incr <= 1'b0;
    init_done_out <= 1'b0;
    sm_init_active <= 1'b1;
    sm_init <= ST_START;
    end
    else begin
    case (sm_init)
    // When starting the initialization procedure, clear the timer and remove reset outputs, then proceed to wait
    // for completion of TX initialization
    ST_START: begin
    if (sm_init_active) begin
    timer_clr <= 1'b1;
    reset_all_out <= 1'b0;
    reset_rx_out <= 1'b0;
    retry_ctr_incr <= 1'b0;
    sm_init <= ST_TX_WAIT;
    end
    end
    // Enable the timer. If TX initialization completes before the counter's TX terminal count, clear the timer and
    // proceed to wait for RX initialization. If the TX terminal count is reached, clear the timer, assert the
    // reset_all_out output (which in this example causes a master reset_all assertion), and increment the retry
    // counter. Completion conditions for TX initialization are described above.
    ST_TX_WAIT: begin
    if (tx_init_done_sync) begin
    timer_clr <= 1'b1;
    sm_init <= ST_RX_WAIT;
    end
    else begin
    if (tx_timer_sat) begin
    timer_clr <= 1'b1;
    reset_all_out <= 1'b1;
    retry_ctr_incr <= 1'b1;
    sm_init <= ST_START;
    end
    else begin
    timer_clr <= 1'b0;
    end
    end
    end
    // Enable the timer. When the RX terminal count is reached, check whether RX initialization has completed and
    // whether the data good indicator is high. If both conditions are met, transition to the MONITOR state. If
    // either condition is not met, then clear the timer, assert the reset_rx_out output (which in this example
    // either drives gtwiz_reset_rx_pll_and_datapath_in or gtwiz_reset_rx_datapath_in, depending on PLL sharing),
    // and increnent the retry counter.
    ST_RX_WAIT: begin
    if (rx_timer_sat) begin
    if (rx_init_done_sync && rx_data_good_sync) begin
    init_done_out <= 1'b1;
    sm_init <= ST_MONITOR;
    end
    else begin
    timer_clr <= 1'b1;
    reset_rx_out <= 1'b1;
    retry_ctr_incr <= 1'b1;
    sm_init <= ST_START;
    end
    end
    else begin
    timer_clr <= 1'b0;
    end
    end
    // In this MONITOR state, assert the init_done_out output for use as desired. If RX initialization or the data
    // good indicator is lost while in this state, reset the RX components as described in the ST_RX_WAIT state.
    ST_MONITOR: begin
    if (~rx_init_done_sync || ~rx_data_good_sync) begin
    init_done_out <= 1'b0;
    timer_clr <= 1'b1;
    reset_rx_out <= 1'b1;
    retry_ctr_incr <= 1'b1;
    sm_init <= ST_START;
    end
    end
    endcase
    end
    end
    endmodule
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_reset_sync.v 0 → 100644
    View file @ d5952890
    //------------------------------------------------------------------------------
    // (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
    //
    // This file contains confidential and proprietary information
    // of Xilinx, Inc. and is protected under U.S. and
    // international copyright and other intellectual property
    // laws.
    //
    // DISCLAIMER
    // This disclaimer is not a license and does not grant any
    // rights to the materials distributed herewith. Except as
    // otherwise provided in a valid license issued to you by
    // Xilinx, and to the maximum extent permitted by applicable
    // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
    // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
    // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
    // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
    // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
    // (2) Xilinx shall not be liable (whether in contract or tort,
    // including negligence, or under any other theory of
    // liability) for any loss or damage of any kind or nature
    // related to, arising under or in connection with these
    // materials, including for any direct, or any indirect,
    // special, incidental, or consequential loss or damage
    // (including loss of data, profits, goodwill, or any type of
    // loss or damage suffered as a result of any action brought
    // by a third party) even if such damage or loss was
    // reasonably foreseeable or Xilinx had been advised of the
    // possibility of the same.
    //
    // CRITICAL APPLICATIONS
    // Xilinx products are not designed or intended to be fail-
    // safe, or for use in any application requiring fail-safe
    // performance, such as life-support or safety devices or
    // systems, Class III medical devices, nuclear facilities,
    // applications related to the deployment of airbags, or any
    // other applications that could lead to death, personal
    // injury, or severe property or environmental damage
    // (individually and collectively, "Critical
    // Applications"). Customer assumes the sole risk and
    // liability of any use of Xilinx products in Critical
    // Applications, subject only to applicable laws and
    // regulations governing limitations on product liability.
    //
    // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
    // PART OF THIS FILE AT ALL TIMES.
    //------------------------------------------------------------------------------
    `timescale 1ps/1ps
    // *********************************************************************************************************************
    // IMPORTANT
    // This block is delivered within the example design. If you wish to modify its behavior, be careful to understand the
    // existing behavior and the effects of any modifications you may choose to make.
    // *********************************************************************************************************************
    module wr_gth_wrapper_example_reset_synchronizer # (
    parameter FREQUENCY = 512
    )(
    input wire clk_in,
    input wire rst_in,
    output wire rst_out
    );
    // Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to
    // enable clustering. Each flip-flop in the synchronizer is asynchronously reset so that the downstream logic is also
    // asynchronously reset but encounters no reset assertion latency. The removal of reset is synchronous, so that the
    // downstream logic is also removed from reset synchronously. This module is designed for active-high reset use.
    (* ASYNC_REG = "TRUE" *) reg rst_in_meta = 1'b0;
    (* ASYNC_REG = "TRUE" *) reg rst_in_sync1 = 1'b0;
    (* ASYNC_REG = "TRUE" *) reg rst_in_sync2 = 1'b0;
    (* ASYNC_REG = "TRUE" *) reg rst_in_sync3 = 1'b0;
    reg rst_in_out = 1'b0;
    always @(posedge clk_in, posedge rst_in) begin
    if (rst_in) begin
    rst_in_meta <= 1'b1;
    rst_in_sync1 <= 1'b1;
    rst_in_sync2 <= 1'b1;
    rst_in_sync3 <= 1'b1;
    rst_in_out <= 1'b1;
    end
    else begin
    rst_in_meta <= 1'b0;
    rst_in_sync1 <= rst_in_meta;
    rst_in_sync2 <= rst_in_sync1;
    rst_in_sync3 <= rst_in_sync2;
    rst_in_out <= rst_in_sync3;
    end
    end
    assign rst_out = rst_in_out;
    endmodule
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_top.v 0 → 100644
    View file @ d5952890
    //------------------------------------------------------------------------------
    // (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
    //
    // This file contains confidential and proprietary information
    // of Xilinx, Inc. and is protected under U.S. and
    // international copyright and other intellectual property
    // laws.
    //
    // DISCLAIMER
    // This disclaimer is not a license and does not grant any
    // rights to the materials distributed herewith. Except as
    // otherwise provided in a valid license issued to you by
    // Xilinx, and to the maximum extent permitted by applicable
    // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
    // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
    // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
    // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
    // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
    // (2) Xilinx shall not be liable (whether in contract or tort,
    // including negligence, or under any other theory of
    // liability) for any loss or damage of any kind or nature
    // related to, arising under or in connection with these
    // materials, including for any direct, or any indirect,
    // special, incidental, or consequential loss or damage
    // (including loss of data, profits, goodwill, or any type of
    // loss or damage suffered as a result of any action brought
    // by a third party) even if such damage or loss was
    // reasonably foreseeable or Xilinx had been advised of the
    // possibility of the same.
    //
    // CRITICAL APPLICATIONS
    // Xilinx products are not designed or intended to be fail-
    // safe, or for use in any application requiring fail-safe
    // performance, such as life-support or safety devices or
    // systems, Class III medical devices, nuclear facilities,
    // applications related to the deployment of airbags, or any
    // other applications that could lead to death, personal
    // injury, or severe property or environmental damage
    // (individually and collectively, "Critical
    // Applications"). Customer assumes the sole risk and
    // liability of any use of Xilinx products in Critical
    // Applications, subject only to applicable laws and
    // regulations governing limitations on product liability.
    //
    // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
    // PART OF THIS FILE AT ALL TIMES.
    //------------------------------------------------------------------------------
    `timescale 1ps/1ps
    // =====================================================================================================================
    // This example design top module instantiates the example design wrapper; slices vectored ports for per-channel
    // assignment; and instantiates example resources such as buffers, pattern generators, and pattern checkers for core
    // demonstration purposes
    // =====================================================================================================================
    module wr_gth_wrapper_example_top (
    // Differential reference clock inputs
    input wire mgtrefclk0_x0y2_p,
    input wire mgtrefclk0_x0y2_n,
    // Serial data ports for transceiver channel 0
    input wire ch0_gthrxn_in,
    input wire ch0_gthrxp_in,
    output wire ch0_gthtxn_out,
    output wire ch0_gthtxp_out,
    // User-provided ports for reset helper block(s)
    input wire hb_gtwiz_reset_clk_freerun_in,
    input wire hb_gtwiz_reset_all_in,
    output tx_clk_o,
    input [15:0] tx_data_i,
    output [15:0] rx_data_o,
    input rx_slide_i,
    output rx_byte_is_aligned_o,
    output rx_comma_det_o,
    output rx_clk_o,
    input [1:0] tx_k_i,
    output [1:0] rx_k_o,
    output ready_o
    );
    // ===================================================================================================================
    // PER-CHANNEL SIGNAL ASSIGNMENTS
    // ===================================================================================================================
    // The core and example design wrapper vectorize ports across all enabled transceiver channel and common instances for
    // simplicity and compactness. This example design top module assigns slices of each vector to individual, per-channel
    // signal vectors for use if desired. Signals which connect to helper blocks are prefixed "hb#", signals which connect
    // to transceiver common primitives are prefixed "cm#", and signals which connect to transceiver channel primitives
    // are prefixed "ch#", where "#" is the sequential resource number.
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gthrxn_int;
    assign gthrxn_int[0:0] = ch0_gthrxn_in;
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gthrxp_int;
    assign gthrxp_int[0:0] = ch0_gthrxp_in;
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gthtxn_int;
    assign ch0_gthtxn_out = gthtxn_int[0:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gthtxp_int;
    assign ch0_gthtxp_out = gthtxp_int[0:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_userclk_tx_reset_int;
    wire [0:0] hb0_gtwiz_userclk_tx_reset_int;
    assign gtwiz_userclk_tx_reset_int[0:0] = hb0_gtwiz_userclk_tx_reset_int;
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_userclk_tx_srcclk_int;
    wire [0:0] hb0_gtwiz_userclk_tx_srcclk_int;
    assign hb0_gtwiz_userclk_tx_srcclk_int = gtwiz_userclk_tx_srcclk_int[0:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_userclk_tx_usrclk_int;
    wire [0:0] hb0_gtwiz_userclk_tx_usrclk_int;
    assign hb0_gtwiz_userclk_tx_usrclk_int = gtwiz_userclk_tx_usrclk_int[0:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_userclk_tx_usrclk2_int;
    wire [0:0] hb0_gtwiz_userclk_tx_usrclk2_int;
    assign hb0_gtwiz_userclk_tx_usrclk2_int = gtwiz_userclk_tx_usrclk2_int[0:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_userclk_tx_active_int;
    wire [0:0] hb0_gtwiz_userclk_tx_active_int;
    assign hb0_gtwiz_userclk_tx_active_int = gtwiz_userclk_tx_active_int[0:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_userclk_rx_reset_int;
    wire [0:0] hb0_gtwiz_userclk_rx_reset_int;
    assign gtwiz_userclk_rx_reset_int[0:0] = hb0_gtwiz_userclk_rx_reset_int;
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_userclk_rx_srcclk_int;
    wire [0:0] hb0_gtwiz_userclk_rx_srcclk_int;
    assign hb0_gtwiz_userclk_rx_srcclk_int = gtwiz_userclk_rx_srcclk_int[0:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_userclk_rx_usrclk_int;
    wire [0:0] hb0_gtwiz_userclk_rx_usrclk_int;
    assign hb0_gtwiz_userclk_rx_usrclk_int = gtwiz_userclk_rx_usrclk_int[0:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_userclk_rx_usrclk2_int;
    wire [0:0] hb0_gtwiz_userclk_rx_usrclk2_int;
    assign hb0_gtwiz_userclk_rx_usrclk2_int = gtwiz_userclk_rx_usrclk2_int[0:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_userclk_rx_active_int;
    wire [0:0] hb0_gtwiz_userclk_rx_active_int;
    assign hb0_gtwiz_userclk_rx_active_int = gtwiz_userclk_rx_active_int[0:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_buffbypass_tx_reset_int;
    wire [0:0] hb0_gtwiz_buffbypass_tx_reset_int;
    assign gtwiz_buffbypass_tx_reset_int[0:0] = hb0_gtwiz_buffbypass_tx_reset_int;
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_buffbypass_tx_start_user_int;
    wire [0:0] hb0_gtwiz_buffbypass_tx_start_user_int = 1'b0;
    assign gtwiz_buffbypass_tx_start_user_int[0:0] = hb0_gtwiz_buffbypass_tx_start_user_int;
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_buffbypass_tx_done_int;
    wire [0:0] hb0_gtwiz_buffbypass_tx_done_int;
    assign hb0_gtwiz_buffbypass_tx_done_int = gtwiz_buffbypass_tx_done_int[0:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_buffbypass_tx_error_int;
    wire [0:0] hb0_gtwiz_buffbypass_tx_error_int;
    assign hb0_gtwiz_buffbypass_tx_error_int = gtwiz_buffbypass_tx_error_int[0:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_buffbypass_rx_reset_int;
    wire [0:0] hb0_gtwiz_buffbypass_rx_reset_int;
    assign gtwiz_buffbypass_rx_reset_int[0:0] = hb0_gtwiz_buffbypass_rx_reset_int;
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_buffbypass_rx_start_user_int;
    wire [0:0] hb0_gtwiz_buffbypass_rx_start_user_int = 1'b0;
    assign gtwiz_buffbypass_rx_start_user_int[0:0] = hb0_gtwiz_buffbypass_rx_start_user_int;
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_buffbypass_rx_done_int;
    wire [0:0] hb0_gtwiz_buffbypass_rx_done_int;
    assign hb0_gtwiz_buffbypass_rx_done_int = gtwiz_buffbypass_rx_done_int[0:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_buffbypass_rx_error_int;
    wire [0:0] hb0_gtwiz_buffbypass_rx_error_int;
    assign hb0_gtwiz_buffbypass_rx_error_int = gtwiz_buffbypass_rx_error_int[0:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_reset_clk_freerun_int;
    wire [0:0] hb0_gtwiz_reset_clk_freerun_int = 1'b0;
    assign gtwiz_reset_clk_freerun_int[0:0] = hb0_gtwiz_reset_clk_freerun_int;
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_reset_all_int;
    wire [0:0] hb0_gtwiz_reset_all_int = 1'b0;
    assign gtwiz_reset_all_int[0:0] = hb0_gtwiz_reset_all_int;
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_reset_tx_pll_and_datapath_int = 1'b0;
    wire [0:0] hb0_gtwiz_reset_tx_pll_and_datapath_int;
    assign gtwiz_reset_tx_pll_and_datapath_int[0:0] = hb0_gtwiz_reset_tx_pll_and_datapath_int;
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_reset_tx_datapath_int = 1'b0;
    wire [0:0] hb0_gtwiz_reset_tx_datapath_int;
    assign gtwiz_reset_tx_datapath_int[0:0] = hb0_gtwiz_reset_tx_datapath_int;
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_reset_rx_pll_and_datapath_int;
    wire [0:0] hb0_gtwiz_reset_rx_pll_and_datapath_int = 1'b0;
    assign gtwiz_reset_rx_pll_and_datapath_int[0:0] = hb0_gtwiz_reset_rx_pll_and_datapath_int;
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_reset_rx_datapath_int;
    wire [0:0] hb0_gtwiz_reset_rx_datapath_int = 1'b0;
    assign gtwiz_reset_rx_datapath_int[0:0] = hb0_gtwiz_reset_rx_datapath_int;
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_reset_rx_cdr_stable_int;
    wire [0:0] hb0_gtwiz_reset_rx_cdr_stable_int;
    assign hb0_gtwiz_reset_rx_cdr_stable_int = gtwiz_reset_rx_cdr_stable_int[0:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_reset_tx_done_int;
    wire [0:0] hb0_gtwiz_reset_tx_done_int;
    assign hb0_gtwiz_reset_tx_done_int = gtwiz_reset_tx_done_int[0:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtwiz_reset_rx_done_int;
    wire [0:0] hb0_gtwiz_reset_rx_done_int;
    assign hb0_gtwiz_reset_rx_done_int = gtwiz_reset_rx_done_int[0:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [15:0] gtwiz_userdata_tx_int;
    wire [15:0] hb0_gtwiz_userdata_tx_int;
    assign gtwiz_userdata_tx_int[15:0] = hb0_gtwiz_userdata_tx_int;
    //--------------------------------------------------------------------------------------------------------------------
    wire [15:0] gtwiz_userdata_rx_int;
    wire [15:0] hb0_gtwiz_userdata_rx_int;
    assign hb0_gtwiz_userdata_rx_int = gtwiz_userdata_rx_int[15:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] drpclk_int;
    wire [0:0] ch0_drpclk_int;
    assign drpclk_int[0:0] = ch0_drpclk_int;
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] gtrefclk0_int;
    wire [0:0] ch0_gtrefclk0_int;
    assign gtrefclk0_int[0:0] = ch0_gtrefclk0_int;
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] rx8b10ben_int;
    wire [0:0] ch0_rx8b10ben_int = 1'b1;
    assign rx8b10ben_int[0:0] = ch0_rx8b10ben_int;
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] rxcommadeten_int;
    wire [0:0] ch0_rxcommadeten_int = 1'b1;
    assign rxcommadeten_int[0:0] = ch0_rxcommadeten_int;
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] rxmcommaalignen_int;
    wire [0:0] ch0_rxmcommaalignen_int = 1'b0;
    assign rxmcommaalignen_int[0:0] = ch0_rxmcommaalignen_int;
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] rxpcommaalignen_int;
    wire [0:0] ch0_rxpcommaalignen_int = 1'b0;
    assign rxpcommaalignen_int[0:0] = ch0_rxpcommaalignen_int;
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] tx8b10ben_int;
    wire [0:0] ch0_tx8b10ben_int = 1'b1;
    assign tx8b10ben_int[0:0] = ch0_tx8b10ben_int;
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] rxbyteisaligned_int;
    wire [0:0] ch0_rxbyteisaligned_int;
    assign ch0_rxbyteisaligned_int = rxbyteisaligned_int[0:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] rxbyterealign_int;
    wire [0:0] ch0_rxbyterealign_int;
    assign ch0_rxbyterealign_int = rxbyterealign_int[0:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] rxcommadet_int;
    wire [0:0] ch0_rxcommadet_int;
    assign ch0_rxcommadet_int = rxcommadet_int[0:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [15:0] rxctrl0_int;
    wire [15:0] ch0_rxctrl0_int;
    assign ch0_rxctrl0_int = rxctrl0_int[15:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [15:0] rxctrl1_int;
    wire [15:0] ch0_rxctrl1_int;
    assign ch0_rxctrl1_int = rxctrl1_int[15:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [7:0] rxctrl2_int;
    wire [7:0] ch0_rxctrl2_int;
    assign ch0_rxctrl2_int = rxctrl2_int[7:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [7:0] rxctrl3_int;
    wire [7:0] ch0_rxctrl3_int;
    assign ch0_rxctrl3_int = rxctrl3_int[7:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] rxpmaresetdone_int;
    wire [0:0] ch0_rxpmaresetdone_int;
    assign ch0_rxpmaresetdone_int = rxpmaresetdone_int[0:0];
    //--------------------------------------------------------------------------------------------------------------------
    wire [0:0] txpmaresetdone_int;
    wire [0:0] ch0_txpmaresetdone_int;
    assign ch0_txpmaresetdone_int = txpmaresetdone_int[0:0];
    // ===================================================================================================================
    // BUFFERS
    // ===================================================================================================================
    // Buffer the hb_gtwiz_reset_all_in input and logically combine it with the internal signal from the example
    // initialization block as well as the VIO-sourced reset
    wire hb_gtwiz_reset_all_vio_int;
    wire hb_gtwiz_reset_all_buf_int;
    wire hb_gtwiz_reset_all_init_int;
    wire hb_gtwiz_reset_all_int;
    assign hb_gtwiz_reset_all_buf_int = hb_gtwiz_reset_all_in;
    assign hb_gtwiz_reset_all_int = hb_gtwiz_reset_all_buf_int || hb_gtwiz_reset_all_init_int;
    // Globally buffer the free-running input clock
    wire hb_gtwiz_reset_clk_freerun_buf_int;
    BUFG bufg_clk_freerun_inst (
    .I (hb_gtwiz_reset_clk_freerun_in),
    .O (hb_gtwiz_reset_clk_freerun_buf_int)
    );
    // For GTH core configurations which utilize the transceiver channel CPLL, the drpclk_in port must be driven by
    // the free-running clock at the exact frequency specified during core customization, for reliable bring-up
    assign ch0_drpclk_int = hb_gtwiz_reset_clk_freerun_buf_int;
    // Instantiate a differential reference clock buffer for each reference clock differential pair in this configuration,
    // and assign the single-ended output of each differential reference clock buffer to the appropriate PLL input signal
    // Differential reference clock buffer for MGTREFCLK0_X0Y2
    wire mgtrefclk0_x0y2_int;
    IBUFDS_GTE3 #(
    .REFCLK_EN_TX_PATH (1'b0),
    .REFCLK_HROW_CK_SEL (2'b00),
    .REFCLK_ICNTL_RX (2'b00)
    ) IBUFDS_GTE3_MGTREFCLK0_X0Y2_INST (
    .I (mgtrefclk0_x0y2_p),
    .IB (mgtrefclk0_x0y2_n),
    .CEB (1'b0),
    .O (mgtrefclk0_x0y2_int),
    .ODIV2 ()
    );
    assign ch0_gtrefclk0_int = mgtrefclk0_x0y2_int;
    // ===================================================================================================================
    // USER CLOCKING RESETS
    // ===================================================================================================================
    // The TX user clocking helper block should be held in reset until the clock source of that block is known to be
    // stable. The following assignment is an example of how that stability can be determined, based on the selected TX
    // user clock source. Replace the assignment with the appropriate signal or logic to achieve that behavior as needed.
    assign hb0_gtwiz_userclk_tx_reset_int = ~(&txpmaresetdone_int);
    // The RX user clocking helper block should be held in reset until the clock source of that block is known to be
    // stable. The following assignment is an example of how that stability can be determined, based on the selected RX
    // user clock source. Replace the assignment with the appropriate signal or logic to achieve that behavior as needed.
    assign hb0_gtwiz_userclk_rx_reset_int = ~(&rxpmaresetdone_int);
    // ===================================================================================================================
    // BUFFER BYPASS CONTROLLER RESETS
    // ===================================================================================================================
    // The TX buffer bypass controller helper block should be held in reset until the TX user clocking network helper
    // block which drives it is active
    (* DONT_TOUCH = "TRUE" *)
    wr_gth_wrapper_example_reset_synchronizer reset_synchronizer_gtwiz_buffbypass_tx_reset_inst (
    .clk_in (hb0_gtwiz_userclk_tx_usrclk2_int),
    .rst_in (~hb0_gtwiz_userclk_tx_active_int),
    .rst_out (hb0_gtwiz_buffbypass_tx_reset_int)
    );
    // The RX buffer bypass controller helper block should be held in reset until the RX user clocking network helper
    // block which drives it is active and the TX buffer bypass sequence has completed for this loopback configuration
    (* DONT_TOUCH = "TRUE" *)
    wr_gth_wrapper_example_reset_synchronizer reset_synchronizer_gtwiz_buffbypass_rx_reset_inst (
    .clk_in (hb0_gtwiz_userclk_rx_usrclk2_int),
    .rst_in (~hb0_gtwiz_userclk_rx_active_int || ~hb0_gtwiz_buffbypass_tx_done_int),
    .rst_out (hb0_gtwiz_buffbypass_rx_reset_int)
    );
    assign tx_clk_o = hb0_gtwiz_userclk_tx_usrclk2_int;
    assign rx_clk_o = hb0_gtwiz_userclk_rx_usrclk2_int;
    assign hb0_gtwiz_userdata_tx_int = tx_data_i;
    assign rx_data_o = hb0_gtwiz_userdata_rx_int;
    assign ready_o = ~(hb_gtwiz_reset_all_int || ~hb0_gtwiz_reset_rx_done_int || ~hb0_gtwiz_buffbypass_rx_done_int || ~hb0_gtwiz_buffbypass_tx_done_int);
    wire [15:0] txctrl0_int;
    wire [15:0] txctrl1_int;
    wire [7:0] txctrl2_int;
    assign txctrl0_int = 16'b0;
    assign txctrl1_int = 16'b0;
    assign txctrl2_int = {6'b0, tx_k_i};
    assign rx_k_o = rxctrl0_int[1:0];
    // ===================================================================================================================
    // INITIALIZATION
    // ===================================================================================================================
    // Declare the receiver reset signals that interface to the reset controller helper block. For this configuration,
    // which uses the same PLL type for transmitter and receiver, the "reset RX PLL and datapath" feature is not used.
    wire hb_gtwiz_reset_rx_pll_and_datapath_int = 1'b0;
    wire hb_gtwiz_reset_rx_datapath_int;
    // Declare signals which connect the VIO instance to the initialization module for debug purposes
    wire init_done_int;
    wire [3:0] init_retry_ctr_int;
    // Combine the receiver reset signals form the initialization module and the VIO to drive the appropriate reset
    // controller helper block reset input
    wire hb_gtwiz_reset_rx_datapath_init_int;
    assign hb_gtwiz_reset_rx_datapath_int = hb_gtwiz_reset_rx_datapath_init_int ;
    // The example initialization module interacts with the reset controller helper block and other example design logic
    // to retry failed reset attempts in order to mitigate bring-up issues such as initially-unavilable reference clocks
    // or data connections. It also resets the receiver in the event of link loss in an attempt to regain link, so please
    // note the possibility that this behavior can have the effect of overriding or disturbing user-provided inputs that
    // destabilize the data stream. It is a demonstration only and can be modified to suit your system needs.
    wr_gth_wrapper_example_init example_init_inst (
    .clk_freerun_in (hb_gtwiz_reset_clk_freerun_buf_int),
    .reset_all_in (hb_gtwiz_reset_all_int),
    .tx_init_done_in (gtwiz_reset_tx_done_int && gtwiz_buffbypass_tx_done_int),
    .rx_init_done_in (gtwiz_reset_rx_done_int && gtwiz_buffbypass_rx_done_int),
    .rx_data_good_in (1'b1),
    .reset_all_out (hb_gtwiz_reset_all_init_int),
    .reset_rx_out (hb_gtwiz_reset_rx_datapath_init_int),
    .init_done_out (init_done_int),
    .retry_ctr_out (init_retry_ctr_int)
    );
    // ===================================================================================================================
    // EXAMPLE WRAPPER INSTANCE
    // ===================================================================================================================
    // Instantiate the example design wrapper, mapping its enabled ports to per-channel internal signals and example
    // resources as appropriate
    wr_gth_wrapper_example_wrapper example_wrapper_inst (
    .gthrxn_in (gthrxn_int)
    ,.gthrxp_in (gthrxp_int)
    ,.gthtxn_out (gthtxn_int)
    ,.gthtxp_out (gthtxp_int)
    ,.gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_int)
    ,.gtwiz_userclk_tx_srcclk_out (gtwiz_userclk_tx_srcclk_int)
    ,.gtwiz_userclk_tx_usrclk_out (gtwiz_userclk_tx_usrclk_int)
    ,.gtwiz_userclk_tx_usrclk2_out (gtwiz_userclk_tx_usrclk2_int)
    ,.gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_int)
    ,.gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_int)
    ,.gtwiz_userclk_rx_srcclk_out (gtwiz_userclk_rx_srcclk_int)
    ,.gtwiz_userclk_rx_usrclk_out (gtwiz_userclk_rx_usrclk_int)
    ,.gtwiz_userclk_rx_usrclk2_out (gtwiz_userclk_rx_usrclk2_int)
    ,.gtwiz_userclk_rx_active_out (gtwiz_userclk_rx_active_int)
    ,.gtwiz_buffbypass_tx_reset_in (gtwiz_buffbypass_tx_reset_int)
    ,.gtwiz_buffbypass_tx_start_user_in (gtwiz_buffbypass_tx_start_user_int)
    ,.gtwiz_buffbypass_tx_done_out (gtwiz_buffbypass_tx_done_int)
    ,.gtwiz_buffbypass_tx_error_out (gtwiz_buffbypass_tx_error_int)
    ,.gtwiz_buffbypass_rx_reset_in (gtwiz_buffbypass_rx_reset_int)
    ,.gtwiz_buffbypass_rx_start_user_in (gtwiz_buffbypass_rx_start_user_int)
    ,.gtwiz_buffbypass_rx_done_out (gtwiz_buffbypass_rx_done_int)
    ,.gtwiz_buffbypass_rx_error_out (gtwiz_buffbypass_rx_error_int)
    ,.gtwiz_reset_clk_freerun_in ({1{hb_gtwiz_reset_clk_freerun_buf_int}})
    ,.gtwiz_reset_all_in ({1{hb_gtwiz_reset_all_int}})
    ,.gtwiz_reset_tx_pll_and_datapath_in (gtwiz_reset_tx_pll_and_datapath_int)
    ,.gtwiz_reset_tx_datapath_in (gtwiz_reset_tx_datapath_int)
    ,.gtwiz_reset_rx_pll_and_datapath_in ({1{hb_gtwiz_reset_rx_pll_and_datapath_int}})
    ,.gtwiz_reset_rx_datapath_in ({1{hb_gtwiz_reset_rx_datapath_int}})
    ,.gtwiz_reset_rx_cdr_stable_out (gtwiz_reset_rx_cdr_stable_int)
    ,.gtwiz_reset_tx_done_out (gtwiz_reset_tx_done_int)
    ,.gtwiz_reset_rx_done_out (gtwiz_reset_rx_done_int)
    ,.gtwiz_userdata_tx_in (gtwiz_userdata_tx_int)
    ,.gtwiz_userdata_rx_out (gtwiz_userdata_rx_int)
    ,.drpclk_in (drpclk_int)
    ,.gtrefclk0_in (gtrefclk0_int)
    ,.rx8b10ben_in (rx8b10ben_int)
    ,.rxcommadeten_in (rxcommadeten_int)
    ,.rxmcommaalignen_in (rxmcommaalignen_int)
    ,.rxpcommaalignen_in (rxpcommaalignen_int)
    ,.rxslide_in (rx_slide_i)
    ,.tx8b10ben_in (tx8b10ben_int)
    ,.txctrl0_in (txctrl0_int)
    ,.txctrl1_in (txctrl1_int)
    ,.txctrl2_in (txctrl2_int)
    ,.rxbyteisaligned_out (rx_byte_is_aligned_o)
    ,.rxbyterealign_out (rxbyterealign_int)
    ,.rxcommadet_out (rx_comma_det_o)
    ,.rxctrl0_out (rxctrl0_int)
    ,.rxctrl1_out (rxctrl1_int)
    ,.rxctrl2_out (rxctrl2_int)
    ,.rxctrl3_out (rxctrl3_int)
    ,.rxpmaresetdone_out (rxpmaresetdone_int)
    ,.txpmaresetdone_out (txpmaresetdone_int)
    );
    endmodule
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_wrapper.v 0 → 100644
    View file @ d5952890
    //------------------------------------------------------------------------------
    // (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
    //
    // This file contains confidential and proprietary information
    // of Xilinx, Inc. and is protected under U.S. and
    // international copyright and other intellectual property
    // laws.
    //
    // DISCLAIMER
    // This disclaimer is not a license and does not grant any
    // rights to the materials distributed herewith. Except as
    // otherwise provided in a valid license issued to you by
    // Xilinx, and to the maximum extent permitted by applicable
    // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
    // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
    // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
    // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
    // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
    // (2) Xilinx shall not be liable (whether in contract or tort,
    // including negligence, or under any other theory of
    // liability) for any loss or damage of any kind or nature
    // related to, arising under or in connection with these
    // materials, including for any direct, or any indirect,
    // special, incidental, or consequential loss or damage
    // (including loss of data, profits, goodwill, or any type of
    // loss or damage suffered as a result of any action brought
    // by a third party) even if such damage or loss was
    // reasonably foreseeable or Xilinx had been advised of the
    // possibility of the same.
    //
    // CRITICAL APPLICATIONS
    // Xilinx products are not designed or intended to be fail-
    // safe, or for use in any application requiring fail-safe
    // performance, such as life-support or safety devices or
    // systems, Class III medical devices, nuclear facilities,
    // applications related to the deployment of airbags, or any
    // other applications that could lead to death, personal
    // injury, or severe property or environmental damage
    // (individually and collectively, "Critical
    // Applications"). Customer assumes the sole risk and
    // liability of any use of Xilinx products in Critical
    // Applications, subject only to applicable laws and
    // regulations governing limitations on product liability.
    //
    // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
    // PART OF THIS FILE AT ALL TIMES.
    //------------------------------------------------------------------------------
    `timescale 1ps/1ps
    // =====================================================================================================================
    // This example design wrapper module instantiates the core and any helper blocks which the user chose to exclude from
    // the core, connects them as appropriate, and maps enabled ports
    // =====================================================================================================================
    module wr_gth_wrapper_example_wrapper (
    input wire [0:0] gthrxn_in
    ,input wire [0:0] gthrxp_in
    ,output wire [0:0] gthtxn_out
    ,output wire [0:0] gthtxp_out
    ,input wire [0:0] gtwiz_userclk_tx_reset_in
    ,output wire [0:0] gtwiz_userclk_tx_srcclk_out
    ,output wire [0:0] gtwiz_userclk_tx_usrclk_out
    ,output wire [0:0] gtwiz_userclk_tx_usrclk2_out
    ,output wire [0:0] gtwiz_userclk_tx_active_out
    ,input wire [0:0] gtwiz_userclk_rx_reset_in
    ,output wire [0:0] gtwiz_userclk_rx_srcclk_out
    ,output wire [0:0] gtwiz_userclk_rx_usrclk_out
    ,output wire [0:0] gtwiz_userclk_rx_usrclk2_out
    ,output wire [0:0] gtwiz_userclk_rx_active_out
    ,input wire [0:0] gtwiz_buffbypass_tx_reset_in
    ,input wire [0:0] gtwiz_buffbypass_tx_start_user_in
    ,output wire [0:0] gtwiz_buffbypass_tx_done_out
    ,output wire [0:0] gtwiz_buffbypass_tx_error_out
    ,input wire [0:0] gtwiz_buffbypass_rx_reset_in
    ,input wire [0:0] gtwiz_buffbypass_rx_start_user_in
    ,output wire [0:0] gtwiz_buffbypass_rx_done_out
    ,output wire [0:0] gtwiz_buffbypass_rx_error_out
    ,input wire [0:0] gtwiz_reset_clk_freerun_in
    ,input wire [0:0] gtwiz_reset_all_in
    ,input wire [0:0] gtwiz_reset_tx_pll_and_datapath_in
    ,input wire [0:0] gtwiz_reset_tx_datapath_in
    ,input wire [0:0] gtwiz_reset_rx_pll_and_datapath_in
    ,input wire [0:0] gtwiz_reset_rx_datapath_in
    ,output wire [0:0] gtwiz_reset_rx_cdr_stable_out
    ,output wire [0:0] gtwiz_reset_tx_done_out
    ,output wire [0:0] gtwiz_reset_rx_done_out
    ,input wire [15:0] gtwiz_userdata_tx_in
    ,output wire [15:0] gtwiz_userdata_rx_out
    ,input wire [0:0] drpclk_in
    ,input wire [0:0] gtrefclk0_in
    ,input wire [0:0] rx8b10ben_in
    ,input wire [0:0] rxcommadeten_in
    ,input wire [0:0] rxmcommaalignen_in
    ,input wire [0:0] rxpcommaalignen_in
    ,input wire [0:0] rxslide_in
    ,input wire [0:0] tx8b10ben_in
    ,input wire [15:0] txctrl0_in
    ,input wire [15:0] txctrl1_in
    ,input wire [7:0] txctrl2_in
    ,output wire [0:0] rxbyteisaligned_out
    ,output wire [0:0] rxbyterealign_out
    ,output wire [0:0] rxcommadet_out
    ,output wire [15:0] rxctrl0_out
    ,output wire [15:0] rxctrl1_out
    ,output wire [7:0] rxctrl2_out
    ,output wire [7:0] rxctrl3_out
    ,output wire [0:0] rxpmaresetdone_out
    ,output wire [0:0] txpmaresetdone_out
    );
    // ===================================================================================================================
    // PARAMETERS AND FUNCTIONS
    // ===================================================================================================================
    // Declare and initialize local parameters and functions used for HDL generation
    localparam [191:0] P_CHANNEL_ENABLE = 192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000;
    `define INCLUDE_WRAPPER_FUNCTIONS 1
    `include "wr_gth_wrapper_example_wrapper_functions.v"
    localparam integer P_TX_MASTER_CH_PACKED_IDX = f_calc_pk_mc_idx(8);
    localparam integer P_RX_MASTER_CH_PACKED_IDX = f_calc_pk_mc_idx(8);
    // ===================================================================================================================
    // HELPER BLOCKS
    // ===================================================================================================================
    // Any helper blocks which the user chose to exclude from the core will appear below. In addition, some signal
    // assignments related to optionally-enabled ports may appear below.
    // -------------------------------------------------------------------------------------------------------------------
    // Transmitter user clocking network helper block
    // -------------------------------------------------------------------------------------------------------------------
    wire [0:0] txusrclk_int;
    wire [0:0] txusrclk2_int;
    wire [0:0] txoutclk_int;
    // Generate a single module instance which is driven by a clock source associated with the master transmitter channel,
    // and which drives TXUSRCLK and TXUSRCLK2 for all channels
    // The source clock is TXOUTCLK from the master transmitter channel
    assign gtwiz_userclk_tx_srcclk_out = txoutclk_int[P_TX_MASTER_CH_PACKED_IDX];
    // Instantiate a single instance of the transmitter user clocking network helper block
    wr_gth_wrapper_example_gtwiz_userclk_tx gtwiz_userclk_tx_inst (
    .gtwiz_userclk_tx_srcclk_in (gtwiz_userclk_tx_srcclk_out),
    .gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_in),
    .gtwiz_userclk_tx_usrclk_out (gtwiz_userclk_tx_usrclk_out),
    .gtwiz_userclk_tx_usrclk2_out (gtwiz_userclk_tx_usrclk2_out),
    .gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_out)
    );
    // Drive TXUSRCLK and TXUSRCLK2 for all channels with the respective helper block outputs
    assign txusrclk_int = {1{gtwiz_userclk_tx_usrclk_out}};
    assign txusrclk2_int = {1{gtwiz_userclk_tx_usrclk2_out}};
    // -------------------------------------------------------------------------------------------------------------------
    // Receiver user clocking network helper block
    // -------------------------------------------------------------------------------------------------------------------
    wire [0:0] rxusrclk_int;
    wire [0:0] rxusrclk2_int;
    wire [0:0] rxoutclk_int;
    // Generate a single module instance which is driven by a clock source associated with the master receiver channel,
    // and which drives RXUSRCLK and RXUSRCLK2 for all channels
    // The source clock is RXOUTCLK from the master receiver channel
    assign gtwiz_userclk_rx_srcclk_out = rxoutclk_int[P_RX_MASTER_CH_PACKED_IDX];
    // Instantiate a single instance of the receiver user clocking network helper block
    wr_gth_wrapper_example_gtwiz_userclk_rx gtwiz_userclk_rx_inst (
    .gtwiz_userclk_rx_srcclk_in (gtwiz_userclk_rx_srcclk_out),
    .gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_in),
    .gtwiz_userclk_rx_usrclk_out (gtwiz_userclk_rx_usrclk_out),
    .gtwiz_userclk_rx_usrclk2_out (gtwiz_userclk_rx_usrclk2_out),
    .gtwiz_userclk_rx_active_out (gtwiz_userclk_rx_active_out)
    );
    // Drive RXUSRCLK and RXUSRCLK2 for all channels with the respective helper block outputs
    assign rxusrclk_int = {1{gtwiz_userclk_rx_usrclk_out}};
    assign rxusrclk2_int = {1{gtwiz_userclk_rx_usrclk2_out}};
    // ----------------------------------------------------------------------------------------------------------------
    // Assignments to expose data ports, or data control ports, per configuration requirement or user request
    // ----------------------------------------------------------------------------------------------------------------
    wire [15:0] txctrl0_int;
    // Required assignment to expose the TXCTRL0 port per configuration requirement or user request
    assign txctrl0_int = txctrl0_in;
    wire [15:0] txctrl1_int;
    // Required assignment to expose the TXCTRL1 port per configuration requirement or user request
    assign txctrl1_int = txctrl1_in;
    wire [15:0] rxctrl0_int;
    // Required assignment to expose the RXCTRL0 port per configuration requirement or user request
    assign rxctrl0_out = rxctrl0_int;
    wire [15:0] rxctrl1_int;
    // Required assignment to expose the RXCTRL1 port per configuration requirement or user request
    assign rxctrl1_out = rxctrl1_int;
    // ===================================================================================================================
    // CORE INSTANCE
    // ===================================================================================================================
    // Instantiate the core, mapping its enabled ports to example design ports and helper blocks as appropriate
    wr_gth_wrapper wr_gth_wrapper_inst (
    .gthrxn_in (gthrxn_in)
    ,.gthrxp_in (gthrxp_in)
    ,.gthtxn_out (gthtxn_out)
    ,.gthtxp_out (gthtxp_out)
    ,.gtwiz_userclk_tx_active_in (gtwiz_userclk_tx_active_out)
    ,.gtwiz_userclk_rx_active_in (gtwiz_userclk_rx_active_out)
    ,.gtwiz_buffbypass_tx_reset_in (gtwiz_buffbypass_tx_reset_in)
    ,.gtwiz_buffbypass_tx_start_user_in (gtwiz_buffbypass_tx_start_user_in)
    ,.gtwiz_buffbypass_tx_done_out (gtwiz_buffbypass_tx_done_out)
    ,.gtwiz_buffbypass_tx_error_out (gtwiz_buffbypass_tx_error_out)
    ,.gtwiz_buffbypass_rx_reset_in (gtwiz_buffbypass_rx_reset_in)
    ,.gtwiz_buffbypass_rx_start_user_in (gtwiz_buffbypass_rx_start_user_in)
    ,.gtwiz_buffbypass_rx_done_out (gtwiz_buffbypass_rx_done_out)
    ,.gtwiz_buffbypass_rx_error_out (gtwiz_buffbypass_rx_error_out)
    ,.gtwiz_reset_clk_freerun_in (gtwiz_reset_clk_freerun_in)
    ,.gtwiz_reset_all_in (gtwiz_reset_all_in)
    ,.gtwiz_reset_tx_pll_and_datapath_in (gtwiz_reset_tx_pll_and_datapath_in)
    ,.gtwiz_reset_tx_datapath_in (gtwiz_reset_tx_datapath_in)
    ,.gtwiz_reset_rx_pll_and_datapath_in (gtwiz_reset_rx_pll_and_datapath_in)
    ,.gtwiz_reset_rx_datapath_in (gtwiz_reset_rx_datapath_in)
    ,.gtwiz_reset_rx_cdr_stable_out (gtwiz_reset_rx_cdr_stable_out)
    ,.gtwiz_reset_tx_done_out (gtwiz_reset_tx_done_out)
    ,.gtwiz_reset_rx_done_out (gtwiz_reset_rx_done_out)
    ,.gtwiz_userdata_tx_in (gtwiz_userdata_tx_in)
    ,.gtwiz_userdata_rx_out (gtwiz_userdata_rx_out)
    ,.drpclk_in (drpclk_in)
    ,.gtrefclk0_in (gtrefclk0_in)
    ,.rx8b10ben_in (rx8b10ben_in)
    ,.rxcommadeten_in (rxcommadeten_in)
    ,.rxmcommaalignen_in (rxmcommaalignen_in)
    ,.rxpcommaalignen_in (rxpcommaalignen_in)
    ,.rxslide_in (rxslide_in)
    ,.rxusrclk_in (rxusrclk_int)
    ,.rxusrclk2_in (rxusrclk2_int)
    ,.tx8b10ben_in (tx8b10ben_in)
    ,.txctrl0_in (txctrl0_int)
    ,.txctrl1_in (txctrl1_int)
    ,.txctrl2_in (txctrl2_in)
    ,.txusrclk_in (txusrclk_int)
    ,.txusrclk2_in (txusrclk2_int)
    ,.rxbyteisaligned_out (rxbyteisaligned_out)
    ,.rxbyterealign_out (rxbyterealign_out)
    ,.rxcommadet_out (rxcommadet_out)
    ,.rxctrl0_out (rxctrl0_int)
    ,.rxctrl1_out (rxctrl1_int)
    ,.rxctrl2_out (rxctrl2_out)
    ,.rxctrl3_out (rxctrl3_out)
    ,.rxoutclk_out (rxoutclk_int)
    ,.rxpmaresetdone_out (rxpmaresetdone_out)
    ,.txoutclk_out (txoutclk_int)
    ,.txpmaresetdone_out (txpmaresetdone_out)
    );
    endmodule
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_wrapper_functions.v 0 → 100644
    View file @ d5952890
    //------------------------------------------------------------------------------
    // (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
    //
    // This file contains confidential and proprietary information
    // of Xilinx, Inc. and is protected under U.S. and
    // international copyright and other intellectual property
    // laws.
    //
    // DISCLAIMER
    // This disclaimer is not a license and does not grant any
    // rights to the materials distributed herewith. Except as
    // otherwise provided in a valid license issued to you by
    // Xilinx, and to the maximum extent permitted by applicable
    // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
    // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
    // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
    // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
    // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
    // (2) Xilinx shall not be liable (whether in contract or tort,
    // including negligence, or under any other theory of
    // liability) for any loss or damage of any kind or nature
    // related to, arising under or in connection with these
    // materials, including for any direct, or any indirect,
    // special, incidental, or consequential loss or damage
    // (including loss of data, profits, goodwill, or any type of
    // loss or damage suffered as a result of any action brought
    // by a third party) even if such damage or loss was
    // reasonably foreseeable or Xilinx had been advised of the
    // possibility of the same.
    //
    // CRITICAL APPLICATIONS
    // Xilinx products are not designed or intended to be fail-
    // safe, or for use in any application requiring fail-safe
    // performance, such as life-support or safety devices or
    // systems, Class III medical devices, nuclear facilities,
    // applications related to the deployment of airbags, or any
    // other applications that could lead to death, personal
    // injury, or severe property or environmental damage
    // (individually and collectively, "Critical
    // Applications"). Customer assumes the sole risk and
    // liability of any use of Xilinx products in Critical
    // Applications, subject only to applicable laws and
    // regulations governing limitations on product liability.
    //
    // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
    // PART OF THIS FILE AT ALL TIMES.
    //------------------------------------------------------------------------------
    `ifdef INCLUDE_WRAPPER_FUNCTIONS
    // =====================================================================================================================
    // This file contains functions available for example design HDL generation as required
    // =====================================================================================================================
    // Function to populate a bit mapping of enabled transceiver common blocks to transceiver quads
    function [47:0] f_pop_cm_en (
    input integer in_null
    );
    begin : main_f_pop_cm_en
    integer i;
    reg [47:0] tmp;
    for (i = 0; i < 192; i = i + 4) begin
    if ((P_CHANNEL_ENABLE[i] == 1'b1) ||
    (P_CHANNEL_ENABLE[i+1] == 1'b1) ||
    (P_CHANNEL_ENABLE[i+2] == 1'b1) ||
    (P_CHANNEL_ENABLE[i+3] == 1'b1))
    tmp[i/4] = 1'b1;
    else
    tmp[i/4] = 1'b0;
    end
    f_pop_cm_en = tmp;
    end
    endfunction
    // Function to calculate a pointer to a master channel's packed index
    function integer f_calc_pk_mc_idx (
    input integer idx_mc
    );
    begin : main_f_calc_pk_mc_idx
    integer i, j;
    integer tmp;
    j = 0;
    for (i = 0; i < 192; i = i + 1) begin
    if (P_CHANNEL_ENABLE[i] == 1'b1) begin
    if (i == idx_mc)
    tmp = j;
    else
    j = j + 1;
    end
    end
    f_calc_pk_mc_idx = tmp;
    end
    endfunction
    // Function to calculate the upper bound of a transceiver common-related signal within a packed vector, for a given
    // signal width and unpacked common index
    function integer f_ub_cm (
    input integer width,
    input integer index
    );
    begin : main_f_ub_cm
    integer i, j;
    j = 0;
    for (i = 0; i <= index; i = i + 4) begin
    if (P_CHANNEL_ENABLE[i] == 1'b1 ||
    P_CHANNEL_ENABLE[i+1] == 1'b1 ||
    P_CHANNEL_ENABLE[i+2] == 1'b1 ||
    P_CHANNEL_ENABLE[i+3] == 1'b1)
    j = j + 1;
    end
    f_ub_cm = (width * j) - 1;
    end
    endfunction
    // Function to calculate the lower bound of a transceiver common-related signal within a packed vector, for a given
    // signal width and unpacked common index
    function integer f_lb_cm (
    input integer width,
    input integer index
    );
    begin : main_f_lb_cm
    integer i, j;
    j = 0;
    for (i = 0; i < index; i = i + 4) begin
    if (P_CHANNEL_ENABLE[i] == 1'b1 ||
    P_CHANNEL_ENABLE[i+1] == 1'b1 ||
    P_CHANNEL_ENABLE[i+2] == 1'b1 ||
    P_CHANNEL_ENABLE[i+3] == 1'b1)
    j = j + 1;
    end
    f_lb_cm = (width * j);
    end
    endfunction
    // Function to calculate the packed vector index of a transceiver common, provided the packed vector index of the
    // associated transceiver channel
    function integer f_idx_cm (
    input integer index
    );
    begin : main_f_idx_cm
    integer i, j, k, flag, result;
    j = 0;
    k = 0;
    flag = 0;
    for (i = 0; (i < 192) && (flag == 0); i = i + 4) begin
    if (P_CHANNEL_ENABLE[i] == 1'b1 ||
    P_CHANNEL_ENABLE[i+1] == 1'b1 ||
    P_CHANNEL_ENABLE[i+2] == 1'b1 ||
    P_CHANNEL_ENABLE[i+3] == 1'b1) begin
    k = k + 1;
    if (P_CHANNEL_ENABLE[i+3] == 1'b1)
    j = j + 1;
    if (P_CHANNEL_ENABLE[i+2] == 1'b1)
    j = j + 1;
    if (P_CHANNEL_ENABLE[i+1] == 1'b1)
    j = j + 1;
    if (P_CHANNEL_ENABLE[i] == 1'b1)
    j = j + 1;
    end
    if (j >= (index + 1)) begin
    flag = 1;
    result = k;
    end
    end
    f_idx_cm = result - 1;
    end
    endfunction
    // Function to calculate the packed vector index of the upper bound transceiver channel which is associated with the
    // provided transceiver common packed vector index
    function integer f_idx_ch_ub (
    input integer index
    );
    begin : main_f_idx_ch_ub
    integer i, j, k, flag, result;
    j = 0;
    k = 0;
    flag = 0;
    for (i = 0; (i < 192) && (flag == 0); i = i + 4) begin
    if (P_CHANNEL_ENABLE[i] == 1'b1 ||
    P_CHANNEL_ENABLE[i+1] == 1'b1 ||
    P_CHANNEL_ENABLE[i+2] == 1'b1 ||
    P_CHANNEL_ENABLE[i+3] == 1'b1) begin
    k = k + 1;
    if (P_CHANNEL_ENABLE[i] == 1'b1)
    j = j + 1;
    if (P_CHANNEL_ENABLE[i+1] == 1'b1)
    j = j + 1;
    if (P_CHANNEL_ENABLE[i+2] == 1'b1)
    j = j + 1;
    if (P_CHANNEL_ENABLE[i+3] == 1'b1)
    j = j + 1;
    if (k == index + 1) begin
    flag = 1;
    result = j;
    end
    end
    end
    f_idx_ch_ub = result - 1;
    end
    endfunction
    // Function to calculate the packed vector index of the lower bound transceiver channel which is associated with the
    // provided transceiver common packed vector index
    function integer f_idx_ch_lb (
    input integer index
    );
    begin : main_f_idx_ch_lb
    integer i, j, k, flag, result;
    j = 0;
    k = 0;
    flag = 0;
    for (i = 0; (i < 192) && (flag == 0); i = i + 4) begin
    if (P_CHANNEL_ENABLE[i] == 1'b1 ||
    P_CHANNEL_ENABLE[i+1] == 1'b1 ||
    P_CHANNEL_ENABLE[i+2] == 1'b1 ||
    P_CHANNEL_ENABLE[i+3] == 1'b1) begin
    k = k + 1;
    if (k == index + 1) begin
    flag = 1;
    result = j + 1;
    end
    else begin
    if (P_CHANNEL_ENABLE[i] == 1'b1)
    j = j + 1;
    if (P_CHANNEL_ENABLE[i+1] == 1'b1)
    j = j + 1;
    if (P_CHANNEL_ENABLE[i+2] == 1'b1)
    j = j + 1;
    if (P_CHANNEL_ENABLE[i+3] == 1'b1)
    j = j + 1;
    end
    end
    end
    f_idx_ch_lb = result - 1;
    end
    endfunction
    `endif
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_gthe3_channel_wrapper.v 0 → 100644
    View file @ d5952890
    This source diff could not be displayed because it is too large. You can view the blob instead.
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_gtwizard_gthe3.v 0 → 100644
    View file @ d5952890
    This source diff could not be displayed because it is too large. You can view the blob instead.
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_gtwizard_top.v 0 → 100644
    View file @ d5952890
    This source diff could not be displayed because it is too large. You can view the blob instead.
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