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Commit d5952890 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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platform/xilinx/wr_gtp_phy: added Vivado-generated wrapper files for GTHE3

parent 28191b5a
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    platform/xilinx/wr_gtp_phy/Manifest.py
    View file @ d5952890
    ......@@ -2,6 +2,55 @@ files = [
    "gtp_bitslide.vhd",
    ];
    xilinx_ip_gthe3 = [
    "xilinx-ip/gthe3/gtwizard_ultrascale_v1_6_gthe3_channel.v",
    "xilinx-ip/gthe3/wr_gth_wrapper_gthe3_channel_wrapper.v",
    "xilinx-ip/gthe3/wr_gth_wrapper_example_wrapper.v",
    "xilinx-ip/gthe3/wr_gth_wrapper_example_bit_sync.v",
    "xilinx-ip/gthe3/wr_gth_wrapper_example_wrapper_functions.v",
    "xilinx-ip/gthe3/wr_gth_wrapper.v",
    "xilinx-ip/gthe3/wr_gth_wrapper_gtwizard_top.v",
    "xilinx-ip/gthe3/wr_gth_wrapper_example_top.v",
    "xilinx-ip/gthe3/wr_gth_wrapper_gtwizard_gthe3.v",
    "xilinx-ip/gthe3/wr_gth_wrapper_example_reset_sync.v",
    "xilinx-ip/gthe3/wr_gth_wrapper_example_gtwiz_userclk_tx.v",
    "xilinx-ip/gthe3/wr_gth_wrapper_example_init.v",
    "xilinx-ip/gthe3/wr_gth_wrapper_example_gtwiz_userclk_rx.v"
    ];
    xilinx_ip_gthe4 = [
    "xilinx-ip/gthe4/gtwizard_ultrascale_2.v",
    "xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_top.v",
    "xilinx-ip/gthe4/gtwizard_ultrascale_2.xdc",
    "xilinx-ip/gthe4/gtwizard_ultrascale_2_gthe4_channel_wrapper.v",
    "xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_gthe4.v",
    "xilinx-ip/gthe4/gtwizard_ultrascale_2_ooc.xdc",
    "xilinx-ip/gthe4/gtwizard_ultrascale_v1_7_gthe4_channel.v"
    ];
    xilinx_ip_common = [
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_bit_sync.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_reset.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gte4_drp_arb.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_reset_inv_sync.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_reset_sync.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v",
    "xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v"
    ];
    if (syn_device[0:4].upper()=="XC6S"): # Spartan6
    files.extend(["spartan6/wr_gtp_phy_spartan6.vhd",
    "spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd",
    ......@@ -49,7 +98,9 @@ elif (syn_device[0:4].upper()=="XCKU"): # Kintex Ultrascale GTH
    "family7-gthe3/wr_gthe3_rx_buffer_bypass.vhd",
    "family7-gthe3/wr_gthe3_tx_buffer_bypass.vhd",
    "family7-gthe3/wr_gthe3_wrapper.vhd",
    "family7-gthe3/gc_reset_synchronizer.vhd" ]);
    "family7-gthe3/gc_reset_synchronizer.vhd" ])
    files.extend( xilinx_ip_gthe3 );
    files.extend( xilinx_ip_common );
    elif (syn_device[0:4].upper()=="XCZU"): # Zynq Ultrascale GTH
    files.extend(["family7-gthe4/wr_gthe4_phy_family7.vhd",
    "family7-gthe4/wr_gthe4_phy_family7_xilinx_ip.vhd",
    ......@@ -58,27 +109,6 @@ elif (syn_device[0:4].upper()=="XCZU"): # Zynq Ultrascale GTH
    "family7-gthe4/wr_gthe4_tx_buffer_bypass.vhd",
    "family7-gthe4/wr_gthe4_wrapper.vhd",
    "family7-gthe4/gc_reset_synchronizer.vhd",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_bit_sync.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_reset.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gte4_drp_arb.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_reset_inv_sync.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_reset_sync.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v",
    "family7-gthe4/gthe4/common/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v",
    "family7-gthe4/gthe4/synth/gtwizard_ultrascale_2.v",
    "family7-gthe4/gthe4/synth/gtwizard_ultrascale_2_gtwizard_top.v",
    "family7-gthe4/gthe4/synth/gtwizard_ultrascale_2_gthe4_channel_wrapper.v",
    "family7-gthe4/gthe4/synth/gtwizard_ultrascale_2_gtwizard_gthe4.v",
    "family7-gthe4/gthe4/synth/gtwizard_ultrascale_v1_7_gthe4_channel.v"
    ]);
    files.extend( xilinx_ip_gthe4 );
    files.extend( xilinx_ip_common );
    platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4/Manifest.py deleted 100644 → 0
    View file @ 28191b5a
    files = ["common/gtwizard_ultrascale_v1_7_bit_sync.v",
    "common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v",
    "common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v",
    "common/gtwizard_ultrascale_v1_7_gtwiz_reset.v",
    "common/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v",
    "common/gtwizard_ultrascale_v1_7_gte4_drp_arb.v",
    "common/gtwizard_ultrascale_v1_7_reset_inv_sync.v",
    "common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v",
    "common/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v",
    "common/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v",
    "common/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v",
    "common/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v",
    "common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v",
    "common/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v",
    "common/gtwizard_ultrascale_v1_7_reset_sync.v",
    "common/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v",
    "common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v",
    "common/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v",
    "synth/gtwizard_ultrascale_2.v",
    "synth/gtwizard_ultrascale_2_gtwizard_top.v",
    "synth/gtwizard_ultrascale_2_gthe4_channel_wrapper.v",
    "synth/gtwizard_ultrascale_2_gtwizard_gthe4.v",
    "synth/gtwizard_ultrascale_v1_7_gthe4_channel.v"];
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/gtwizard_ultrascale_v1_6_gthe3_channel.v 0 → 100755
    View file @ d5952890
    This source diff could not be displayed because it is too large. You can view the blob instead.
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper.v 0 → 100644
    View file @ d5952890
    This diff is collapsed.
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_bit_sync.v 0 → 100644
    View file @ d5952890
    //------------------------------------------------------------------------------
    // (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
    //
    // This file contains confidential and proprietary information
    // of Xilinx, Inc. and is protected under U.S. and
    // international copyright and other intellectual property
    // laws.
    //
    // DISCLAIMER
    // This disclaimer is not a license and does not grant any
    // rights to the materials distributed herewith. Except as
    // otherwise provided in a valid license issued to you by
    // Xilinx, and to the maximum extent permitted by applicable
    // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
    // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
    // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
    // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
    // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
    // (2) Xilinx shall not be liable (whether in contract or tort,
    // including negligence, or under any other theory of
    // liability) for any loss or damage of any kind or nature
    // related to, arising under or in connection with these
    // materials, including for any direct, or any indirect,
    // special, incidental, or consequential loss or damage
    // (including loss of data, profits, goodwill, or any type of
    // loss or damage suffered as a result of any action brought
    // by a third party) even if such damage or loss was
    // reasonably foreseeable or Xilinx had been advised of the
    // possibility of the same.
    //
    // CRITICAL APPLICATIONS
    // Xilinx products are not designed or intended to be fail-
    // safe, or for use in any application requiring fail-safe
    // performance, such as life-support or safety devices or
    // systems, Class III medical devices, nuclear facilities,
    // applications related to the deployment of airbags, or any
    // other applications that could lead to death, personal
    // injury, or severe property or environmental damage
    // (individually and collectively, "Critical
    // Applications"). Customer assumes the sole risk and
    // liability of any use of Xilinx products in Critical
    // Applications, subject only to applicable laws and
    // regulations governing limitations on product liability.
    //
    // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
    // PART OF THIS FILE AT ALL TIMES.
    //------------------------------------------------------------------------------
    `timescale 1ps/1ps
    // *********************************************************************************************************************
    // IMPORTANT
    // This block is delivered within the example design. If you wish to modify its behavior, be careful to understand the
    // existing behavior and the effects of any modifications you may choose to make.
    // *********************************************************************************************************************
    module wr_gth_wrapper_example_bit_synchronizer # (
    parameter INITIALIZE = 5'b00000,
    parameter FREQUENCY = 512
    )(
    input wire clk_in,
    input wire i_in,
    output wire o_out
    );
    // Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to
    // enable clustering. Their GSR default values are provided by the INITIALIZE parameter.
    (* ASYNC_REG = "TRUE" *) reg i_in_meta = INITIALIZE[0];
    (* ASYNC_REG = "TRUE" *) reg i_in_sync1 = INITIALIZE[1];
    (* ASYNC_REG = "TRUE" *) reg i_in_sync2 = INITIALIZE[2];
    (* ASYNC_REG = "TRUE" *) reg i_in_sync3 = INITIALIZE[3];
    reg i_in_out = INITIALIZE[4];
    always @(posedge clk_in) begin
    i_in_meta <= i_in;
    i_in_sync1 <= i_in_meta;
    i_in_sync2 <= i_in_sync1;
    i_in_sync3 <= i_in_sync2;
    i_in_out <= i_in_sync3;
    end
    assign o_out = i_in_out;
    endmodule
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_gtwiz_userclk_rx.v 0 → 100644
    View file @ d5952890
    //------------------------------------------------------------------------------
    // (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
    //
    // This file contains confidential and proprietary information
    // of Xilinx, Inc. and is protected under U.S. and
    // international copyright and other intellectual property
    // laws.
    //
    // DISCLAIMER
    // This disclaimer is not a license and does not grant any
    // rights to the materials distributed herewith. Except as
    // otherwise provided in a valid license issued to you by
    // Xilinx, and to the maximum extent permitted by applicable
    // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
    // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
    // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
    // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
    // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
    // (2) Xilinx shall not be liable (whether in contract or tort,
    // including negligence, or under any other theory of
    // liability) for any loss or damage of any kind or nature
    // related to, arising under or in connection with these
    // materials, including for any direct, or any indirect,
    // special, incidental, or consequential loss or damage
    // (including loss of data, profits, goodwill, or any type of
    // loss or damage suffered as a result of any action brought
    // by a third party) even if such damage or loss was
    // reasonably foreseeable or Xilinx had been advised of the
    // possibility of the same.
    //
    // CRITICAL APPLICATIONS
    // Xilinx products are not designed or intended to be fail-
    // safe, or for use in any application requiring fail-safe
    // performance, such as life-support or safety devices or
    // systems, Class III medical devices, nuclear facilities,
    // applications related to the deployment of airbags, or any
    // other applications that could lead to death, personal
    // injury, or severe property or environmental damage
    // (individually and collectively, "Critical
    // Applications"). Customer assumes the sole risk and
    // liability of any use of Xilinx products in Critical
    // Applications, subject only to applicable laws and
    // regulations governing limitations on product liability.
    //
    // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
    // PART OF THIS FILE AT ALL TIMES.
    //------------------------------------------------------------------------------
    `timescale 1ps/1ps
    // *********************************************************************************************************************
    // IMPORTANT
    // This helper block was chosen for exclusion from the IP core, and is therefore delivered within the example design.
    // However, it is still customized for the chosen core configuration. If you wish to modify its behavior, refer to this
    // core's Product Guide for possible guidance and be careful to understand the existing behavior and the effects of any
    // modifications you may choose to make.
    // *********************************************************************************************************************
    module wr_gth_wrapper_example_gtwiz_userclk_rx #(
    parameter integer P_CONTENTS = 0,
    parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK = 1,
    parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK2 = 1
    )(
    input wire gtwiz_userclk_rx_srcclk_in,
    input wire gtwiz_userclk_rx_reset_in,
    output wire gtwiz_userclk_rx_usrclk_out,
    output wire gtwiz_userclk_rx_usrclk2_out,
    output wire gtwiz_userclk_rx_active_out
    );
    // -------------------------------------------------------------------------------------------------------------------
    // Local parameters
    // -------------------------------------------------------------------------------------------------------------------
    // Convert integer parameters with known, limited legal range to a 3-bit local parameter values
    localparam integer P_USRCLK_INT_DIV = P_FREQ_RATIO_SOURCE_TO_USRCLK - 1;
    localparam [2:0] P_USRCLK_DIV = P_USRCLK_INT_DIV[2:0];
    localparam integer P_USRCLK2_INT_DIV = (P_FREQ_RATIO_SOURCE_TO_USRCLK * P_FREQ_RATIO_USRCLK_TO_USRCLK2) - 1;
    localparam [2:0] P_USRCLK2_DIV = P_USRCLK2_INT_DIV[2:0];
    // -------------------------------------------------------------------------------------------------------------------
    // Receiver user clocking network conditional generation, based on parameter values in module instantiation
    // -------------------------------------------------------------------------------------------------------------------
    generate if (1) begin: gen_gtwiz_userclk_rx_main
    // Use BUFG_GT instance(s) to drive RXUSRCLK and RXUSRCLK2, inferred for integral source to RXUSRCLK frequency ratio
    if (P_CONTENTS == 0) begin
    // Drive RXUSRCLK with BUFG_GT-buffered source clock, dividing the input by the integral source clock to RXUSRCLK
    // frequency ratio
    BUFG_GT bufg_gt_usrclk_inst (
    .CE (1'b1),
    .CEMASK (1'b0),
    .CLR (gtwiz_userclk_rx_reset_in),
    .CLRMASK (1'b0),
    .DIV (P_USRCLK_DIV),
    .I (gtwiz_userclk_rx_srcclk_in),
    .O (gtwiz_userclk_rx_usrclk_out)
    );
    // If RXUSRCLK and RXUSRCLK2 frequencies are identical, drive both from the same BUFG_GT. Otherwise, drive
    // RXUSRCLK2 from a second BUFG_GT instance, dividing the source clock down to the RXUSRCLK2 frequency.
    if (P_FREQ_RATIO_USRCLK_TO_USRCLK2 == 1)
    assign gtwiz_userclk_rx_usrclk2_out = gtwiz_userclk_rx_usrclk_out;
    else begin
    BUFG_GT bufg_gt_usrclk2_inst (
    .CE (1'b1),
    .CEMASK (1'b0),
    .CLR (gtwiz_userclk_rx_reset_in),
    .CLRMASK (1'b0),
    .DIV (P_USRCLK2_DIV),
    .I (gtwiz_userclk_rx_srcclk_in),
    .O (gtwiz_userclk_rx_usrclk2_out)
    );
    end
    // Indicate active helper block functionality when the BUFG_GT divider is not held in reset
    (* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_rx_active_meta = 1'b0;
    (* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_rx_active_sync = 1'b0;
    always @(posedge gtwiz_userclk_rx_usrclk2_out, posedge gtwiz_userclk_rx_reset_in) begin
    if (gtwiz_userclk_rx_reset_in) begin
    gtwiz_userclk_rx_active_meta <= 1'b0;
    gtwiz_userclk_rx_active_sync <= 1'b0;
    end
    else begin
    gtwiz_userclk_rx_active_meta <= 1'b1;
    gtwiz_userclk_rx_active_sync <= gtwiz_userclk_rx_active_meta;
    end
    end
    assign gtwiz_userclk_rx_active_out = gtwiz_userclk_rx_active_sync;
    end
    end
    endgenerate
    endmodule
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_gtwiz_userclk_tx.v 0 → 100644
    View file @ d5952890
    //------------------------------------------------------------------------------
    // (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
    //
    // This file contains confidential and proprietary information
    // of Xilinx, Inc. and is protected under U.S. and
    // international copyright and other intellectual property
    // laws.
    //
    // DISCLAIMER
    // This disclaimer is not a license and does not grant any
    // rights to the materials distributed herewith. Except as
    // otherwise provided in a valid license issued to you by
    // Xilinx, and to the maximum extent permitted by applicable
    // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
    // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
    // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
    // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
    // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
    // (2) Xilinx shall not be liable (whether in contract or tort,
    // including negligence, or under any other theory of
    // liability) for any loss or damage of any kind or nature
    // related to, arising under or in connection with these
    // materials, including for any direct, or any indirect,
    // special, incidental, or consequential loss or damage
    // (including loss of data, profits, goodwill, or any type of
    // loss or damage suffered as a result of any action brought
    // by a third party) even if such damage or loss was
    // reasonably foreseeable or Xilinx had been advised of the
    // possibility of the same.
    //
    // CRITICAL APPLICATIONS
    // Xilinx products are not designed or intended to be fail-
    // safe, or for use in any application requiring fail-safe
    // performance, such as life-support or safety devices or
    // systems, Class III medical devices, nuclear facilities,
    // applications related to the deployment of airbags, or any
    // other applications that could lead to death, personal
    // injury, or severe property or environmental damage
    // (individually and collectively, "Critical
    // Applications"). Customer assumes the sole risk and
    // liability of any use of Xilinx products in Critical
    // Applications, subject only to applicable laws and
    // regulations governing limitations on product liability.
    //
    // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
    // PART OF THIS FILE AT ALL TIMES.
    //------------------------------------------------------------------------------
    `timescale 1ps/1ps
    // *********************************************************************************************************************
    // IMPORTANT
    // This helper block was chosen for exclusion from the IP core, and is therefore delivered within the example design.
    // However, it is still customized for the chosen core configuration. If you wish to modify its behavior, refer to this
    // core's Product Guide for possible guidance and be careful to understand the existing behavior and the effects of any
    // modifications you may choose to make.
    // *********************************************************************************************************************
    module wr_gth_wrapper_example_gtwiz_userclk_tx #(
    parameter integer P_CONTENTS = 0,
    parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK = 2,
    parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK2 = 1
    )(
    input wire gtwiz_userclk_tx_srcclk_in,
    input wire gtwiz_userclk_tx_reset_in,
    output wire gtwiz_userclk_tx_usrclk_out,
    output wire gtwiz_userclk_tx_usrclk2_out,
    output wire gtwiz_userclk_tx_active_out
    );
    // -------------------------------------------------------------------------------------------------------------------
    // Local parameters
    // -------------------------------------------------------------------------------------------------------------------
    // Convert integer parameters with known, limited legal range to a 3-bit local parameter values
    localparam integer P_USRCLK_INT_DIV = P_FREQ_RATIO_SOURCE_TO_USRCLK - 1;
    localparam [2:0] P_USRCLK_DIV = P_USRCLK_INT_DIV[2:0];
    localparam integer P_USRCLK2_INT_DIV = (P_FREQ_RATIO_SOURCE_TO_USRCLK * P_FREQ_RATIO_USRCLK_TO_USRCLK2) - 1;
    localparam [2:0] P_USRCLK2_DIV = P_USRCLK2_INT_DIV[2:0];
    // -------------------------------------------------------------------------------------------------------------------
    // Transmitter user clocking network conditional generation, based on parameter values in module instantiation
    // -------------------------------------------------------------------------------------------------------------------
    generate if (1) begin: gen_gtwiz_userclk_tx_main
    // Use BUFG_GT instance(s) to drive TXUSRCLK and TXUSRCLK2, inferred for integral source to TXUSRCLK frequency ratio
    if (P_CONTENTS == 0) begin
    // Drive TXUSRCLK with BUFG_GT-buffered source clock, dividing the input by the integral source clock to TXUSRCLK
    // frequency ratio
    BUFG_GT bufg_gt_usrclk_inst (
    .CE (1'b1),
    .CEMASK (1'b0),
    .CLR (gtwiz_userclk_tx_reset_in),
    .CLRMASK (1'b0),
    .DIV (P_USRCLK_DIV),
    .I (gtwiz_userclk_tx_srcclk_in),
    .O (gtwiz_userclk_tx_usrclk_out)
    );
    // If TXUSRCLK and TXUSRCLK2 frequencies are identical, drive both from the same BUFG_GT. Otherwise, drive
    // TXUSRCLK2 from a second BUFG_GT instance, dividing the source clock down to the TXUSRCLK2 frequency.
    if (P_FREQ_RATIO_USRCLK_TO_USRCLK2 == 1)
    assign gtwiz_userclk_tx_usrclk2_out = gtwiz_userclk_tx_usrclk_out;
    else begin
    BUFG_GT bufg_gt_usrclk2_inst (
    .CE (1'b1),
    .CEMASK (1'b0),
    .CLR (gtwiz_userclk_tx_reset_in),
    .CLRMASK (1'b0),
    .DIV (P_USRCLK2_DIV),
    .I (gtwiz_userclk_tx_srcclk_in),
    .O (gtwiz_userclk_tx_usrclk2_out)
    );
    end
    // Indicate active helper block functionality when the BUFG_GT divider is not held in reset
    (* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_tx_active_meta = 1'b0;
    (* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_tx_active_sync = 1'b0;
    always @(posedge gtwiz_userclk_tx_usrclk2_out, posedge gtwiz_userclk_tx_reset_in) begin
    if (gtwiz_userclk_tx_reset_in) begin
    gtwiz_userclk_tx_active_meta <= 1'b0;
    gtwiz_userclk_tx_active_sync <= 1'b0;
    end
    else begin
    gtwiz_userclk_tx_active_meta <= 1'b1;
    gtwiz_userclk_tx_active_sync <= gtwiz_userclk_tx_active_meta;
    end
    end
    assign gtwiz_userclk_tx_active_out = gtwiz_userclk_tx_active_sync;
    end
    end
    endgenerate
    endmodule
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_reset_sync.v 0 → 100644
    View file @ d5952890
    //------------------------------------------------------------------------------
    // (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
    //
    // This file contains confidential and proprietary information
    // of Xilinx, Inc. and is protected under U.S. and
    // international copyright and other intellectual property
    // laws.
    //
    // DISCLAIMER
    // This disclaimer is not a license and does not grant any
    // rights to the materials distributed herewith. Except as
    // otherwise provided in a valid license issued to you by
    // Xilinx, and to the maximum extent permitted by applicable
    // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
    // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
    // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
    // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
    // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
    // (2) Xilinx shall not be liable (whether in contract or tort,
    // including negligence, or under any other theory of
    // liability) for any loss or damage of any kind or nature
    // related to, arising under or in connection with these
    // materials, including for any direct, or any indirect,
    // special, incidental, or consequential loss or damage
    // (including loss of data, profits, goodwill, or any type of
    // loss or damage suffered as a result of any action brought
    // by a third party) even if such damage or loss was
    // reasonably foreseeable or Xilinx had been advised of the
    // possibility of the same.
    //
    // CRITICAL APPLICATIONS
    // Xilinx products are not designed or intended to be fail-
    // safe, or for use in any application requiring fail-safe
    // performance, such as life-support or safety devices or
    // systems, Class III medical devices, nuclear facilities,
    // applications related to the deployment of airbags, or any
    // other applications that could lead to death, personal
    // injury, or severe property or environmental damage
    // (individually and collectively, "Critical
    // Applications"). Customer assumes the sole risk and
    // liability of any use of Xilinx products in Critical
    // Applications, subject only to applicable laws and
    // regulations governing limitations on product liability.
    //
    // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
    // PART OF THIS FILE AT ALL TIMES.
    //------------------------------------------------------------------------------
    `timescale 1ps/1ps
    // *********************************************************************************************************************
    // IMPORTANT
    // This block is delivered within the example design. If you wish to modify its behavior, be careful to understand the
    // existing behavior and the effects of any modifications you may choose to make.
    // *********************************************************************************************************************
    module wr_gth_wrapper_example_reset_synchronizer # (
    parameter FREQUENCY = 512
    )(
    input wire clk_in,
    input wire rst_in,
    output wire rst_out
    );
    // Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to
    // enable clustering. Each flip-flop in the synchronizer is asynchronously reset so that the downstream logic is also
    // asynchronously reset but encounters no reset assertion latency. The removal of reset is synchronous, so that the
    // downstream logic is also removed from reset synchronously. This module is designed for active-high reset use.
    (* ASYNC_REG = "TRUE" *) reg rst_in_meta = 1'b0;
    (* ASYNC_REG = "TRUE" *) reg rst_in_sync1 = 1'b0;
    (* ASYNC_REG = "TRUE" *) reg rst_in_sync2 = 1'b0;
    (* ASYNC_REG = "TRUE" *) reg rst_in_sync3 = 1'b0;
    reg rst_in_out = 1'b0;
    always @(posedge clk_in, posedge rst_in) begin
    if (rst_in) begin
    rst_in_meta <= 1'b1;
    rst_in_sync1 <= 1'b1;
    rst_in_sync2 <= 1'b1;
    rst_in_sync3 <= 1'b1;
    rst_in_out <= 1'b1;
    end
    else begin
    rst_in_meta <= 1'b0;
    rst_in_sync1 <= rst_in_meta;
    rst_in_sync2 <= rst_in_sync1;
    rst_in_sync3 <= rst_in_sync2;
    rst_in_out <= rst_in_sync3;
    end
    end
    assign rst_out = rst_in_out;
    endmodule
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_wrapper_functions.v 0 → 100644
    View file @ d5952890
    //------------------------------------------------------------------------------
    // (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
    //
    // This file contains confidential and proprietary information
    // of Xilinx, Inc. and is protected under U.S. and
    // international copyright and other intellectual property
    // laws.
    //
    // DISCLAIMER
    // This disclaimer is not a license and does not grant any
    // rights to the materials distributed herewith. Except as
    // otherwise provided in a valid license issued to you by
    // Xilinx, and to the maximum extent permitted by applicable
    // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
    // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
    // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
    // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
    // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
    // (2) Xilinx shall not be liable (whether in contract or tort,
    // including negligence, or under any other theory of
    // liability) for any loss or damage of any kind or nature
    // related to, arising under or in connection with these
    // materials, including for any direct, or any indirect,
    // special, incidental, or consequential loss or damage
    // (including loss of data, profits, goodwill, or any type of
    // loss or damage suffered as a result of any action brought
    // by a third party) even if such damage or loss was
    // reasonably foreseeable or Xilinx had been advised of the
    // possibility of the same.
    //
    // CRITICAL APPLICATIONS
    // Xilinx products are not designed or intended to be fail-
    // safe, or for use in any application requiring fail-safe
    // performance, such as life-support or safety devices or
    // systems, Class III medical devices, nuclear facilities,
    // applications related to the deployment of airbags, or any
    // other applications that could lead to death, personal
    // injury, or severe property or environmental damage
    // (individually and collectively, "Critical
    // Applications"). Customer assumes the sole risk and
    // liability of any use of Xilinx products in Critical
    // Applications, subject only to applicable laws and
    // regulations governing limitations on product liability.
    //
    // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
    // PART OF THIS FILE AT ALL TIMES.
    //------------------------------------------------------------------------------
    `ifdef INCLUDE_WRAPPER_FUNCTIONS
    // =====================================================================================================================
    // This file contains functions available for example design HDL generation as required
    // =====================================================================================================================
    // Function to populate a bit mapping of enabled transceiver common blocks to transceiver quads
    function [47:0] f_pop_cm_en (
    input integer in_null
    );
    begin : main_f_pop_cm_en
    integer i;
    reg [47:0] tmp;
    for (i = 0; i < 192; i = i + 4) begin
    if ((P_CHANNEL_ENABLE[i] == 1'b1) ||
    (P_CHANNEL_ENABLE[i+1] == 1'b1) ||
    (P_CHANNEL_ENABLE[i+2] == 1'b1) ||
    (P_CHANNEL_ENABLE[i+3] == 1'b1))
    tmp[i/4] = 1'b1;
    else
    tmp[i/4] = 1'b0;
    end
    f_pop_cm_en = tmp;
    end
    endfunction
    // Function to calculate a pointer to a master channel's packed index
    function integer f_calc_pk_mc_idx (
    input integer idx_mc
    );
    begin : main_f_calc_pk_mc_idx
    integer i, j;
    integer tmp;
    j = 0;
    for (i = 0; i < 192; i = i + 1) begin
    if (P_CHANNEL_ENABLE[i] == 1'b1) begin
    if (i == idx_mc)
    tmp = j;
    else
    j = j + 1;
    end
    end
    f_calc_pk_mc_idx = tmp;
    end
    endfunction
    // Function to calculate the upper bound of a transceiver common-related signal within a packed vector, for a given
    // signal width and unpacked common index
    function integer f_ub_cm (
    input integer width,
    input integer index
    );
    begin : main_f_ub_cm
    integer i, j;
    j = 0;
    for (i = 0; i <= index; i = i + 4) begin
    if (P_CHANNEL_ENABLE[i] == 1'b1 ||
    P_CHANNEL_ENABLE[i+1] == 1'b1 ||
    P_CHANNEL_ENABLE[i+2] == 1'b1 ||
    P_CHANNEL_ENABLE[i+3] == 1'b1)
    j = j + 1;
    end
    f_ub_cm = (width * j) - 1;
    end
    endfunction
    // Function to calculate the lower bound of a transceiver common-related signal within a packed vector, for a given
    // signal width and unpacked common index
    function integer f_lb_cm (
    input integer width,
    input integer index
    );
    begin : main_f_lb_cm
    integer i, j;
    j = 0;
    for (i = 0; i < index; i = i + 4) begin
    if (P_CHANNEL_ENABLE[i] == 1'b1 ||
    P_CHANNEL_ENABLE[i+1] == 1'b1 ||
    P_CHANNEL_ENABLE[i+2] == 1'b1 ||
    P_CHANNEL_ENABLE[i+3] == 1'b1)
    j = j + 1;
    end
    f_lb_cm = (width * j);
    end
    endfunction
    // Function to calculate the packed vector index of a transceiver common, provided the packed vector index of the
    // associated transceiver channel
    function integer f_idx_cm (
    input integer index
    );
    begin : main_f_idx_cm
    integer i, j, k, flag, result;
    j = 0;
    k = 0;
    flag = 0;
    for (i = 0; (i < 192) && (flag == 0); i = i + 4) begin
    if (P_CHANNEL_ENABLE[i] == 1'b1 ||
    P_CHANNEL_ENABLE[i+1] == 1'b1 ||
    P_CHANNEL_ENABLE[i+2] == 1'b1 ||
    P_CHANNEL_ENABLE[i+3] == 1'b1) begin
    k = k + 1;
    if (P_CHANNEL_ENABLE[i+3] == 1'b1)
    j = j + 1;
    if (P_CHANNEL_ENABLE[i+2] == 1'b1)
    j = j + 1;
    if (P_CHANNEL_ENABLE[i+1] == 1'b1)
    j = j + 1;
    if (P_CHANNEL_ENABLE[i] == 1'b1)
    j = j + 1;
    end
    if (j >= (index + 1)) begin
    flag = 1;
    result = k;
    end
    end
    f_idx_cm = result - 1;
    end
    endfunction
    // Function to calculate the packed vector index of the upper bound transceiver channel which is associated with the
    // provided transceiver common packed vector index
    function integer f_idx_ch_ub (
    input integer index
    );
    begin : main_f_idx_ch_ub
    integer i, j, k, flag, result;
    j = 0;
    k = 0;
    flag = 0;
    for (i = 0; (i < 192) && (flag == 0); i = i + 4) begin
    if (P_CHANNEL_ENABLE[i] == 1'b1 ||
    P_CHANNEL_ENABLE[i+1] == 1'b1 ||
    P_CHANNEL_ENABLE[i+2] == 1'b1 ||
    P_CHANNEL_ENABLE[i+3] == 1'b1) begin
    k = k + 1;
    if (P_CHANNEL_ENABLE[i] == 1'b1)
    j = j + 1;
    if (P_CHANNEL_ENABLE[i+1] == 1'b1)
    j = j + 1;
    if (P_CHANNEL_ENABLE[i+2] == 1'b1)
    j = j + 1;
    if (P_CHANNEL_ENABLE[i+3] == 1'b1)
    j = j + 1;
    if (k == index + 1) begin
    flag = 1;
    result = j;
    end
    end
    end
    f_idx_ch_ub = result - 1;
    end
    endfunction
    // Function to calculate the packed vector index of the lower bound transceiver channel which is associated with the
    // provided transceiver common packed vector index
    function integer f_idx_ch_lb (
    input integer index
    );
    begin : main_f_idx_ch_lb
    integer i, j, k, flag, result;
    j = 0;
    k = 0;
    flag = 0;
    for (i = 0; (i < 192) && (flag == 0); i = i + 4) begin
    if (P_CHANNEL_ENABLE[i] == 1'b1 ||
    P_CHANNEL_ENABLE[i+1] == 1'b1 ||
    P_CHANNEL_ENABLE[i+2] == 1'b1 ||
    P_CHANNEL_ENABLE[i+3] == 1'b1) begin
    k = k + 1;
    if (k == index + 1) begin
    flag = 1;
    result = j + 1;
    end
    else begin
    if (P_CHANNEL_ENABLE[i] == 1'b1)
    j = j + 1;
    if (P_CHANNEL_ENABLE[i+1] == 1'b1)
    j = j + 1;
    if (P_CHANNEL_ENABLE[i+2] == 1'b1)
    j = j + 1;
    if (P_CHANNEL_ENABLE[i+3] == 1'b1)
    j = j + 1;
    end
    end
    end
    f_idx_ch_lb = result - 1;
    end
    endfunction
    `endif
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_gthe3_channel_wrapper.v 0 → 100644
    View file @ d5952890
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