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White Rabbit core collection
Commit d4590b9d authored by A. Hahn's avatar A. Hahn
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platform: added det phy for arria 10

parent d6db884f
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Showing with 146482 additions and 39 deletions
platform/altera/wr_altera_pkg.vhd
View file @ d4590b9d
......@@ -189,19 +189,45 @@ package wr_altera_pkg is
component wr_arria10_e3p1_transceiver is
generic (
g_use_atx_pll : boolean := TRUE);
g_use_atx_pll : boolean := true;
g_use_cmu_pll : boolean := false;
g_use_det_phy : boolean := true;
g_use_sfp_los_rst : boolean := true;
g_use_tx_lcr_dbg : boolean := false;
g_use_rx_lcr_dbg : boolean := false;
g_use_ext_loop : boolean := true;
g_use_ext_rst : boolean := true);
port (
clk_ref_i : in std_logic := '0';
ready_o : out std_logic := '0';
drop_link_i : in std_logic;
tx_clk_o : out std_logic;
tx_data_i : in std_logic_vector(7 downto 0):= (others => '0');
tx_ready_o : out std_logic := '0';
rx_clk_o : out std_logic;
rx_data_o : out std_logic_vector(7 downto 0);
rx_ready_o : out std_logic;
pad_txp_o : out std_logic;
pad_rxp_i : in std_logic := '0'
clk_ref_i : in std_logic := '0';
clk_phy_i : in std_logic := '0';
reconfig_write_i : in std_logic_vector(0 downto 0) := (others => '0');
reconfig_read_i : in std_logic_vector(0 downto 0) := (others => '0');
reconfig_address_i : in std_logic_vector(9 downto 0) := (others => '0');
reconfig_writedata_i : in std_logic_vector(31 downto 0) := (others => '0');
reconfig_readdata_o : out std_logic_vector(31 downto 0);
reconfig_waitrequest_o : out std_logic_vector(0 downto 0);
reconfig_clk_i : in std_logic_vector(0 downto 0) := (others => '0');
reconfig_reset_i : in std_logic_vector(0 downto 0) := (others => '0');
ready_o : out std_logic := '0';
drop_link_i : in std_logic;
loopen_i : in std_logic;
sfp_los_i : in std_logic;
tx_clk_o : out std_logic;
tx_data_i : in std_logic_vector(7 downto 0):= (others => '0');
tx_data_k_i : in std_logic;
tx_ready_o : out std_logic := '0';
tx_disparity_o : out std_logic := '0';
tx_enc_err_o : out std_logic := '0';
rx_clk_o : out std_logic;
rx_data_o : out std_logic_vector(7 downto 0);
rx_ready_o : out std_logic;
rx_data_k_o : out std_logic;
rx_enc_err_o : out std_logic;
rx_bitslide_o : out std_logic_vector(3 downto 0);
debug_o : out std_logic;
debug_i : in std_logic_vector(7 downto 0):= (others => '0');
pad_txp_o : out std_logic;
pad_rxp_i : in std_logic := '0'
);
end component wr_arria10_e3p1_transceiver;
......@@ -259,6 +285,49 @@ package wr_altera_pkg is
);
end component wr_arria10_e3p1_phy;
component wr_arria10_e3p1_det_phy is
port (
reconfig_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- write
reconfig_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- read
reconfig_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
reconfig_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
reconfig_readdata : out std_logic_vector(31 downto 0); -- readdata
reconfig_waitrequest : out std_logic_vector(0 downto 0); -- waitrequest
reconfig_clk : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk
reconfig_reset : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset
rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
rx_cdr_refclk0 : in std_logic := 'X'; -- clk
rx_clkout : out std_logic_vector(0 downto 0); -- clk
rx_coreclkin : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk
rx_datak : out std_logic; -- rx_datak
rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
rx_disperr : out std_logic; -- rx_disperr
rx_errdetect : out std_logic; -- rx_errdetect
rx_is_lockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
rx_is_lockedtoref : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref
rx_parallel_data : out std_logic_vector(7 downto 0); -- rx_parallel_data
rx_patterndetect : out std_logic; -- rx_patterndetect
rx_runningdisp : out std_logic; -- rx_runningdisp
rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
rx_std_bitslipboundarysel : out std_logic_vector(4 downto 0); -- rx_std_bitslipboundarysel
rx_std_wa_patternalign : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_std_wa_patternalign
rx_syncstatus : out std_logic; -- rx_syncstatus
tx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_analogreset
tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy
tx_clkout : out std_logic_vector(0 downto 0); -- clk
tx_coreclkin : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk
tx_datak : in std_logic := 'X'; -- tx_datak
tx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_digitalreset
tx_parallel_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- tx_parallel_data
tx_serial_clk0 : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk
tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data
unused_rx_parallel_data : out std_logic_vector(113 downto 0); -- unused_rx_parallel_data
unused_tx_parallel_data : in std_logic_vector(118 downto 0) := (others => 'X'); -- unused_tx_parallel_data
rx_seriallpbken : in std_logic_vector(0 downto 0) := (others => 'X') -- rx_seriallpbken
);
end component wr_arria10_e3p1_det_phy;
component wr_arria10_scu4_transceiver is
generic (
g_use_atx_pll : boolean := TRUE);
......
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/.qsys_edit/filters.xml 0 → 100644
View file @ d4590b9d
<?xml version="1.0" encoding="UTF-8"?>
<filters version="18.1" />
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/.qsys_edit/preferences.xml 0 → 100644
View file @ d4590b9d
<?xml version="1.0" encoding="UTF-8"?>
<preferences>
<debug showDebugMenu="0" />
<systemtable filter="All Interfaces">
<columns>
<connections preferredWidth="47" />
<irq preferredWidth="34" />
</columns>
</systemtable>
<library expandedCategories="Library,Project" />
<window width="1100" height="800" x="1745" y="1408" />
</preferences>
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_det_phy/.qsys_edit/filters.xml 0 → 100644
View file @ d4590b9d
<?xml version="1.0" encoding="UTF-8"?>
<filters version="18.1" />
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_det_phy/.qsys_edit/preferences.xml 0 → 100644
View file @ d4590b9d
<?xml version="1.0" encoding="UTF-8"?>
<preferences>
<debug showDebugMenu="0" />
<systemtable filter="All Interfaces">
<columns>
<connections preferredWidth="31" />
<irq preferredWidth="34" />
</columns>
</systemtable>
<library expandedCategories="Project,Library" />
<window width="1949" height="1308" x="1440" y="1119" />
<generation path="" synthesis="VHDL" block_symbol_file="0" />
</preferences>
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_det_phy/.qsys_edit/wr_arria10_e3p1_det_phy_schematic.nlv 0 → 100644
View file @ d4590b9d
# # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35
#
preplace inst wr_arria10_e3p1_det_phy -pg 1 -lvl 1 -y 40 -regy -20
preplace inst wr_arria10_e3p1_det_phy.xcvr_native_a10_0 -pg 1 -lvl 1 -y 30
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)wr_arria10_e3p1_det_phy.tx_serial_data,(SLAVE)xcvr_native_a10_0.tx_serial_data) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)wr_arria10_e3p1_det_phy.rx_set_locktodata,(SLAVE)xcvr_native_a10_0.rx_set_locktodata) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)wr_arria10_e3p1_det_phy.rx_digitalreset,(SLAVE)xcvr_native_a10_0.rx_digitalreset) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)wr_arria10_e3p1_det_phy.reconfig_reset,(SLAVE)xcvr_native_a10_0.reconfig_reset) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)xcvr_native_a10_0.reconfig_avmm,(SLAVE)wr_arria10_e3p1_det_phy.reconfig_avmm) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)wr_arria10_e3p1_det_phy.tx_parallel_data,(SLAVE)xcvr_native_a10_0.tx_parallel_data) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)xcvr_native_a10_0.tx_cal_busy,(SLAVE)wr_arria10_e3p1_det_phy.tx_cal_busy) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)wr_arria10_e3p1_det_phy.rx_set_locktoref,(SLAVE)xcvr_native_a10_0.rx_set_locktoref) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)xcvr_native_a10_0.rx_is_lockedtoref,(SLAVE)wr_arria10_e3p1_det_phy.rx_is_lockedtoref) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)xcvr_native_a10_0.rx_clkout,(SLAVE)wr_arria10_e3p1_det_phy.rx_clkout) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)wr_arria10_e3p1_det_phy.unused_tx_parallel_data,(SLAVE)xcvr_native_a10_0.unused_tx_parallel_data) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)wr_arria10_e3p1_det_phy.rx_std_bitslipboundarysel,(SLAVE)xcvr_native_a10_0.rx_std_bitslipboundarysel) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)wr_arria10_e3p1_det_phy.rx_parallel_data,(SLAVE)xcvr_native_a10_0.rx_parallel_data) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)wr_arria10_e3p1_det_phy.rx_coreclkin,(SLAVE)xcvr_native_a10_0.rx_coreclkin) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)xcvr_native_a10_0.rx_is_lockedtodata,(SLAVE)wr_arria10_e3p1_det_phy.rx_is_lockedtodata) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)wr_arria10_e3p1_det_phy.unused_rx_parallel_data,(SLAVE)xcvr_native_a10_0.unused_rx_parallel_data) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)wr_arria10_e3p1_det_phy.rx_errdetect,(SLAVE)xcvr_native_a10_0.rx_errdetect) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)wr_arria10_e3p1_det_phy.rx_disperr,(SLAVE)xcvr_native_a10_0.rx_disperr) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)xcvr_native_a10_0.rx_datak,(SLAVE)wr_arria10_e3p1_det_phy.rx_datak) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)xcvr_native_a10_0.tx_serial_clk0,(SLAVE)wr_arria10_e3p1_det_phy.tx_serial_clk0) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)xcvr_native_a10_0.tx_digitalreset,(SLAVE)wr_arria10_e3p1_det_phy.tx_digitalreset) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)xcvr_native_a10_0.rx_std_wa_patternalign,(SLAVE)wr_arria10_e3p1_det_phy.rx_std_wa_patternalign) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)wr_arria10_e3p1_det_phy.rx_runningdisp,(SLAVE)xcvr_native_a10_0.rx_runningdisp) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)xcvr_native_a10_0.tx_datak,(SLAVE)wr_arria10_e3p1_det_phy.tx_datak) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)xcvr_native_a10_0.rx_cdr_refclk0,(SLAVE)wr_arria10_e3p1_det_phy.rx_cdr_refclk0) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)wr_arria10_e3p1_det_phy.rx_analogreset,(SLAVE)xcvr_native_a10_0.rx_analogreset) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)xcvr_native_a10_0.tx_coreclkin,(SLAVE)wr_arria10_e3p1_det_phy.tx_coreclkin) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)wr_arria10_e3p1_det_phy.reconfig_clk,(SLAVE)xcvr_native_a10_0.reconfig_clk) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)wr_arria10_e3p1_det_phy.tx_std_bitslipboundarysel,(SLAVE)xcvr_native_a10_0.tx_std_bitslipboundarysel) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)wr_arria10_e3p1_det_phy.tx_clkout,(SLAVE)xcvr_native_a10_0.tx_clkout) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)xcvr_native_a10_0.tx_analogreset,(SLAVE)wr_arria10_e3p1_det_phy.tx_analogreset) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)wr_arria10_e3p1_det_phy.rx_syncstatus,(SLAVE)xcvr_native_a10_0.rx_syncstatus) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)wr_arria10_e3p1_det_phy.rx_serial_data,(SLAVE)xcvr_native_a10_0.rx_serial_data) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)wr_arria10_e3p1_det_phy.rx_patterndetect,(SLAVE)xcvr_native_a10_0.rx_patterndetect) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_det_phy</net_container>(SLAVE)wr_arria10_e3p1_det_phy.rx_cal_busy,(SLAVE)xcvr_native_a10_0.rx_cal_busy) 1 0 1 NJ
levelinfo -pg 1 0 170 410
levelinfo -hier wr_arria10_e3p1_det_phy 180 210 400
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_det_phy/serv_req_info.txt 0 → 100644
View file @ d4590b9d
<internal_error>
<sub_system>ERR</sub_system>
<callstack>
0x7f1bfe9be171: ccl_err + 0x8171 (_ZN15ERR_STACKWALKER15get_stack_traceEPPKviiPv + 0xb1)
0x7f1bfe9c1015: ccl_err + 0xb015 (_Z14err_terminatorv + 0x4b)
0x7f1bf6390796: stdc++.so.6 + 0x63796 (_ZN10__cxxabiv111__terminateEPFvvE + 0x6)
0x7f1bf63907c3: stdc++.so.6 + 0x637c3
0x7f1bf6390a36: stdc++.so.6 + 0x63a36 (__cxa_rethrow + 0x46)
0x7f1c223e6b64: QtCore.so.4 + 0x1a5b64 (_ZN10QEventLoop4execE6QFlagsINS_17ProcessEventsFlagEE + 0x2f4)
0x7f1c223eb7c4: QtCore.so.4 + 0x1aa7c4 (_ZN16QCoreApplication4execEv + 0xb4)
0x401ea8: quartus + 0x1ea8 (_Z8qgq_mainiPPKc + 0x68)
0x7f1c01228720: ccl_msg + 0x40720 (_Z15msg_main_threadPv + 0x10)
0x7f1bfe58002c: ccl_thr + 0x602c (thr_final_wrapper + 0xc)
0x7f1c012287df: ccl_msg + 0x407df (_Z18msg_thread_wrapperPFPvS_ES_ + 0x62)
0x7f1bfebf1559: ccl_mem + 0xa559 (_Z18mem_thread_wrapperPFPvS_ES_ + 0x99)
0x7f1bfe9bef92: ccl_err + 0x8f92 (_Z18err_thread_wrapperPFPvS_ES_ + 0x27)
0x7f1bfe5803f2: ccl_thr + 0x63f2 (thr_thread_wrapper + 0x15)
0x7f1c0122a7e2: ccl_msg + 0x427e2 (_Z12msg_exe_mainiPPKcPFiiS1_E + 0xa3)
0x401f7a: quartus + 0x1f7a (main + 0x26)
0x7f1bf579bb97: c.so.6 + 0x21b97 (__libc_start_main + 0xe7)
0x401d59: quartus + 0x1d59
</callstack>
<error>*** Fatal Error: Unhandled Exception</error>
<date>Fri Apr 5 17:51:38 2019
</date>
<version>Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition</version>
</internal_error>
\ No newline at end of file
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_det_phy/wr_arria10_e3p1_det_phy/altera_xcvr_native_a10_181/synth/a10_avmm_h.sv 0 → 100644
View file @ d4590b9d
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps/1 ps
package a10_avmm_h;
// localparam to define unused bus
localparam RD_UNUSED = 8'h0;
// localparams for common capability registers
localparam A10_XR_ADDR_ID_0 = 9'h0;
localparam A10_XR_ADDR_ID_1 = 9'h1;
localparam A10_XR_ADDR_ID_2 = 9'h2;
localparam A10_XR_ADDR_ID_3 = 9'h3;
localparam A10_XR_ADDR_STATUS_EN = 9'h4;
localparam A10_XR_ADDR_CONTROL_EN = 9'h5;
// Reserve Address 9'h6 to 9'hF for common capablities
// native phy capability
localparam A10_XR_ADDR_NAT_CHNLS = 9'h10;
localparam A10_XR_ADDR_NAT_CHNL_NUM = 9'h11;
localparam A10_XR_ADDR_NAT_DUPLEX = 9'h12;
localparam A10_XR_ADDR_NAT_PRBS_EN = 9'h13;
localparam A10_XR_ADDR_NAT_ODI_EN = 9'h14;
// pll ip capability
localparam A10_XR_ADDR_PLL_MCGB_EN = 9'h10;
// localparams for csr for pll locked and cal busy
localparam A10_XR_ADDR_GP_PLL_LOCK = 9'h80;
localparam A10_XR_OFFSET_GP_LOCK = 0;
localparam A10_XR_OFFSET_GP_CAL_BUSY = 1;
localparam A10_XR_OFFSET_GP_AVMM_BUSY = 2;
localparam A10_XR_OFFSET_LOCK_UNUSED = 3;
localparam A10_XR_LOCK_UNUSED_LEN = 5;
// localparams for pll powerdown
localparam A10_XR_ADDR_GP_PLL_RST = 9'hE0;
localparam A10_XR_OFFSET_PLL_RST = 0;
localparam A10_XR_OFFSET_PLL_RST_OVR = 1;
localparam A10_XR_OFFSET_PLL_RST_UNUSED = 2;
localparam A10_XR_PLL_RST_UNUSED_LEN = 6;
// localparams for csr for lock to ref and lock to data
localparam A10_XR_ADDR_GP_RD_LTR = 9'h80;
localparam A10_XR_OFFSET_RD_LTD = 0;
localparam A10_XR_OFFSET_RD_LTR = 1;
localparam A10_XR_OFFSET_LTR_UNUSED = 2;
localparam A10_XR_LTR_UNUSED_LEN = 6;
// localparams for csr for cal busy
localparam A10_XR_ADDR_GP_CAL_BUSY = 9'h81;
localparam A10_XR_OFFSET_TX_CAL_BUSY = 0;
localparam A10_XR_OFFSET_RX_CAL_BUSY = 1;
localparam A10_XR_OFFSET_AVMM_BUSY = 2;
localparam A10_XR_OFFSET_CAL_DUMMY = 3;
localparam A10_XR_OFFSET_TX_CAL_MASK = 4;
localparam A10_XR_OFFSET_RX_CAL_MASK = 5;
localparam A10_XR_OFFSET_CAL_UNUSED = 6;
localparam A10_XR_CAL_UNUSED_LEN = 2;
// localparams for setting lock to ref and lock to data
localparam A10_XR_ADDR_GP_SET_LTR = 9'hE0;
localparam A10_XR_OFFSET_SET_LTD = 0;
localparam A10_XR_OFFSET_SET_LTR = 1;
localparam A10_XR_OFFSET_SET_LTD_OVR = 2;
localparam A10_XR_OFFSET_SET_LTR_OVR = 3;
localparam A10_XR_OFFSET_SET_LTR_UNUSED = 4;
localparam A10_XR_SET_LTR_UNUSED_LEN = 4;
// localparams for setting loopback
localparam A10_XR_ADDR_GP_LPBK = 9'hE1;
localparam A10_XR_OFFSET_LPBK = 0;
localparam A10_XR_OFFSET_LPBK_UNUSED = 1;
localparam A10_XR_LPBK_UNUSED_LEN = 7;
// localparams for setting channel resets
localparam A10_XR_ADDR_CHNL_RESET = 9'hE2;
localparam A10_XR_OFFSET_RX_ANA = 0;
localparam A10_XR_OFFSET_RX_DIG = 1;
localparam A10_XR_OFFSET_TX_ANA = 2;
localparam A10_XR_OFFSET_TX_DIG = 3;
localparam A10_XR_OFFSET_RX_ANA_OVR = 4;
localparam A10_XR_OFFSET_RX_DIG_OVR = 5;
localparam A10_XR_OFFSET_TX_ANA_OVR = 6;
localparam A10_XR_OFFSET_TX_DIG_OVR = 7;
// localparams for prbs addresses
localparam A10_XR_ADDR_PRBS_CTRL = 9'h100;
localparam A10_XR_ADDR_PRBS_ERR_0 = 9'h101;
localparam A10_XR_ADDR_PRBS_ERR_1 = 9'h102;
localparam A10_XR_ADDR_PRBS_ERR_2 = 9'h103;
localparam A10_XR_ADDR_PRBS_ERR_3 = 9'h104;
localparam A10_XR_ADDR_PRBS_ERR_4 = 9'h105;
localparam A10_XR_ADDR_PRBS_ERR_5 = 9'h106;
localparam A10_XR_ADDR_PRBS_ERR_6 = 9'h107;
localparam A10_XR_ADDR_PRBS_BIT_0 = 9'h10D;
localparam A10_XR_ADDR_PRBS_BIT_1 = 9'h10E;
localparam A10_XR_ADDR_PRBS_BIT_2 = 9'h10F;
localparam A10_XR_ADDR_PRBS_BIT_3 = 9'h110;
localparam A10_XR_ADDR_PRBS_BIT_4 = 9'h111;
localparam A10_XR_ADDR_PRBS_BIT_5 = 9'h112;
localparam A10_XR_ADDR_PRBS_BIT_6 = 9'h113;
// localparams for prbs bit offsets
localparam A10_XR_OFFSET_PRBS_EN = 0;
localparam A10_XR_OFFSET_PRBS_RESET = 1;
localparam A10_XR_OFFSET_PRBS_SNAP = 2;
localparam A10_XR_OFFSET_PRBS_DONE = 3;
localparam A10_XR_OFFSET_PRBS_UNUSED = 4;
localparam A10_XR_PRBS_UNUSED_LEN = 4;
// localparams for odi addresses
localparam A10_XR_ADDR_ODI_CTRL = 9'h120;
localparam A10_XR_ADDR_ODI_ERR_0 = 9'h121;
localparam A10_XR_ADDR_ODI_ERR_1 = 9'h122;
localparam A10_XR_ADDR_ODI_ERR_2 = 9'h123;
localparam A10_XR_ADDR_ODI_ERR_3 = 9'h124;
localparam A10_XR_ADDR_ODI_ERR_4 = 9'h125;
localparam A10_XR_ADDR_ODI_ERR_5 = 9'h126;
localparam A10_XR_ADDR_ODI_ERR_6 = 9'h127;
localparam A10_XR_ADDR_ODI_BIT_0 = 9'h12D;
localparam A10_XR_ADDR_ODI_BIT_1 = 9'h12E;
localparam A10_XR_ADDR_ODI_BIT_2 = 9'h12F;
localparam A10_XR_ADDR_ODI_BIT_3 = 9'h130;
localparam A10_XR_ADDR_ODI_BIT_4 = 9'h131;
localparam A10_XR_ADDR_ODI_BIT_5 = 9'h132;
localparam A10_XR_ADDR_ODI_BIT_6 = 9'h133;
// localparams for odi bit offsets
localparam A10_XR_OFFSET_ODI_EN = 0;
localparam A10_XR_OFFSET_ODI_RESET = 1;
localparam A10_XR_OFFSET_ODI_SNAP = 2;
localparam A10_XR_OFFSET_ODI_DONE = 3;
localparam A10_XR_OFFSET_ODI_UNUSED = 4;
localparam A10_XR_ODI_UNUSED_LEN = 4;
// localparams for embedded reconfig addresses
// Control reg and offsets
localparam A10_XR_ADDR_EMBED_RCFG_CTRL = 9'h140;
localparam A10_XR_OFFSET_EMBED_RCFG_CFG_SEL = 0;
localparam A10_XR_EMBED_RCFG_CFG_SEL_LEN = 6; //bits [5:0] are alloted for cfg_sel even though GUI currently only supports upto 8 profiles.
localparam A10_XR_OFFSET_EMBED_RCFG_BCAST_EN = 6;
localparam A10_XR_OFFSET_EMBED_RCFG_CFG_LOAD = 7;
// Status reg and offsets
localparam A10_XR_ADDR_EMBED_RCFG_STATUS = 9'h141;
localparam A10_XR_OFFSET_EMBED_RCFG_STRM_BUSY = 0;
endpackage
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_det_phy/wr_arria10_e3p1_det_phy/altera_xcvr_native_a10_181/synth/alt_xcvr_arbiter.sv 0 → 100644
View file @ d4590b9d
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Clocked priority encoder with state
//
// On each clock cycle, updates state to show which request is granted.
// Most recent grant holder is always the highest priority.
// If current grant holder is not making a request, while others are,
// then new grant holder is always the requester with lowest bit number.
// If no requests, current grant holder retains grant state
// $Header$
`timescale 1 ns / 1 ns
module alt_xcvr_arbiter #(
parameter width = 2
) (
input wire clock,
input wire [width-1:0] req, // req[n] requests for this cycle
output reg [width-1:0] grant // grant[n] means requester n is grantee in this cycle
);
wire idle; // idle when no requests
wire [width-1:0] keep; // keep[n] means requester n is requesting, and already has the grant
// Note: current grantee is always highest priority for next grant
wire [width-1:0] take; // take[n] means requester n is requesting, and there are no higher-priority requests
assign keep = req & grant; // current grantee is always highest priority for next grant
assign idle = ~| req; // idle when no requests
initial begin
grant = 0;
end
// grant next state depends on current grant and take priority
always @(posedge clock) begin
grant <=
// synthesis translate_off
(grant === {width{1'bx}})? {width{1'b0}} :
// synthesis translate_on
keep // if current grantee is requesting, gets to keep grant
| ({width{idle}} & grant) // if no requests, grant state remains unchanged
| take; // take applies only if current grantee is not requesting
end
// 'take' bus encodes priority. Request with lowest bit number wins when current grantee not requesting
assign take[0] = req[0]
& (~| (keep & ({width{1'b1}} << 1))); // no 'keep' from lower-priority inputs
genvar i;
generate
for (i=1; i < width; i = i + 1) begin : arb
assign take[i] = req[i]
& (~| (keep & ({width{1'b1}} << (i+1)))) // no 'keep' from lower-priority inputs
& (~| (req & {i{1'b1}})); // no 'req' from higher-priority inputs
end
endgenerate
endmodule
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_det_phy/wr_arria10_e3p1_det_phy/altera_xcvr_native_a10_181/synth/alt_xcvr_native_prbs_accum.sv 0 → 100644
View file @ d4590b9d
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps/1 ps
module alt_xcvr_native_prbs_accum (
input avmm_clk,
input avmm_reset,
// Control signals from CSR
input prbs_reset,
input prbs_snapshot,
input prbs_counter_en,
// Status signals from PRBS
output prbs_done_sync,
output [49:0] prbs_err_count,
output [49:0] prbs_bit_count,
// Signals from the transceiver
input rx_clkout,
input prbs_err_signal,
input prbs_done_signal
);
/**********************************************************************/
// wires for synchronizers
/**********************************************************************/
wire avmm_reset_sync;
wire prbs_reset_sync;
wire prbs_err_rx_sync;
wire prbs_done_rx_sync;
wire avmm_rx_cnt_edge_sync;
/**********************************************************************/
// Synchronizer for avmm_reset to rx_clkout
/**********************************************************************/
alt_xcvr_resync #(
.SYNC_CHAIN_LENGTH ( 3 ),
.WIDTH ( 1 ),
.INIT_VALUE ( 1 )
) rx_clk_reset_sync (
.clk (rx_clkout),
.reset (avmm_reset),
.d (1'b0),
.q (avmm_reset_sync)
);
/**********************************************************************/
// Synchronizer for prbs_reset to rx_clkout
/**********************************************************************/
alt_xcvr_resync #(
.SYNC_CHAIN_LENGTH ( 3 ),
.WIDTH ( 1 ),
.INIT_VALUE ( 1 )
) rx_clk_prbs_reset_sync (
.clk (rx_clkout),
.reset (prbs_reset),
.d (1'b0),
.q (prbs_reset_sync)
);
/**********************************************************************/
// Synchronizer for prbs_err to rx_clkout
/**********************************************************************/
alt_xcvr_resync #(
.SYNC_CHAIN_LENGTH ( 2 ),
.WIDTH ( 1 ),
.INIT_VALUE ( 0 )
) rx_clk_prbs_err_sync (
.clk (rx_clkout),
.reset (avmm_reset_sync),
.d (prbs_err_signal),
.q (prbs_err_rx_sync)
);
/**********************************************************************/
// Synchronizer for prbs_done to rx_clkout
/**********************************************************************/
alt_xcvr_resync #(
.SYNC_CHAIN_LENGTH ( 2 ),
.WIDTH ( 1 ),
.INIT_VALUE ( 0 )
) rx_clk_prbs_done_sync (
.clk (rx_clkout),
.reset (avmm_reset_sync),
.d (prbs_done_signal),
.q (prbs_done_rx_sync)
);
/**********************************************************************/
// wires and registers
/**********************************************************************/
wire rx_prbs_err_edge;
wire rx_prbs_cnt_edge;
wire avmm_prbs_cnt_edge;
reg rx_prbs_cnt_edge_reg;
reg rx_prbs_err_edge_reg;
reg avmm_prbs_cnt_edge_reg;
reg rx_error_high;
reg [3:0] rx_consecutive_error;
reg [7:0] rx_prbs_bit_count;
reg [7:0] rx_prbs_err_count;
reg [7:0] rx_prbs_err_snapshot;
reg [49:0] avmm_prbs_err_count;
reg [49:0] avmm_prbs_bit_count;
reg [49:0] avmm_prbs_err_snapshot;
reg [49:0] avmm_prbs_bit_snapshot;
/**********************************************************************/
// Logic on rx_clkout for accumulating bits and errors
/**********************************************************************/
assign rx_prbs_err_edge = (~rx_prbs_err_edge_reg && prbs_err_rx_sync);
assign rx_prbs_cnt_edge = (rx_prbs_cnt_edge_reg ^ rx_prbs_bit_count[7]);
always@(posedge rx_clkout or posedge avmm_reset_sync) begin
if(avmm_reset_sync) begin
rx_prbs_err_edge_reg <= 1'b0;
rx_prbs_cnt_edge_reg <= 1'b0;
rx_prbs_bit_count <= 8'b0;
rx_prbs_err_count <= 8'b0;
rx_prbs_err_snapshot <= 8'b0;
rx_consecutive_error <= 4'b0;
rx_error_high <= 1'b0;
end else if (prbs_reset_sync == 1'b1) begin
rx_prbs_err_edge_reg <= 1'b0;
rx_prbs_cnt_edge_reg <= 1'b0;
rx_prbs_bit_count <= 8'b0;
rx_prbs_err_count <= 8'b0;
rx_prbs_err_snapshot <= 8'b0;
rx_consecutive_error <= 4'b0;
rx_error_high <= 1'b0;
end else if (prbs_done_rx_sync == 1'b1) begin
// prbs error edge
rx_prbs_err_edge_reg <= prbs_err_rx_sync;
// prbs count edge
rx_prbs_cnt_edge_reg <= rx_prbs_bit_count[7];
// If the error signal is high for more than 7 cycles, constantly count errors
if(prbs_err_rx_sync == 1'b1) begin
if(&rx_consecutive_error) begin
rx_consecutive_error <= rx_consecutive_error;
end else begin
rx_consecutive_error <= rx_consecutive_error + 1'b1;
end
end else begin
rx_consecutive_error <= 4'b0;
end
rx_error_high <= (&rx_consecutive_error);
// error and bit accumulation
rx_prbs_bit_count <= rx_prbs_bit_count + 1'b1;
rx_prbs_err_count <= (rx_prbs_cnt_edge) ? {7'b0, rx_prbs_err_edge} : (rx_prbs_err_count + (rx_prbs_err_edge || rx_error_high));
rx_prbs_err_snapshot <= (rx_prbs_cnt_edge) ? rx_prbs_err_count : rx_prbs_err_snapshot;
end
end
/**********************************************************************/
// Synchronizer for prbs_done to avmm_clock
/**********************************************************************/
alt_xcvr_resync #(
.SYNC_CHAIN_LENGTH ( 3 ),
.WIDTH ( 1 )
) avmm_clk_prbs_done_sync (
.clk (avmm_clk),
.reset (avmm_reset),
.d (prbs_done_signal),
.q (prbs_done_sync)
);
/**********************************************************************/
// Synchronizer for bit_count edge to avmm_clock
/**********************************************************************/
alt_xcvr_resync #(
.SYNC_CHAIN_LENGTH ( 3 ),
.WIDTH ( 1 )
) avmm_clk_bit_count_edge (
.clk (avmm_clk),
.reset (avmm_reset),
.d (rx_prbs_cnt_edge_reg),
.q (avmm_rx_cnt_edge_sync)
);
/**********************************************************************/
// Logic for overall bit and error count in avmm_clk
/**********************************************************************/
assign prbs_err_count = avmm_prbs_err_snapshot;
assign prbs_bit_count = avmm_prbs_bit_snapshot;
assign avmm_prbs_cnt_edge = (avmm_prbs_cnt_edge_reg ^ avmm_rx_cnt_edge_sync);
always@(posedge avmm_clk or posedge avmm_reset) begin
if(avmm_reset) begin
avmm_prbs_bit_count <= 50'b0;
avmm_prbs_err_count <= 50'b0;
avmm_prbs_bit_snapshot <= 50'b0;
avmm_prbs_err_snapshot <= 50'b0;
avmm_prbs_cnt_edge_reg <= 1'b0;
end else if(prbs_reset) begin
avmm_prbs_bit_count <= 50'b0;
avmm_prbs_err_count <= 50'b0;
avmm_prbs_bit_snapshot <= 50'b0;
avmm_prbs_err_snapshot <= 50'b0;
avmm_prbs_cnt_edge_reg <= 1'b0;
end else if(prbs_counter_en) begin
avmm_prbs_cnt_edge_reg <= avmm_rx_cnt_edge_sync;
// on an edge of prbs count, accumulate the number of errors and bits
if(avmm_prbs_cnt_edge) begin
avmm_prbs_bit_count <= avmm_prbs_bit_count + 8'd128;
avmm_prbs_err_count <= avmm_prbs_err_count + rx_prbs_err_snapshot;
end else begin
avmm_prbs_bit_count <= avmm_prbs_bit_count;
avmm_prbs_err_count <= avmm_prbs_err_count;
end
// on a snapshot signal, capture the bit and error count to keep them in sync with each other
if(prbs_snapshot) begin
avmm_prbs_bit_snapshot <= avmm_prbs_bit_count;
avmm_prbs_err_snapshot <= avmm_prbs_err_count;
end else begin
avmm_prbs_bit_snapshot <= avmm_prbs_bit_snapshot;
avmm_prbs_err_snapshot <= avmm_prbs_err_snapshot;
end
end else begin
avmm_prbs_bit_count <= avmm_prbs_bit_count;
avmm_prbs_err_count <= avmm_prbs_err_count;
avmm_prbs_bit_snapshot <= avmm_prbs_bit_snapshot;
avmm_prbs_err_snapshot <= avmm_prbs_err_snapshot;
avmm_prbs_cnt_edge_reg <= avmm_prbs_cnt_edge_reg;
end
end
endmodule
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_det_phy/wr_arria10_e3p1_det_phy/altera_xcvr_native_a10_181/synth/alt_xcvr_native_rcfg_arb.sv 0 → 100644
View file @ d4590b9d
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps/1 ps
module alt_xcvr_native_rcfg_arb #(
parameter total_masters = 4,
parameter channels = 1,
parameter address_width = 10,
parameter data_width = 32
) (
// Basic AVMM inputs
input [channels-1:0] reconfig_clk,
input [channels-1:0] reconfig_reset,
// User AVMM input
input [channels-1:0] user_read,
input [channels-1:0] user_write,
input [channels*address_width-1:0] user_address,
input [channels*data_width-1:0] user_writedata,
input [channels-1:0] user_read_write,
output [channels-1:0] user_waitrequest,
// Reconfig Steamer AVMM input
input [channels-1:0] strm_read,
input [channels-1:0] strm_write,
input [channels*address_width-1:0] strm_address,
input [channels*data_width-1:0] strm_writedata,
input [channels-1:0] strm_read_write,
output [channels-1:0] strm_waitrequest,
// ODI AVMM input
input [channels-1:0] odi_read,
input [channels-1:0] odi_write,
input [channels*address_width-1:0] odi_address,
input [channels*data_width-1:0] odi_writedata,
input [channels-1:0] odi_read_write,
output [channels-1:0] odi_waitrequest,
// ADME AVMM input
input [channels-1:0] jtag_read,
input [channels-1:0] jtag_write,
input [channels*address_width-1:0] jtag_address,
input [channels*data_width-1:0] jtag_writedata,
input [channels-1:0] jtag_read_write,
output [channels-1:0] jtag_waitrequest,
// PCIe DFE IP
input [channels-1:0] pcie_dfe_read,
input [channels-1:0] pcie_dfe_write,
input [channels*address_width-1:0] pcie_dfe_address,
input [channels*data_width-1:0] pcie_dfe_writedata,
input [channels-1:0] pcie_dfe_read_write,
output [channels-1:0] pcie_dfe_waitrequest,
// AVMM output the channel and the CSR
input [channels-1:0] avmm_waitrequest,
output [channels-1:0] avmm_read,
output [channels-1:0] avmm_write,
output [channels*address_width-1:0] avmm_address,
output [channels*data_width-1:0] avmm_writedata
);
// General wires
wire [channels*total_masters-1:0] grant;
wire [channels-1:0] strm_grants;
wire [channels-1:0] user_read_write_lcl;
// Variables for the generate loops
genvar ig; // For bus widths
genvar jg; // For Channels
generate for(jg=0;jg<channels;jg=jg+1) begin: g_arb
/*********************************************************************/
// case: 309705
// Simulation fix. When the user inputs drive x at the beginning of simulation,
// then even after a reset, the grant will have been assigned a value of x.
// since there is a loopback in the RTL, the value will continue to be x,
// and gets reflected on avmm_readdata and avmm_waitrequest. once an avmm master
// requests a read or write, the x value for grant will correct itself.
/**********************************************************************/
assign user_read_write_lcl[jg] =
// synthesis translate_off
(user_read_write[jg] === 1'bx) ? 1'b0 :
// synthesis translate_on
user_read_write[jg];
/**********************************************************************/
// Per Instance instantiations and assignments
// Priority in decreasing order is embedded reconfig -> odi -> user AVMM -> JTAG
/**********************************************************************/
alt_xcvr_arbiter #(
.width (total_masters)
) arbiter_inst (
.clock (reconfig_clk[jg]),
.req ({jtag_read_write[jg], user_read_write_lcl[jg], odi_read_write[jg], strm_read_write[jg], pcie_dfe_read_write[jg]}),
.grant (grant[jg*total_masters+:total_masters])
);
// Assign the grant signal
assign strm_grants[jg] = grant[(jg*total_masters)+1];
// Use the grant as a mask for the varoius read and writs signals
// if you or them all together, it will generate the read/write request if any are high
// For streamer write/read condition - if broadcasting, wait for all channels to receive grant before asserting write/read
assign avmm_write[jg] = |(grant[jg*total_masters+:total_masters] & {jtag_write[jg], user_write[jg], odi_write[jg], ((~&strm_write | &strm_grants) & strm_write[jg]), pcie_dfe_write[jg]});
assign avmm_read[jg] = |(grant[jg*total_masters+:total_masters] & {jtag_read[jg], user_read[jg], odi_read[jg], ((~&strm_read | &strm_grants) & strm_read[jg]), pcie_dfe_read[jg]});
// Split the wait request, and if the grant is asserted to any one master, assert wait request to all others
assign {jtag_waitrequest[jg], user_waitrequest[jg], odi_waitrequest[jg], strm_waitrequest[jg], pcie_dfe_waitrequest[jg]} = (~grant[jg*total_masters+:total_masters] | {total_masters{avmm_waitrequest[jg]}});
// Since thse are busses, the logic must be done in a bit-wise fashion; hence the for loop
// Generate the address for the bus width
for(ig=0; ig<address_width;ig=ig+1) begin: g_avmm_address
assign avmm_address[jg*address_width + ig] = |(grant[jg*total_masters+:total_masters] & {jtag_address[jg*address_width + ig], user_address[jg*address_width + ig], odi_address[jg*address_width + ig], strm_address[jg*address_width + ig], pcie_dfe_address[jg*address_width + ig]});
end // End g_avmm_address
// Generate the write data for the bus width
for(ig=0; ig<data_width;ig=ig+1) begin: g_avmm_writdata
assign avmm_writedata[jg*data_width+ ig] = |(grant[jg*total_masters+:total_masters] & {jtag_writedata[jg*data_width + ig], user_writedata[jg*data_width + ig],odi_writedata[jg*data_width + ig], strm_writedata[jg*data_width + ig], pcie_dfe_writedata[jg*data_width + ig]});
end // End g_avmm_writedata
end //End for channel-wise for loop
endgenerate // End generate
endmodule
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_det_phy/wr_arria10_e3p1_det_phy/altera_xcvr_native_a10_181/synth/altera_xcvr_native_pcie_dfe_params_h.sv 0 → 100644
View file @ d4590b9d
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Revision 2.0
package altera_xcvr_native_pcie_dfe_params_h;
// Program Labels for Jumps
localparam PRGM_BEGIN = 1;
localparam PRGM_SW_GEN3 = 2;
localparam PRGM_PHASE2_CTLE = 3;
localparam PRGM_PHASE2_DFE = 4;
localparam PRGM_SW_GEN1_2 = 5;
localparam PRGM_RESTORE_MODEB = 6;
localparam PRGM_SKIP_MANUAL_DFE = 7;
localparam PRGM_SKIP_CONT_DFE = 8;
localparam PRGM_SKIP_DFE_LOAD = 9;
localparam PRGM_SKIP_DFE_HOLD = 10;
localparam PRGM_SKIP_DFE_MODE_8 = 11;
// Labels for PIO in
localparam NUM_PIO_IN = 7;
localparam PIO_IN_GO = 0;
localparam PIO_IN_SW_GEN_1_2 = 1;
localparam PIO_IN_SW_GEN_3 = 2;
localparam PIO_IN_RESTORE_MODEB = 3;
localparam PIO_IN_PHASE2_CTLE = 4;
localparam PIO_IN_PHASE2_DFE = 5;
localparam PIO_IN_CONTINUOUS_DFE= 6;
// Labels for PIO out
localparam NUM_PIO_OUT = 7;
localparam PIO_OUT_ERROR = 0;
localparam PIO_OUT_RUNNING = 1;
localparam PIO_OUT_SW_GEN_1_2 = 2;
localparam PIO_OUT_SW_GEN_3 = 3;
localparam PIO_OUT_RESTORE_MODEB= 4;
localparam PIO_OUT_PHASE2_CTLE = 5;
localparam PIO_OUT_PHASE2_DFE = 6;
// Static settings
localparam FORCE_JUMP = 1;
localparam GEN1_GEN2_CTLE_VAL = 32'h00;
// Test parameters
localparam TST_MUX_DELAY = 30;
localparam SLEEP_DELAY = 5;
// Parameters for indexing through mem
localparam NUM_ADDR_PER_CHNL = 12;
localparam INDX_ADDR_CTLE = 0;
localparam NUM_ADDR_CTLE = 1;
localparam INDX_ADDR_DFE = 1;
localparam NUM_ADDR_DFE = 11;
// Calibration status
localparam ADDR_CALIBRATION = 10'h103;
localparam BIT_CALIBRATION = 5;
// DFE IP States
localparam SM_POWERUP = 4'h0;
localparam SM_CHECK_CAL_STATUS = 4'h1;
localparam SM_IDLE = 4'h2;
localparam SM_EXECUTE_RATE_SW = 4'h3;
localparam SM_RESTORE_MODEB = 4'h4;
localparam SM_TIMEOUT_CTLE = 4'h5;
localparam SM_EXECUTE_CTLE = 4'h6;
localparam SM_TIMEOUT_DFE = 4'h7;
localparam SM_EXECUTE_DFE = 4'h8;
endpackage
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_det_phy/wr_arria10_e3p1_det_phy/synth/wr_arria10_e3p1_det_phy_cfg.v 0 → 100644
View file @ d4590b9d
config wr_arria10_e3p1_det_phy_cfg;
design wr_arria10_e3p1_det_phy;
instance wr_arria10_e3p1_det_phy.xcvr_native_a10_0 use wr_arria10_e3p1_det_phy_altera_xcvr_native_a10_181.wr_arria10_e3p1_det_phy_altera_xcvr_native_a10_181_b7porpa;
endconfig
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