platform/xilinx/wr_gtp_phy: fix for simulation

because of assigning clock signals, sometimes that simulator gets lost, in such case the input ch{0/1}_rx_data_o is faster than ch{0/1}_rx_rbclk_o. To make sure it works ok, artificial 1ns delay is introduced.

platform/xilinx/wr_gtp_phy: fix for simulation
because of assigning clock signals, sometimes that simulator gets lost, in such case the input ch{0/1}_rx_data_o is faster than ch{0/1}_rx_rbclk_o. To make sure it works ok, artificial 1ns delay is introduced.
c23ed1b5 · Maciej Lipinski · b8aee73b · c23ed1b5
Commit c23ed1b5 authored Mar 10, 2016 by Maciej Lipinski
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wr_gtp_phy_spartan6.vhd platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd +6 -6

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--- a/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
+++ b/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
@@ -519,9 +519,9 @@ begin  -- rtl
          ch0_rx_k_o       <= '1';
          ch0_rx_enc_err_o <= '1';
        else
-          ch0_rx_data_o    <= ch0_rx_data_int;
-          ch0_rx_k_o       <= ch0_rx_k_int;
-          ch0_rx_enc_err_o <= ch0_rx_disperr or ch0_rx_invcode;
+          ch0_rx_data_o    <= ch0_rx_data_int after 1ns;
+          ch0_rx_k_o       <= ch0_rx_k_int after 1ns;
+          ch0_rx_enc_err_o <= (ch0_rx_disperr or ch0_rx_invcode) after 1ns;
        end if;
      end if;
    end process;
@@ -674,9 +674,9 @@ begin  -- rtl
          ch1_rx_k_o       <= '1';
          ch1_rx_enc_err_o <= '1';
        else
-          ch1_rx_data_o    <= ch1_rx_data_int;
-          ch1_rx_k_o       <= ch1_rx_k_int;
-          ch1_rx_enc_err_o <= ch1_rx_disperr or ch1_rx_invcode;
+          ch1_rx_data_o    <= ch1_rx_data_int after 1ns;
+          ch1_rx_k_o       <= ch1_rx_k_int after 1ns;
+          ch1_rx_enc_err_o <= (ch1_rx_disperr or ch1_rx_invcode) after 1ns;
        end if;
      end if;
    end process;