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White Rabbit core collection
Commit bd157484 authored by Tristan Gingold's avatar Tristan Gingold
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cleanup: use direct instantiation, remove unused signals

parent 5c551ddc
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    modules/wr_endpoint/ep_timestamping_unit.vhd
    View file @ bd157484
    ......@@ -128,31 +128,11 @@ entity ep_timestamping_unit is
    regs_i : in t_ep_out_registers;
    regs_o : out t_ep_in_registers
    );
    end ep_timestamping_unit;
    architecture syn of ep_timestamping_unit is
    component ep_ts_counter
    generic (
    g_num_bits_r : natural;
    g_num_bits_f : natural;
    g_init_value : natural;
    g_max_value : natural);
    port (
    clk_i : in std_logic;
    rst_n_i : in std_logic;
    overflow_o : out std_logic := '0';
    value_r_o : out std_logic_vector(g_num_bits_r-1 downto 0);
    value_f_o : out std_logic_vector(g_num_bits_f-1 downto 0);
    pps_p_i : in std_logic;
    sync_start_p_i : in std_logic;
    sync_done_o : out std_logic);
    end component;
    signal cntr_rx_r : std_logic_vector(g_timestamp_bits_r-1 downto 0);
    signal cntr_rx_f : std_logic_vector(g_timestamp_bits_f-1 downto 0);
    signal cntr_tx_r : std_logic_vector(g_timestamp_bits_r-1 downto 0);
    ......@@ -170,19 +150,9 @@ architecture syn of ep_timestamping_unit is
    signal tx_ts_done : std_logic;
    signal txts : std_logic;
    signal got_tx_oob : std_logic;
    signal tx_oob_reg : std_logic_vector(15 downto 0);
    signal rx_oob_reg : std_logic_vector(47 downto 0);
    signal fid_valid : std_logic;
    signal txts_valid : std_logic;
    signal valid_rx, valid_tx : std_logic;
    signal cal_count : unsigned(5 downto 0);
    signal cal_count : unsigned(5 downto 0);
    signal rx_trigger_mask, rx_trigger_a, rx_cal_pulse_a : std_logic;
    signal regs_o_tscr_cs_done : std_logic;
    ......@@ -192,8 +162,8 @@ architecture syn of ep_timestamping_unit is
    begin -- syn
    -- Instatniation of the timestamping counter
    U_counter : ep_ts_counter
    -- Instantiation of the timestamping counter
    U_counter : entity work.ep_ts_counter
    generic map (
    g_num_bits_r => g_timestamp_bits_r,
    g_num_bits_f => g_timestamp_bits_f,
    ......@@ -250,7 +220,7 @@ begin -- syn
    rx_trigger_mask <= '1';
    end if;
    if(cal_count (5 downto 4) = x"01") then
    if(cal_count (5 downto 4) = b"01") then
    rx_cal_pulse_a <= '1';
    else
    rx_cal_pulse_a <= '0';
    ......
    modules/wr_pps_gen/wr_pps_gen.vhd
    View file @ bd157484
    ......@@ -100,47 +100,6 @@ architecture behavioral of wr_pps_gen is
    constant c_PERIOD : integer := g_ref_clock_rate;
    component pps_gen_wb is
    port (
    rst_n_i : in std_logic;
    clk_sys_i : in std_logic;
    wb_adr_i : in std_logic_vector(2 downto 0);
    wb_dat_i : in std_logic_vector(31 downto 0);
    wb_dat_o : out std_logic_vector(31 downto 0);
    wb_cyc_i : in std_logic;
    wb_sel_i : in std_logic_vector(3 downto 0);
    wb_stb_i : in std_logic;
    wb_we_i : in std_logic;
    wb_ack_o : out std_logic;
    wb_stall_o : out std_logic;
    refclk_i : in std_logic;
    ppsg_cr_cnt_rst_o : out std_logic;
    ppsg_cr_cnt_en_o : out std_logic;
    ppsg_cr_cnt_adj_o : out std_logic;
    ppsg_cr_cnt_adj_i : in std_logic;
    ppsg_cr_cnt_adj_load_o : out std_logic;
    ppsg_cr_cnt_set_o : out std_logic;
    ppsg_cr_pwidth_o : out std_logic_vector(27 downto 0);
    ppsg_cntr_nsec_i : in std_logic_vector(27 downto 0);
    ppsg_cntr_utclo_i : in std_logic_vector(31 downto 0);
    ppsg_cntr_utchi_i : in std_logic_vector(7 downto 0);
    ppsg_adj_nsec_o : out std_logic_vector(27 downto 0);
    ppsg_adj_nsec_wr_o : out std_logic;
    ppsg_adj_utclo_o : out std_logic_vector(31 downto 0);
    ppsg_adj_utclo_wr_o : out std_logic;
    ppsg_adj_utchi_o : out std_logic_vector(7 downto 0);
    ppsg_adj_utchi_wr_o : out std_logic;
    ppsg_escr_sync_o : out std_logic;
    ppsg_escr_sync_i : in std_logic;
    ppsg_escr_sync_load_o : out std_logic;
    ppsg_escr_pps_valid_o : out std_logic;
    ppsg_escr_tm_valid_o : out std_logic;
    ppsg_escr_sec_set_o : out std_logic;
    ppsg_escr_nsec_set_o : out std_logic;
    ppsg_escr_pps_unmask_o : out std_logic;
    ppsg_escr_pps_in_term_o: out std_logic);
    end component pps_gen_wb;
    -- Wisbone slave signals
    signal ppsg_cr_cnt_rst : std_logic;
    signal ppsg_cr_cnt_en : std_logic;
    ......@@ -174,7 +133,6 @@ architecture behavioral of wr_pps_gen is
    signal cntr_nsec : unsigned (27 downto 0);
    signal cntr_utc : unsigned (39 downto 0);
    signal cntr_pps_ext : unsigned (24 downto 0);
    signal ns_overflow : std_logic;
    signal ns_overflow_adv : std_logic;
    ......@@ -197,9 +155,7 @@ architecture behavioral of wr_pps_gen is
    signal wb_in : t_wishbone_slave_in;
    signal ns_overflow_2nd : std_logic;
    signal pps_in_d0, pps_ext_d0 : std_logic;
    signal retime_counter : unsigned(4 downto 0);
    signal pps_valid_int : std_logic;
    signal pps_out_int : std_logic;
    ......@@ -260,7 +216,7 @@ begin -- behavioral
    -- loads adjustment values into internal regsiters
    p_wishbone_loads : process(clk_sys_i, rst_n_i)
    p_wishbone_loads : process(clk_sys_i)
    begin
    if rising_edge(clk_sys_i) then
    if rst_n_i = '0' then
    ......@@ -467,7 +423,7 @@ begin -- behavioral
    end if;
    end process;
    Uwb_slave : pps_gen_wb
    Uwb_slave : entity work.pps_gen_wb
    port map (
    rst_n_i => rst_n_i,
    clk_sys_i => clk_sys_i,
    ......@@ -479,6 +435,7 @@ begin -- behavioral
    wb_stb_i => wb_in.stb,
    wb_we_i => wb_in.we,
    wb_ack_o => wb_out.ack,
    wb_stall_o => open,
    refclk_i => clk_ref_i,
    ppsg_cr_cnt_rst_o => ppsg_cr_cnt_rst,
    ppsg_cr_cnt_en_o => ppsg_cr_cnt_en,
    ......
    modules/wr_softpll_ng/wr_softpll_ng.vhd
    View file @ bd157484
    ......@@ -163,63 +163,14 @@ entity wr_softpll_ng is
    -- Debug FIFO readout interrupt
    dbg_fifo_irq_o : out std_logic
    );
    end wr_softpll_ng;
    architecture rtl of wr_softpll_ng is
    alias rst_n_i : std_logic is rst_sys_n_i;
    constant c_log2_replication : integer := 2;
    constant c_use_multi_dmtd : boolean := false;
    constant c_DBG_FIFO_THRESHOLD : integer := 8180;
    constant c_DBG_FIFO_COALESCE : integer := 100;
    constant c_BB_ERROR_BITS : integer := 16;
    component spll_wb_slave
    generic (
    g_with_debug_fifo : integer);
    port (
    rst_n_i : in std_logic;
    clk_sys_i : in std_logic;
    wb_adr_i : in std_logic_vector(5 downto 0);
    wb_dat_i : in std_logic_vector(31 downto 0);
    wb_dat_o : out std_logic_vector(31 downto 0);
    wb_cyc_i : in std_logic;
    wb_sel_i : in std_logic_vector(3 downto 0);
    wb_stb_i : in std_logic;
    wb_we_i : in std_logic;
    wb_ack_o : out std_logic;
    wb_stall_o : out std_logic;
    wb_int_o : out std_logic;
    irq_tag_i : in std_logic;
    regs_i : in t_spll_in_registers;
    regs_o : out t_spll_out_registers);
    end component;
    component spll_aligner
    generic (
    g_counter_width : integer;
    g_ref_clock_rate : integer;
    g_in_clock_rate : integer;
    g_sample_rate : integer);
    port (
    clk_sys_i : in std_logic;
    clk_in_i : in std_logic;
    clk_ref_i : in std_logic;
    rst_n_sys_i : in std_logic;
    rst_n_ref_i : in std_logic;
    rst_n_ext_i : in std_logic;
    pps_ext_a_i : in std_logic;
    pps_csync_p1_i : in std_logic;
    sample_cref_o : out std_logic_vector(g_counter_width-1 downto 0);
    sample_cin_o : out std_logic_vector(g_counter_width-1 downto 0);
    sample_valid_o : out std_logic;
    sample_ack_i : in std_logic);
    end component;
    function f_num_total_channels
    return integer is
    begin
    ......@@ -263,8 +214,6 @@ architecture rtl of wr_softpll_ng is
    type t_tag_array is array (0 to f_num_total_channels-1) of std_logic_vector(g_tag_bits-1 downto 0);
    type t_phase_error_array is array(0 to g_num_outputs-1) of std_logic_vector(c_BB_ERROR_BITS-1 downto 0);
    signal tags, tags_masked : t_tag_array;
    signal tags_grant_p, tags_p, tags_req, tags_grant : std_logic_vector(f_num_total_channels-1 downto 0);
    signal tag_muxed : std_logic_vector(g_tag_bits-1 downto 0);
    ......@@ -290,18 +239,8 @@ architecture rtl of wr_softpll_ng is
    signal dbg_fifo_irq : std_logic := '0';
    -- Temporary vectors for DDMTD clock selection (straight/reversed)
    signal dmtd_ref_clk_in, dmtd_ref_clk_dmtd : std_logic_vector(g_num_ref_inputs-1 downto 0);
    signal rst_n_dmtd_ref_clk : std_logic_vector(g_num_ref_inputs-1 downto 0);
    signal dmtd_fb_clk_in, dmtd_fb_clk_dmtd : std_logic_vector(g_num_outputs-1 downto 0);
    signal rst_n_dmtd_fb_clk : std_logic_vector(g_num_outputs-1 downto 0);
    signal ext_ref_present : std_logic;
    signal fb_resync_out : std_logic_vector(g_num_outputs-1 downto 0);
    signal ref_resync_start_p : std_logic_vector(31 downto 0);
    signal fb_resync_start_p : std_logic_vector(15 downto 0);
    type t_aligner_sample_array is array(0 to g_num_outputs) of std_logic_vector(27 downto 0);
    signal aligner_sample_valid, aligner_sample_ack : std_logic_vector(g_num_outputs downto 0);
    ......@@ -330,9 +269,6 @@ architecture rtl of wr_softpll_ng is
    attribute mark_debug of tag_muxed : signal is "true";
    attribute mark_debug of trr_wr_full : signal is "true";
    attribute mark_debug of tag_valid : signal is "true";
    begin -- rtl
    U_Adapter : wb_slave_adapter
    ......@@ -391,8 +327,6 @@ begin -- rtl
    r_stat_reset_i => regs_in.dmtd_stat_cr_rst_o,
    r_stat_ready_o => r_stat_valid_ref(i)
    );
    end generate gen_ref_dmtds;
    gen_feedback_dmtds : for i in 0 to g_num_outputs-1 generate
    ......@@ -433,11 +367,7 @@ begin -- rtl
    r_minmax_sel_i => regs_in.dmtd_stat_cr_minmax_sel_o,
    r_stat_reset_i => regs_in.dmtd_stat_cr_rst_o,
    r_stat_ready_o => r_stat_valid_fb(i)
    ); --debug_o(4));
    end generate gen_feedback_dmtds;
    -- drive unused debug output
    ......@@ -474,7 +404,7 @@ begin -- rtl
    -- debug_o(1) <= tags_p(g_num_ref_inputs + g_num_outputs);
    -- debug_o(2) <= tags_p(g_num_ref_inputs);
    U_Aligner_EXT : spll_aligner
    U_Aligner_EXT : entity work.spll_aligner
    generic map (
    g_counter_width => 28,
    g_ref_clock_rate => g_ref_clock_rate,
    ......@@ -577,7 +507,7 @@ begin -- rtl
    end process;
    U_WB_SLAVE : spll_wb_slave
    U_WB_SLAVE : entity work.spll_wb_slave
    generic map (
    g_with_debug_fifo => f_pick(g_with_debug_fifo, 1, 0))
    port map (
    ......@@ -672,7 +602,6 @@ begin -- rtl
    p_mux_tags : process(clk_sys_i)
    variable muxed : std_logic_vector(g_tag_bits-1 downto 0);
    variable src_id : std_logic_vector(5 downto 0);
    begin
    if rising_edge(clk_sys_i) then
    if rst_n_i = '0' then
    ......
    modules/wrc_core/wr_core.vhd
    View file @ bd157484
    ......@@ -698,6 +698,7 @@ begin
    int_o => softpll_irq,
    dbg_fifo_irq_o => open,
    debug_o => open);
    clk_fb(0) <= clk_ref_i;
    ......
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