riscv port: fix SPEC build errors

bbaae460 · Tomasz Wlostowski · 830b43a7 · bbaae460 · bbaae460 · bbaae460
Commit bbaae460 authored Apr 14, 2021 by Tomasz Wlostowski
4 changed files
--- a/modules/wrc_core/wr_core.vhd
+++ b/modules/wrc_core/wr_core.vhd
@@ -6,7 +6,7 @@
 -- Author     : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2011-02-02
-- Last update: 2021-02-19
+-- Last update: 2021-02-25
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -1005,6 +1005,10 @@ begin
  secbar_master_i(8).rty   <= '0';


+  cpu_csr_wb_in <= secbar_master_o(9);
+  secbar_master_i(9) <= cpu_csr_wb_out;
+  
+
  -----------------------------------------------------------------------------
  -- WBP MUX
  -----------------------------------------------------------------------------

--- a/sim/endpoint_mdio.v
+++ b/sim/endpoint_mdio.v
@@ -142,3 +142,5 @@
 `define MDIO_ECTRL_TX_PRBS_SEL 32'h00000700
 `define ADDR_MDIO_LPC_PHY_STAT         7'h48
 `define ADDR_MDIO_LPC_PHY_CTRL         7'h4c
+`define ADDR_MDIO_DBG_PRBS_CONTROL     7'h50
+`define ADDR_MDIO_DBG_PRBS_STATUS      7'h54
--- a/syn/spec_ref_design/spec_wr_ref.xise
+++ b/syn/spec_ref_design/spec_wr_ref.xise
--- a/top/spec_ref_design/spec_wr_ref_top.vhd
+++ b/top/spec_ref_design/spec_wr_ref_top.vhd
@@ -7,7 +7,7 @@
 -- Author(s)  : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2017-02-20
-- Last update: 2019-04-26
+-- Last update: 2021-02-25
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
 -- Description: Top-level file for the WRPC reference design on the SPEC.
@@ -356,7 +356,7 @@ begin  -- architecture top

      ---------------------------------------------------------
      -- Interrupt interface
-      dma_irq_o => open,
+    --  dma_irq_o => open,
      irq_p_i   => '0',
      irq_p_o   => gn_gpio(0),