Skip to content

W
White Rabbit core collection
Commit b5cb1c8c authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
Browse files
Options

modules/wr_endpoint: add input to stop RX traffic (for WRS watchdog)

parent 37cfba4e
Hide whitespace changes
Inline Side-by-side
Showing with 34 additions and 7 deletions
modules/wr_endpoint/endpoint_pkg.vhd
View file @ b5cb1c8c
...@@ -113,7 +113,8 @@ package endpoint_pkg is ...@@ -113,7 +113,8 @@ package endpoint_pkg is
g_with_dmtd : boolean := false; g_with_dmtd : boolean := false;
g_with_packet_injection : boolean := false; g_with_packet_injection : boolean := false;
g_use_new_rxcrc : boolean := false; g_use_new_rxcrc : boolean := false;
g_use_new_txcrc : boolean := false); g_use_new_txcrc : boolean := false;
g_with_stop_traffic : boolean := false);
port ( port (
clk_ref_i : in std_logic; clk_ref_i : in std_logic;
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
...@@ -185,6 +186,7 @@ package endpoint_pkg is ...@@ -185,6 +186,7 @@ package endpoint_pkg is
led_act_o : out std_logic; led_act_o : out std_logic;
link_kill_i : in std_logic := '0'; link_kill_i : in std_logic := '0';
link_up_o : out std_logic; link_up_o : out std_logic;
stop_traffic_i : in std_logic := '0';
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0); dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0); dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
nice_dbg_o : out t_dbg_ep); nice_dbg_o : out t_dbg_ep);
...@@ -209,7 +211,8 @@ package endpoint_pkg is ...@@ -209,7 +211,8 @@ package endpoint_pkg is
g_with_dmtd : boolean := false; g_with_dmtd : boolean := false;
g_with_packet_injection : boolean := false; g_with_packet_injection : boolean := false;
g_use_new_rxcrc : boolean := false; g_use_new_rxcrc : boolean := false;
g_use_new_txcrc : boolean := false); g_use_new_txcrc : boolean := false;
g_with_stop_traffic : boolean := false);
port ( port (
clk_ref_i : in std_logic; clk_ref_i : in std_logic;
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
...@@ -303,6 +306,7 @@ package endpoint_pkg is ...@@ -303,6 +306,7 @@ package endpoint_pkg is
led_act_o : out std_logic; led_act_o : out std_logic;
link_kill_i : in std_logic := '0'; link_kill_i : in std_logic := '0';
link_up_o : out std_logic; link_up_o : out std_logic;
stop_traffic_i : in std_logic := '0';
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0); dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0); dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
nice_dbg_o : out t_dbg_ep); nice_dbg_o : out t_dbg_ep);
......
modules/wr_endpoint/wr_endpoint.vhd
View file @ b5cb1c8c
...@@ -73,7 +73,8 @@ entity wr_endpoint is ...@@ -73,7 +73,8 @@ entity wr_endpoint is
g_with_dmtd : boolean := false; g_with_dmtd : boolean := false;
g_with_packet_injection : boolean := false; g_with_packet_injection : boolean := false;
g_use_new_rxcrc : boolean := false; g_use_new_rxcrc : boolean := false;
g_use_new_txcrc : boolean := false g_use_new_txcrc : boolean := false;
g_with_stop_traffic : boolean := false
); );
port ( port (
...@@ -288,6 +289,8 @@ entity wr_endpoint is ...@@ -288,6 +289,8 @@ entity wr_endpoint is
-- (e.g.: cable disconnected) -- (e.g.: cable disconnected)
link_up_o : out std_logic; link_up_o : out std_logic;
stop_traffic_i : in std_logic := '0';
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0); dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0); dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
nice_dbg_o : out t_dbg_ep nice_dbg_o : out t_dbg_ep
...@@ -360,6 +363,7 @@ architecture syn of wr_endpoint is ...@@ -360,6 +363,7 @@ architecture syn of wr_endpoint is
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
signal rxpcs_fab : t_ep_internal_fabric; signal rxpcs_fab : t_ep_internal_fabric;
signal rxpath_fab : t_ep_internal_fabric;
signal rxpcs_busy : std_logic; signal rxpcs_busy : std_logic;
signal rxpcs_fifo_almostfull : std_logic; signal rxpcs_fifo_almostfull : std_logic;
...@@ -622,7 +626,7 @@ begin ...@@ -622,7 +626,7 @@ begin
rst_n_sys_i => rst_n_sys, rst_n_sys_i => rst_n_sys,
rst_n_rx_i => rst_n_rx, rst_n_rx_i => rst_n_rx,
pcs_fab_i => rxpcs_fab, pcs_fab_i => rxpath_fab,
pcs_fifo_almostfull_o => rxpcs_fifo_almostfull, pcs_fifo_almostfull_o => rxpcs_fifo_almostfull,
pcs_busy_i => rxpcs_busy, pcs_busy_i => rxpcs_busy,
...@@ -793,7 +797,7 @@ begin ...@@ -793,7 +797,7 @@ begin
else else
if(regs_fromwb.dsr_lact_o = '1' and regs_fromwb.dsr_lact_load_o = '1') then if(regs_fromwb.dsr_lact_o = '1' and regs_fromwb.dsr_lact_load_o = '1') then
regs_towb_ep.dsr_lact_i <= '0'; -- clear-on-write regs_towb_ep.dsr_lact_i <= '0'; -- clear-on-write
elsif(txpcs_fab.dvalid = '1' or rxpcs_fab.dvalid = '1') then elsif(txpcs_fab.dvalid = '1' or rxpath_fab.dvalid = '1') then
regs_towb_ep.dsr_lact_i <= '1'; regs_towb_ep.dsr_lact_i <= '1';
end if; end if;
end if; end if;
...@@ -907,6 +911,21 @@ begin ...@@ -907,6 +911,21 @@ begin
end if; end if;
end process; end process;
GEN_STOP: if(g_with_stop_traffic) generate
rxpath_fab.sof <= rxpcs_fab.sof when(stop_traffic_i='0') else '0';
rxpath_fab.dvalid <= rxpcs_fab.dvalid when(stop_traffic_i='0') else '0';
rxpath_fab.eof <= rxpcs_fab.eof;
rxpath_fab.error <= rxpcs_fab.error;
rxpath_fab.bytesel <= rxpcs_fab.bytesel;
rxpath_fab.has_rx_timestamp <= rxpcs_fab.has_rx_timestamp;
rxpath_fab.rx_timestamp_valid <= rxpcs_fab.rx_timestamp_valid;
rxpath_fab.data <= rxpcs_fab.data;
rxpath_fab.addr <= rxpcs_fab.addr;
end generate;
GEN_NO_STOP: if(not g_with_stop_traffic) generate
rxpath_fab <= rxpcs_fab;
end generate;
-------------------------- RMON events ----------------------------------- -------------------------- RMON events -----------------------------------
rmon.rx_pcs_err <= rx_path_rmon.rx_pcs_err; --from ep_rx_path rmon.rx_pcs_err <= rx_path_rmon.rx_pcs_err; --from ep_rx_path
......
modules/wr_endpoint/xwr_endpoint.vhd
View file @ b5cb1c8c
...@@ -63,7 +63,8 @@ entity xwr_endpoint is ...@@ -63,7 +63,8 @@ entity xwr_endpoint is
g_with_dmtd : boolean := true; g_with_dmtd : boolean := true;
g_with_packet_injection : boolean := false; g_with_packet_injection : boolean := false;
g_use_new_rxcrc : boolean := false; g_use_new_rxcrc : boolean := false;
g_use_new_txcrc : boolean := false g_use_new_txcrc : boolean := false;
g_with_stop_traffic : boolean := false
); );
port ( port (
...@@ -249,6 +250,7 @@ entity xwr_endpoint is ...@@ -249,6 +250,7 @@ entity xwr_endpoint is
link_kill_i : in std_logic := '0'; link_kill_i : in std_logic := '0';
link_up_o : out std_logic; link_up_o : out std_logic;
stop_traffic_i : in std_logic := '0';
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0); dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0); dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
nice_dbg_o : out t_dbg_ep); nice_dbg_o : out t_dbg_ep);
...@@ -278,7 +280,8 @@ begin ...@@ -278,7 +280,8 @@ begin
g_with_dmtd => g_with_dmtd, g_with_dmtd => g_with_dmtd,
g_with_packet_injection => g_with_packet_injection, g_with_packet_injection => g_with_packet_injection,
g_use_new_rxcrc => g_use_new_rxcrc, g_use_new_rxcrc => g_use_new_rxcrc,
g_use_new_txcrc => g_use_new_txcrc) g_use_new_txcrc => g_use_new_txcrc,
g_with_stop_traffic => g_with_stop_traffic)
port map ( port map (
clk_ref_i => clk_ref_i, clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
...@@ -372,6 +375,7 @@ begin ...@@ -372,6 +375,7 @@ begin
inject_user_value_i => inject_user_value_i, inject_user_value_i => inject_user_value_i,
inject_packet_sel_i => inject_packet_sel_i, inject_packet_sel_i => inject_packet_sel_i,
inject_ready_o => inject_ready_o, inject_ready_o => inject_ready_o,
stop_traffic_i => stop_traffic_i,
dbg_tx_pcs_wr_count_o=>dbg_tx_pcs_wr_count_o, dbg_tx_pcs_wr_count_o=>dbg_tx_pcs_wr_count_o,
dbg_tx_pcs_rd_count_o=>dbg_tx_pcs_rd_count_o, dbg_tx_pcs_rd_count_o=>dbg_tx_pcs_rd_count_o,
nice_dbg_o => nice_dbg_o); nice_dbg_o => nice_dbg_o);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment