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Commit b48f0951 authored by Maciej Lipinski's avatar Maciej Lipinski
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[VXS support] added support for two multiplexed GPT/SFP to VXS to ref

parent a842c4b2
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syn/vxs_ref_design/vxs_wr_ref.xise
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top/vxs_ref_design/vxs_wr_ref_top.ucf
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...@@ -57,18 +57,18 @@ NET "VCXO_MHZ20" CLOCK_DEDICATED_ROUTE = FALSE; ...@@ -57,18 +57,18 @@ NET "VCXO_MHZ20" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "VXS2FPGA1_P" LOC = AP3; # NET "VXS2FPGA1_P" LOC = AP3;
# Pinning for GTP118 tile (Added for V2) # Pinning for GTP118 tile (Added for V2)
#INST "C227/U_GTP_TILE_INST/gtp_dual_i" LOC = GTP_DUAL_X0Y1; INST "cmp_xwrc_board_vxs/cmp_xwrc_platform/gen_phy_virtex5.cmp_gtp/U_GTP_TILE_INST/gtp_dual_i" LOC = GTP_DUAL_X0Y1;
#INST "GTP118_CLK_IBUFGDS/IBUFGDS_inst" LOC = BUFDS_X0Y1; INST "cmp_xwrc_board_vxs/cmp_xwrc_platform/gen_phy_virtex5.cmp_ibufgds_gtp" LOC = BUFDS_X0Y1;
NET "FPGA2SFP_N" IOSTANDARD = LVPECL_25; NET "FPGA2SFP_N" IOSTANDARD = LVPECL_25;
NET "FPGA2SFP_N" LOC = AH2; NET "FPGA2SFP_N" LOC = AH2;
NET "FPGA2SFP_P" IOSTANDARD = LVPECL_25; NET "FPGA2SFP_P" IOSTANDARD = LVPECL_25;
NET "FPGA2SFP_P" LOC = AJ2; NET "FPGA2SFP_P" LOC = AJ2;
# NET "FPGA2VXS2_N" IOSTANDARD = LVPECL_25; NET "FPGA2VXS2_N" IOSTANDARD = LVPECL_25;
# NET "FPGA2VXS2_N" LOC = AE2; NET "FPGA2VXS2_N" LOC = AE2;
# NET "FPGA2VXS2_P" IOSTANDARD = LVPECL_25; NET "FPGA2VXS2_P" IOSTANDARD = LVPECL_25;
# NET "FPGA2VXS2_P" LOC = AD2; NET "FPGA2VXS2_P" LOC = AD2;
NET "GTP118_CLK_N" LOC = AF3; NET "GTP118_CLK_N" LOC = AF3;
NET "GTP118_CLK_P" LOC = AF4; NET "GTP118_CLK_P" LOC = AF4;
...@@ -79,10 +79,10 @@ NET "SFP2FPGA_N" LOC = AG1; ...@@ -79,10 +79,10 @@ NET "SFP2FPGA_N" LOC = AG1;
NET "SFP2FPGA_P" IOSTANDARD = LVPECL_25; NET "SFP2FPGA_P" IOSTANDARD = LVPECL_25;
NET "SFP2FPGA_P" LOC = AH1; NET "SFP2FPGA_P" LOC = AH1;
# NET "VXS2FPGA2_N" IOSTANDARD = LVPECL_25; NET "VXS2FPGA2_N" IOSTANDARD = LVPECL_25;
# NET "VXS2FPGA2_N" LOC = AF1; NET "VXS2FPGA2_N" LOC = AF1;
# NET "VXS2FPGA2_P" IOSTANDARD = LVPECL_25; NET "VXS2FPGA2_P" IOSTANDARD = LVPECL_25;
# NET "VXS2FPGA2_P" LOC = AE1; NET "VXS2FPGA2_P" LOC = AE1;
# Clocking # Clocking
...@@ -279,8 +279,8 @@ NET "SFP2_SCL" IOSTANDARD = LVCMOS33; ...@@ -279,8 +279,8 @@ NET "SFP2_SCL" IOSTANDARD = LVCMOS33;
NET "SFP2_SCL" LOC = AE34; NET "SFP2_SCL" LOC = AE34;
NET "SFP2_SDA" IOSTANDARD = LVCMOS33; NET "SFP2_SDA" IOSTANDARD = LVCMOS33;
NET "SFP2_SDA" LOC = AF34; NET "SFP2_SDA" LOC = AF34;
# NET "SFP2_TX_DIS" IOSTANDARD = LVCMOS33; NET "SFP2_TX_DIS" IOSTANDARD = LVCMOS33;
# NET "SFP2_TX_DIS" LOC = AE33; NET "SFP2_TX_DIS" LOC = AE33;
NET "SFP3_LOS" IOSTANDARD = LVCMOS33; NET "SFP3_LOS" IOSTANDARD = LVCMOS33;
NET "SFP3_LOS" LOC = AD34; NET "SFP3_LOS" LOC = AD34;
NET "SFP3_PRSNT_N" IOSTANDARD = LVCMOS33; NET "SFP3_PRSNT_N" IOSTANDARD = LVCMOS33;
...@@ -525,9 +525,13 @@ NET "GTP118_CLK_P" TNM_NET = GTP118_CLK_P; ...@@ -525,9 +525,13 @@ NET "GTP118_CLK_P" TNM_NET = GTP118_CLK_P;
#TIMESPEC TS_GTP118_CLK_P = PERIOD "GTP118_CLK_P" 132 MHz HIGH 50%; #TIMESPEC TS_GTP118_CLK_P = PERIOD "GTP118_CLK_P" 132 MHz HIGH 50%;
TIMESPEC TS_GTP118_CLK_P = PERIOD "GTP118_CLK_P" 8 ns HIGH 50%; TIMESPEC TS_GTP118_CLK_P = PERIOD "GTP118_CLK_P" 8 ns HIGH 50%;
NET "cmp_xwrc_board_vxs/cmp_xwrc_platform/gen_phy_virtex5.cmp_gtp/ch0_rx_rec_clk_pad" TNM_NET = cmp_xwrc_board_vxs/cmp_xwrc_platform/gen_phy_virtex5.cmp_gtp/ch0_rx_rec_clk_pad;
TIMESPEC TS_cmp_xwrc_board_vxs_cmp_xwrc_platform_gen_phy_virtex5_cmp_gtp_ch0_rx_rec_clk_pad = PERIOD "cmp_xwrc_board_vxs/cmp_xwrc_platform/gen_phy_virtex5.cmp_gtp/ch0_rx_rec_clk_pad" 8 ns HIGH 50%;
NET "cmp_xwrc_board_vxs/cmp_xwrc_platform/gen_phy_virtex5.cmp_gtp/ch1_rx_rec_clk_pad" TNM_NET = cmp_xwrc_board_vxs/cmp_xwrc_platform/gen_phy_virtex5.cmp_gtp/ch1_rx_rec_clk_pad; NET "cmp_xwrc_board_vxs/cmp_xwrc_platform/gen_phy_virtex5.cmp_gtp/ch1_rx_rec_clk_pad" TNM_NET = cmp_xwrc_board_vxs/cmp_xwrc_platform/gen_phy_virtex5.cmp_gtp/ch1_rx_rec_clk_pad;
TIMESPEC TS_cmp_xwrc_board_vxs_cmp_xwrc_platform_gen_phy_virtex5_cmp_gtp_ch1_rx_rec_clk_pad = PERIOD "cmp_xwrc_board_vxs/cmp_xwrc_platform/gen_phy_virtex5.cmp_gtp/ch1_rx_rec_clk_pad" 8 ns HIGH 50%; TIMESPEC TS_cmp_xwrc_board_vxs_cmp_xwrc_platform_gen_phy_virtex5_cmp_gtp_ch1_rx_rec_clk_pad = PERIOD "cmp_xwrc_board_vxs/cmp_xwrc_platform/gen_phy_virtex5.cmp_gtp/ch1_rx_rec_clk_pad" 8 ns HIGH 50%;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit; INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit; INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
......
top/vxs_ref_design/vxs_wr_ref_top.vhd
View file @ b48f0951
...@@ -47,7 +47,8 @@ use unisim.vcomponents.all; ...@@ -47,7 +47,8 @@ use unisim.vcomponents.all;
entity vxs_wr_ref_top is entity vxs_wr_ref_top is
generic ( generic (
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram"; -- g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
g_dpram_initf : string := "../../../binaries/wrc-VXS-support-v8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and -- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench. -- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations. -- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
...@@ -88,7 +89,7 @@ entity vxs_wr_ref_top is ...@@ -88,7 +89,7 @@ entity vxs_wr_ref_top is
VXS2FPGA2_N : in std_logic; VXS2FPGA2_N : in std_logic;
VXS2FPGA2_P : in std_logic; VXS2FPGA2_P : in std_logic;
SFP2_LOS : in std_logic; SFP2_LOS : in std_logic;
--unused SFP2_TX_DIS : out std_logic; SFP2_TX_DIS : out std_logic;
SFP2_SCL : inout std_logic; SFP2_SCL : inout std_logic;
SFP2_SDA : inout std_logic; SFP2_SDA : inout std_logic;
SFP2_PRSNT_N : in std_logic; SFP2_PRSNT_N : in std_logic;
...@@ -115,7 +116,7 @@ entity vxs_wr_ref_top is ...@@ -115,7 +116,7 @@ entity vxs_wr_ref_top is
-- flash -- flash
FRAMMOSI : out std_logic; FRAMMOSI : out std_logic;
FRAMSCLK : out std_logic; FRAMSCLK : out std_logic;
FRAMWPDIS : in std_logic; FRAMWPDIS : in std_logic; -- write protect input, use for sfp MUX
FRAMWP_N : out std_logic; FRAMWP_N : out std_logic;
FRAMMISO : in std_logic; FRAMMISO : in std_logic;
FRAMCS_N : out std_logic; FRAMCS_N : out std_logic;
...@@ -250,11 +251,11 @@ architecture top of vxs_wr_ref_top is ...@@ -250,11 +251,11 @@ architecture top of vxs_wr_ref_top is
signal eeprom_scl_in : std_logic; signal eeprom_scl_in : std_logic;
signal eeprom_scl_out : std_logic; signal eeprom_scl_out : std_logic;
-- SFP -- SFP I2C -> ch0 & ch1
signal sfp_sda_in : std_logic; signal sfp_sda_in, sfp1_sda_in : std_logic;
signal sfp_sda_out : std_logic; signal sfp_sda_out, sfp1_sda_out : std_logic;
signal sfp_scl_in : std_logic; signal sfp_scl_in, sfp1_scl_in : std_logic;
signal sfp_scl_out : std_logic; signal sfp_scl_out, sfp1_scl_out : std_logic;
-- OneWire -- OneWire
signal onewire_data : std_logic; signal onewire_data : std_logic;
...@@ -274,28 +275,29 @@ architecture top of vxs_wr_ref_top is ...@@ -274,28 +275,29 @@ architecture top of vxs_wr_ref_top is
-- ChipScope for histogram readout/debugging -- ChipScope for histogram readout/debugging
-- component chipscope_virtex5_icon component chipscope_virtex5_icon
-- port ( port (
-- CONTROL0: inout std_logic_vector(35 downto 0)); CONTROL0: inout std_logic_vector(35 downto 0));
-- end component; end component;
--
-- component chipscope_virtex5_ila component chipscope_virtex5_ila
-- port ( port (
-- CONTROL: inout std_logic_vector(35 downto 0); CONTROL: inout std_logic_vector(35 downto 0);
-- CLK: in std_logic; CLK: in std_logic;
-- TRIG0: in std_logic_vector(31 downto 0); TRIG0: in std_logic_vector(31 downto 0);
-- TRIG1: in std_logic_vector(31 downto 0); TRIG1: in std_logic_vector(31 downto 0);
-- TRIG2: in std_logic_vector(31 downto 0); TRIG2: in std_logic_vector(31 downto 0);
-- TRIG3: in std_logic_vector(31 downto 0)); TRIG3: in std_logic_vector(31 downto 0));
-- end component; end component;
--
-- signal CONTROL0, CONTROL1, CONTROL2, CONTROL3 : std_logic_vector(35 downto 0); signal CONTROL0, CONTROL1, CONTROL2, CONTROL3 : std_logic_vector(35 downto 0);
-- signal TRIG0, TRIG1, TRIG2, TRIG3 : std_logic_vector(31 downto 0); signal TRIG0, TRIG1, TRIG2, TRIG3 : std_logic_vector(31 downto 0);
signal led_link : std_logic; signal led_link : std_logic;
signal led_ack : std_logic; signal led_ack : std_logic;
signal SFP3_TX_DIS_out, SFP3_LOS_in : std_logic; signal SFP3_TX_DIS_out, SFP3_LOS_in : std_logic;
signal sfp_mux_sel: std_logic;
begin -- architecture top begin -- architecture top
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
...@@ -306,6 +308,9 @@ begin -- architecture top ...@@ -306,6 +308,9 @@ begin -- architecture top
generic map ( generic map (
g_simulation => g_simulation, g_simulation => g_simulation,
g_with_external_clock_input => FALSE, g_with_external_clock_input => FALSE,
g_gtp_enable_ch0 => 1,
g_gtp_enable_ch1 => 1,
g_gtp_mux_enable => TRUE,
g_dpram_initf => g_dpram_initf) g_dpram_initf => g_dpram_initf)
port map ( port map (
areset_n_i => std_logic(not POR), -- Power areset_n_i => std_logic(not POR), -- Power
...@@ -326,19 +331,37 @@ begin -- architecture top ...@@ -326,19 +331,37 @@ begin -- architecture top
pll25dac_cs_n_o => DAC_PLL125_SYNC_N, pll25dac_cs_n_o => DAC_PLL125_SYNC_N,
pll20dac_cs_n_o => DAC_PLL20_SYNC_N, pll20dac_cs_n_o => DAC_PLL20_SYNC_N,
sfp_txp_o => FPGA2SFP_P, -- ch0 : backup
sfp_txn_o => FPGA2SFP_N, sfp_txp_o => FPGA2VXS2_P,
sfp_rxp_i => SFP2FPGA_P, sfp_txn_o => FPGA2VXS2_N,
sfp_rxn_i => SFP2FPGA_N, sfp_rxp_i => VXS2FPGA2_P,
sfp_det_i => SFP3_PRSNT_N, sfp_rxn_i => VXS2FPGA2_N,
sfp_det_i => SFP2_PRSNT_N,
sfp_sda_i => sfp_sda_in, sfp_sda_i => sfp_sda_in,
sfp_sda_o => sfp_sda_out, sfp_sda_o => sfp_sda_out,
sfp_scl_i => sfp_scl_in, sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out, sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => open, -- connect later sfp_rate_select_o => open, -- connect later
sfp_tx_fault_i => open, sfp_tx_fault_i => open,
sfp_tx_disable_o => SFP3_TX_DIS_out, sfp_tx_disable_o => SFP2_TX_DIS,
sfp_los_i => SFP3_LOS_in, sfp_los_i => SFP2_LOS,
sfp_mux_sel_i => sfp_mux_sel,
-- ch1 : dedicated to WR
sfp1_txp_o => FPGA2SFP_P,
sfp1_txn_o => FPGA2SFP_N,
sfp1_rxp_i => SFP2FPGA_P,
sfp1_rxn_i => SFP2FPGA_N,
sfp1_det_i => SFP3_PRSNT_N,
sfp1_sda_i => sfp1_sda_in,
sfp1_sda_o => sfp1_sda_out,
sfp1_scl_i => sfp1_scl_in,
sfp1_scl_o => sfp1_scl_out,
sfp1_rate_select_o => open, -- connect later
sfp1_tx_fault_i => open,
sfp1_tx_disable_o => SFP3_TX_DIS_out,
sfp1_los_i => SFP3_LOS_in,
eeprom_sda_i => '1', eeprom_sda_i => '1',
eeprom_sda_o => open, eeprom_sda_o => open,
...@@ -367,10 +390,16 @@ begin -- architecture top ...@@ -367,10 +390,16 @@ begin -- architecture top
LED_CLK_R <= led_ack; LED_CLK_R <= led_ack;
-- Tristates for SFP EEPROM -- Tristates for SFP EEPROM
SFP3_SCL <= '0' when sfp_scl_out = '0' else 'Z'; -- ch0 - backup
SFP3_SDA <= '0' when sfp_sda_out = '0' else 'Z'; SFP2_SCL <= '0' when sfp_scl_out = '0' else 'Z';
sfp_scl_in <= SFP3_SCL; SFP2_SDA <= '0' when sfp_sda_out = '0' else 'Z';
sfp_sda_in <= SFP3_SDA; sfp_scl_in <= SFP2_SCL;
sfp_sda_in <= SFP2_SDA;
-- ch1 - dedicated to wr:
SFP3_SCL <= '0' when sfp1_scl_out = '0' else 'Z';
SFP3_SDA <= '0' when sfp1_sda_out = '0' else 'Z';
sfp1_scl_in <= SFP3_SCL;
sfp1_sda_in <= SFP3_SDA;
SFP3_LOS_in <= SFP3_LOS; SFP3_LOS_in <= SFP3_LOS;
SFP3_TX_DIS <= SFP3_TX_DIS_out; SFP3_TX_DIS <= SFP3_TX_DIS_out;
...@@ -403,26 +432,38 @@ begin -- architecture top ...@@ -403,26 +432,38 @@ begin -- architecture top
-- FLASH -- FLASH
FRAMWP_N <= '1'; -- not write protected FRAMWP_N <= '1'; -- not write protected
-- U_sync_with_clk : gc_sync_ffs
-- CS_ICON : chipscope_virtex5_icon port map (
-- port map ( clk_i => clk_sys_62m5,
-- CONTROL0 => CONTROL0); rst_n_i => rst_sys_62m5_n,
-- CS_ILA : chipscope_virtex5_ila data_i => FRAMWPDIS,
-- port map ( synced_o => sfp_mux_sel);
-- CONTROL => CONTROL0,
-- CLK => clk_sys_62m5, --------------------------------------------------------------------------------
-- TRIG0 => TRIG0, --------------------------------------------------------------------------------
-- TRIG1 => TRIG1, CS_ICON : chipscope_virtex5_icon
-- TRIG2 => TRIG2, port map (
-- TRIG3 => TRIG3); CONTROL0 => CONTROL0);
-- CS_ILA : chipscope_virtex5_ila
-- trig0(2) <= onewire_data; port map (
-- trig0(3) <= led_link; CONTROL => CONTROL0,
-- trig0(4) <= led_ack; CLK => clk_sys_62m5,
-- trig0(5) <= SFP3_PRSNT_N; TRIG0 => TRIG0,
-- trig0(6) <= SFP3_LOS; TRIG1 => TRIG1,
-- trig0(7) <= SFP3_TX_DIS_out; TRIG2 => TRIG2,
-- trig0(8) <= wrc_pps_out; TRIG3 => TRIG3);
-- trig0(9) <= wrc_pps_led;
trig0(0) <= SFP2_PRSNT_N;
trig0(1) <= SFP2_LOS;
trig0(2) <= onewire_data;
trig0(3) <= led_link;
trig0(4) <= led_ack;
trig0(5) <= SFP3_PRSNT_N;
trig0(6) <= SFP3_LOS;
trig0(7) <= SFP3_TX_DIS_out;
trig0(8) <= wrc_pps_out;
trig0(9) <= wrc_pps_led;
trig0(10) <= sfp_mux_sel;
trig0(11) <= FRAMWPDIS;
end architecture top; end architecture top;
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