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White Rabbit core collection
Commit b3ad9a9c authored by Dimitris Lampridis's avatar Dimitris Lampridis
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board: bring up more wrpc signals (includign aux_clks)

parent a9ef1b0c
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board/common/wr_board_pkg.vhd
View file @ b3ad9a9c
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board/common/xwrc_board_common.vhd
View file @ b3ad9a9c
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-22
-- Last update: 2017-03-07
-- Last update: 2017-03-08
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Wrapper for WR PTP core with common features shared between
......@@ -120,21 +120,25 @@ entity xwrc_board_common is
phy16_i : in t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
---------------------------------------------------------------------------
--GPIO
-- I2C EEPROM
---------------------------------------------------------------------------
led_act_o : out std_logic;
led_link_o : out std_logic;
scl_o : out std_logic;
scl_i : in std_logic := '1';
sda_o : out std_logic;
sda_i : in std_logic := '1';
---------------------------------------------------------------------------
-- SFP management info
---------------------------------------------------------------------------
sfp_scl_o : out std_logic;
sfp_scl_i : in std_logic := '1';
sfp_sda_o : out std_logic;
sfp_sda_i : in std_logic := '1';
sfp_det_i : in std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
......@@ -190,6 +194,20 @@ entity xwrc_board_common is
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
---------------------------------------------------------------------------
-- Generic diagnostics interface (access from WRPC via SNMP or uart console
---------------------------------------------------------------------------
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
---------------------------------------------------------------------------
-- Aux clocks control
---------------------------------------------------------------------------
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
---------------------------------------------------------------------------
-- External Tx Timestamping I/F
---------------------------------------------------------------------------
......@@ -204,28 +222,24 @@ entity xwrc_board_common is
fc_tx_pause_ready_o : out std_logic;
---------------------------------------------------------------------------
-- Timecode/Servo Control
-- Timecode I/F
---------------------------------------------------------------------------
tm_link_up_o : out std_logic;
-- DAC Control
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
-- Aux clock lock enable
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
-- Aux clock locked flag
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
-- Timecode output
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
---------------------------------------------------------------------------
-- Buttons, LEDs and PPS output
---------------------------------------------------------------------------
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
-- 1PPS output
pps_p_o : out std_logic;
pps_led_o : out std_logic;
-- access from WRPC (via SNMP or uart console) to applications for diagnostics (generic)
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others =>(others=>'0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
-- Link ok indication
link_ok_o : out std_logic
);
......@@ -267,8 +281,8 @@ architecture struct of xwrc_board_common is
-- when more diagnostics is added to streamers
-- final values that go to WRPC generics (depend on configuration)
constant c_diag_id : integer := f_pick_diag_val(g_fabric_iface,c_streamers_diag_id, g_diag_id);
constant c_diag_ver : integer := f_pick_diag_val(g_fabric_iface,c_streamers_diag_id, g_diag_id);
constant c_diag_id : integer := f_pick_diag_val(g_fabric_iface, c_streamers_diag_id, g_diag_id);
constant c_diag_ver : integer := f_pick_diag_val(g_fabric_iface, c_streamers_diag_id, g_diag_id);
constant c_diag_ro_size : integer := f_pick_diag_size(g_fabric_iface, c_WR_TRANS_ARR_SIZE_OUT, g_diag_ro_size);
constant c_diag_rw_size : integer := f_pick_diag_size(g_fabric_iface, c_WR_TRANS_ARR_SIZE_IN, g_diag_rw_size);
......@@ -285,7 +299,7 @@ begin -- architecture struct
-- check whether diag id and version are correct, i.e.:
-- * diag_id =1 is reserved for wr_streamers and cannot be used
-- * diag_ver values should start with 1
f_check_diag_id(g_diag_id,g_diag_ver);
f_check_diag_id(g_diag_id, g_diag_ver);
-----------------------------------------------------------------------------
-- The WR PTP core itself
......@@ -300,7 +314,7 @@ begin -- architecture struct
g_aux_clks => g_aux_clks,
g_ep_rxbuf_size => g_ep_rxbuf_size,
g_tx_runt_padding => g_tx_runt_padding,
g_dpram_initf => f_find_default_lm32_firmware(g_dpram_initf,g_simulation,g_pcs_16bit),
g_dpram_initf => f_find_default_lm32_firmware(g_dpram_initf, g_simulation, g_pcs_16bit),
g_dpram_size => g_dpram_size,
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
......@@ -373,8 +387,8 @@ begin -- architecture struct
owr_pwren_o => owr_pwren_o,
owr_en_o => owr_en_o,
owr_i => owr_i,
slave_i => slave_i,
slave_o => slave_o,
slave_i => wb_slave_i,
slave_o => wb_slave_o,
aux_master_o => aux_master_out,
aux_master_i => aux_master_in,
wrf_src_o => wrf_src_out,
......
board/spec/wr_spec_pkg.vhd
View file @ b3ad9a9c
......@@ -5,6 +5,7 @@ library work;
use work.wishbone_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wr_board_pkg.all;
package wr_spec_pkg is
......@@ -13,7 +14,8 @@ package wr_spec_pkg is
generic (
g_simulation : integer := 0;
g_with_external_clock_input : boolean := TRUE;
g_fabric_iface : t_board_fabric_iface := PLAIN;
g_aux_clks : integer := 0;
g_fabric_iface : t_board_fabric_iface := plain;
g_tx_streamer_width : integer := 32;
g_rx_streamer_width : integer := 32;
g_dpram_initf : string := "default_xilinx";
......@@ -28,11 +30,13 @@ package wr_spec_pkg is
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_10m_ext_ref_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
rst_62m5_n_o : out std_logic;
rst_125m_n_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic;
......@@ -80,23 +84,37 @@ package wr_spec_pkg is
wrs_rx_dreq_i : in std_logic := '0';
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
pps_ext_i : in std_logic := '0';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1';
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
led_act_o : out std_logic;
led_link_o : out std_logic;
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others =>(others=>'0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
led_act_o : out std_logic);
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
link_ok_o : out std_logic);
end component xwrc_board_spec;
component wrc_board_spec is
generic (
g_simulation : integer := 0;
g_with_external_clock_input : integer := 1;
g_fabric_iface : string := "PLAINFBRC";
g_aux_clks : integer := 0;
g_fabric_iface : string := "plainfbrc";
g_tx_streamer_width : integer := 32;
g_rx_streamer_width : integer := 32;
g_dpram_initf : string := "default_xilinx";
......@@ -112,10 +130,11 @@ package wr_spec_pkg is
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
clk_10m_ext_ref_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
rst_62m5_n_o : out std_logic;
rst_125m_n_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic;
......@@ -199,16 +218,32 @@ package wr_spec_pkg is
wb_eth_err_i : in std_logic := '0';
wb_eth_rty_i : in std_logic := '0';
wb_eth_stall_i : in std_logic := '0';
pps_ext_i : in std_logic;
pps_p_o : out std_logic;
pps_led_o : out std_logic;
aux_diag_i : in std_logic_vector(g_diag_ro_vector_width - 1 downto 0) := (others => '0');
aux_diag_o : out std_logic_vector(g_diag_rw_vector_width - 1 downto 0) := (others => '0');
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
tstamps_stb_o : out std_logic;
tstamps_tsval_o : out std_logic_vector(31 downto 0);
tstamps_port_id_o : out std_logic_vector(5 downto 0);
tstamps_frame_id_o : out std_logic_vector(15 downto 0);
tstamps_incorrect_o : out std_logic;
tstamps_ack_i : in std_logic := '1';
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
led_act_o : out std_logic;
led_link_o : out std_logic;
aux_diag_i : in std_logic_vector(g_diag_ro_vector_width - 1 downto 0) := (others => '0');
aux_diag_o : out std_logic_vector(g_diag_rw_vector_width - 1 downto 0) := (others => '0');
led_act_o : out std_logic);
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
link_ok_o : out std_logic);
end component wrc_board_spec;
end wr_spec_pkg;
board/spec/wrc_board_spec.vhd
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board/spec/xwrc_board_spec.vhd
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board/svec/wr_svec_pkg.vhd
View file @ b3ad9a9c
......@@ -5,6 +5,7 @@ library work;
use work.wishbone_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wr_board_pkg.all;
package wr_svec_pkg is
......@@ -13,7 +14,8 @@ package wr_svec_pkg is
generic (
g_simulation : integer := 0;
g_with_external_clock_input : boolean := TRUE;
g_fabric_iface : t_board_fabric_iface := PLAIN;
g_aux_clks : integer := 0;
g_fabric_iface : t_board_fabric_iface := plain;
g_tx_streamer_width : integer := 32;
g_rx_streamer_width : integer := 32;
g_dpram_initf : string := "default_xilinx";
......@@ -28,10 +30,13 @@ package wr_svec_pkg is
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_10m_ext_ref_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
pll20dac_din_o : out std_logic;
pll20dac_sclk_o : out std_logic;
pll20dac_sync_n_o : out std_logic;
......@@ -81,23 +86,36 @@ package wr_svec_pkg is
wrs_rx_dreq_i : in std_logic := '0';
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
pps_ext_i : in std_logic := '0';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1';
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
led_act_o : out std_logic;
led_link_o : out std_logic;
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others =>(others=>'0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
led_act_o : out std_logic);
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
link_ok_o : out std_logic);
end component xwrc_board_svec;
component wrc_board_svec is
generic (
g_simulation : integer := 0;
g_with_external_clock_input : integer := 1;
g_fabric_iface : string := "PLAINFBRC";
g_aux_clks : integer := 0;
g_fabric_iface : string := "plainfbrc";
g_tx_streamer_width : integer := 32;
g_rx_streamer_width : integer := 32;
g_dpram_initf : string := "default_xilinx";
......@@ -113,9 +131,11 @@ package wr_svec_pkg is
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
clk_10m_ext_ref_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
pll20dac_din_o : out std_logic;
pll20dac_sclk_o : out std_logic;
pll20dac_sync_n_o : out std_logic;
......@@ -201,16 +221,32 @@ package wr_svec_pkg is
wb_eth_err_i : in std_logic := '0';
wb_eth_rty_i : in std_logic := '0';
wb_eth_stall_i : in std_logic := '0';
pps_ext_i : in std_logic;
pps_p_o : out std_logic;
pps_led_o : out std_logic;
aux_diag_i : in std_logic_vector(g_diag_ro_vector_width - 1 downto 0) := (others => '0');
aux_diag_o : out std_logic_vector(g_diag_rw_vector_width - 1 downto 0) := (others => '0');
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
tstamps_stb_o : out std_logic;
tstamps_tsval_o : out std_logic_vector(31 downto 0);
tstamps_port_id_o : out std_logic_vector(5 downto 0);
tstamps_frame_id_o : out std_logic_vector(15 downto 0);
tstamps_incorrect_o : out std_logic;
tstamps_ack_i : in std_logic := '1';
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
led_act_o : out std_logic;
led_link_o : out std_logic;
aux_diag_i : in std_logic_vector(g_diag_ro_vector_width - 1 downto 0) := (others => '0');
aux_diag_o : out std_logic_vector(g_diag_rw_vector_width - 1 downto 0) := (others => '0');
led_act_o : out std_logic);
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
link_ok_o : out std_logic);
end component wrc_board_svec;
end wr_svec_pkg;
board/svec/wrc_board_svec.vhd
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board/svec/xwrc_board_svec.vhd
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board/vfchd/wr_vfchd_pkg.vhd
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board/vfchd/wrc_board_vfchd.vhd
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board/vfchd/xwrc_board_vfchd.vhd
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top/spec_ref_design/spec_wr_ref_top.vhd
View file @ b3ad9a9c
......@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-20
-- Last update: 2017-02-22
-- Last update: 2017-03-08
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the SPEC.
......@@ -428,8 +428,8 @@ begin -- architecture top
clk_10m_ext_ref_i => clk_ext_10m,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
rst_62m5_n_o => rst_sys_62m5_n,
rst_125m_n_o => rst_ref_125m_n,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_125m_n_o => rst_ref_125m_n,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
......
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