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White Rabbit core collection
Commits
b3ad9a9c
Commit
b3ad9a9c
authored
Mar 08, 2017
by
Dimitris Lampridis
Browse files
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Plain Diff
board: bring up more wrpc signals (includign aux_clks)
parent
a9ef1b0c
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Showing
12 changed files
with
1522 additions
and
1209 deletions
+1522
-1209
wr_board_pkg.vhd
board/common/wr_board_pkg.vhd
+95
-95
xwrc_board_common.vhd
board/common/xwrc_board_common.vhd
+66
-52
wr_spec_pkg.vhd
board/spec/wr_spec_pkg.vhd
+209
-174
wrc_board_spec.vhd
board/spec/wrc_board_spec.vhd
+163
-119
xwrc_board_spec.vhd
board/spec/xwrc_board_spec.vhd
+85
-68
wr_svec_pkg.vhd
board/svec/wr_svec_pkg.vhd
+216
-180
wrc_board_svec.vhd
board/svec/wrc_board_svec.vhd
+168
-122
xwrc_board_svec.vhd
board/svec/xwrc_board_svec.vhd
+94
-80
wr_vfchd_pkg.vhd
board/vfchd/wr_vfchd_pkg.vhd
+183
-146
wrc_board_vfchd.vhd
board/vfchd/wrc_board_vfchd.vhd
+148
-100
xwrc_board_vfchd.vhd
board/vfchd/xwrc_board_vfchd.vhd
+92
-70
spec_wr_ref_top.vhd
top/spec_ref_design/spec_wr_ref_top.vhd
+3
-3
No files found.
board/common/wr_board_pkg.vhd
View file @
b3ad9a9c
...
...
@@ -31,13 +31,13 @@ package wr_board_pkg is
return
t_board_fabric_iface
;
function
f_pick_diag_val
(
iface
:
t_board_fabric_iface
;
iface
:
t_board_fabric_iface
;
streamers_val
:
integer
;
application_val
:
integer
)
return
integer
;
function
f_pick_diag_size
(
iface
:
t_board_fabric_iface
;
iface
:
t_board_fabric_iface
;
streamers_size
:
integer
;
application_size
:
integer
)
return
integer
;
...
...
@@ -56,111 +56,111 @@ package wr_board_pkg is
dpram_initf
:
string
;
simulation
:
integer
;
pcs_16_bit
:
boolean
)
return
string
;
return
string
;
component
xwrc_board_common
is
generic
(
g_simulation
:
integer
;
g_with_external_clock_input
:
boolean
;
g_phys_uart
:
boolean
;
g_virtual_uart
:
boolean
;
g_aux_clks
:
integer
;
g_ep_rxbuf_size
:
integer
;
g_tx_runt_padding
:
boolean
;
g_dpram_initf
:
string
;
g_dpram_size
:
integer
;
g_interface_mode
:
t_wishbone_interface_mode
;
g_address_granularity
:
t_wishbone_address_granularity
;
g_aux_sdb
:
t_sdb_device
;
g_softpll_enable_debugger
:
boolean
;
g_vuart_fifo_size
:
integer
;
g_pcs_16bit
:
boolean
;
g_diag_id
:
integer
;
g_diag_ver
:
integer
;
g_diag_ro_size
:
integer
;
g_diag_rw_size
:
integer
;
g_tx_streamer_width
:
integer
;
g_rx_streamer_width
:
integer
;
g_fabric_iface
:
t_board_fabric_iface
);
g_simulation
:
integer
:
=
0
;
g_with_external_clock_input
:
boolean
:
=
TRUE
;
g_phys_uart
:
boolean
:
=
TRUE
;
g_virtual_uart
:
boolean
:
=
TRUE
;
g_aux_clks
:
integer
:
=
0
;
g_ep_rxbuf_size
:
integer
:
=
1024
;
g_tx_runt_padding
:
boolean
:
=
TRUE
;
g_dpram_initf
:
string
:
=
""
;
g_dpram_size
:
integer
:
=
131072
/
4
;
g_interface_mode
:
t_wishbone_interface_mode
:
=
PIPELINED
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
BYTE
;
g_aux_sdb
:
t_sdb_device
:
=
c_wrc_periph3_sdb
;
g_softpll_enable_debugger
:
boolean
:
=
FALSE
;
g_vuart_fifo_size
:
integer
:
=
1024
;
g_pcs_16bit
:
boolean
:
=
FALSE
;
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
g_diag_ro_size
:
integer
:
=
0
;
g_diag_rw_size
:
integer
:
=
0
;
g_tx_streamer_width
:
integer
:
=
32
;
g_rx_streamer_width
:
integer
:
=
32
;
g_fabric_iface
:
t_board_fabric_iface
:
=
PLAIN
);
port
(
clk_sys_i
:
in
std_logic
;
clk_dmtd_i
:
in
std_logic
;
clk_ref_i
:
in
std_logic
;
clk_aux_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
clk_ext_i
:
in
std_logic
:
=
'0'
;
clk_ext_mul_i
:
in
std_logic
:
=
'0'
;
clk_ext_mul_locked_i
:
in
std_logic
:
=
'1'
;
clk_ext_stopped_i
:
in
std_logic
:
=
'0'
;
clk_aux_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
clk_ext_i
:
in
std_logic
:
=
'0'
;
clk_ext_mul_i
:
in
std_logic
:
=
'0'
;
clk_ext_mul_locked_i
:
in
std_logic
:
=
'1'
;
clk_ext_stopped_i
:
in
std_logic
:
=
'0'
;
clk_ext_rst_o
:
out
std_logic
;
pps_ext_i
:
in
std_logic
:
=
'0'
;
pps_ext_i
:
in
std_logic
:
=
'0'
;
rst_n_i
:
in
std_logic
;
dac_hpll_load_p1_o
:
out
std_logic
;
dac_hpll_data_o
:
out
std_logic_vector
(
15
downto
0
);
dac_dpll_load_p1_o
:
out
std_logic
;
dac_dpll_data_o
:
out
std_logic_vector
(
15
downto
0
);
phy8_o
:
out
t_phy_8bits_from_wrc
;
phy8_i
:
in
t_phy_8bits_to_wrc
:
=
c_dummy_phy8_to_wrc
;
phy8_i
:
in
t_phy_8bits_to_wrc
:
=
c_dummy_phy8_to_wrc
;
phy16_o
:
out
t_phy_16bits_from_wrc
;
phy16_i
:
in
t_phy_16bits_to_wrc
:
=
c_dummy_phy16_to_wrc
;
led_act_o
:
out
std_logic
;
led_link_o
:
out
std_logic
;
phy16_i
:
in
t_phy_16bits_to_wrc
:
=
c_dummy_phy16_to_wrc
;
scl_o
:
out
std_logic
;
scl_i
:
in
std_logic
:
=
'1'
;
scl_i
:
in
std_logic
:
=
'1'
;
sda_o
:
out
std_logic
;
sda_i
:
in
std_logic
:
=
'1'
;
sda_i
:
in
std_logic
:
=
'1'
;
sfp_scl_o
:
out
std_logic
;
sfp_scl_i
:
in
std_logic
:
=
'1'
;
sfp_scl_i
:
in
std_logic
:
=
'1'
;
sfp_sda_o
:
out
std_logic
;
sfp_sda_i
:
in
std_logic
:
=
'1'
;
sfp_sda_i
:
in
std_logic
:
=
'1'
;
sfp_det_i
:
in
std_logic
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
spi_sclk_o
:
out
std_logic
;
spi_ncs_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
:
=
'0'
;
uart_rxd_i
:
in
std_logic
:
=
'0'
;
spi_miso_i
:
in
std_logic
:
=
'0'
;
uart_rxd_i
:
in
std_logic
:
=
'0'
;
uart_txd_o
:
out
std_logic
;
owr_pwren_o
:
out
std_logic_vector
(
1
downto
0
);
owr_en_o
:
out
std_logic_vector
(
1
downto
0
);
owr_i
:
in
std_logic_vector
(
1
downto
0
)
:
=
(
others
=>
'1'
);
wb_slave_i
:
in
t_wishbone_slave_in
:
=
cc_dummy_slave_in
;
owr_i
:
in
std_logic_vector
(
1
downto
0
)
:
=
(
others
=>
'1'
);
wb_slave_i
:
in
t_wishbone_slave_in
:
=
cc_dummy_slave_in
;
wb_slave_o
:
out
t_wishbone_slave_out
;
aux_master_o
:
out
t_wishbone_master_out
;
aux_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
aux_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
wrf_src_o
:
out
t_wrf_source_out
;
wrf_src_i
:
in
t_wrf_source_in
:
=
c_dummy_src_in
;
wrf_src_i
:
in
t_wrf_source_in
:
=
c_dummy_src_in
;
wrf_snk_o
:
out
t_wrf_sink_out
;
wrf_snk_i
:
in
t_wrf_sink_in
:
=
c_dummy_snk_in
;
wrf_snk_i
:
in
t_wrf_sink_in
:
=
c_dummy_snk_in
;
wrs_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wb_eth_master_o
:
out
t_wishbone_master_out
;
wb_eth_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
timestamps_o
:
out
t_txtsu_timestamp
;
timestamps_ack_i
:
in
std_logic
:
=
'1'
;
fc_tx_pause_req_i
:
in
std_logic
:
=
'0'
;
fc_tx_pause_delay_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
fc_tx_pause_ready_o
:
out
std_logic
;
tm_link_up_o
:
out
std_logic
;
wb_eth_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
aux_diag_o
:
out
t_generic_word_array
(
g_diag_rw_size
-1
downto
0
);
tm_dac_value_o
:
out
std_logic_vector
(
23
downto
0
);
tm_dac_wr_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tm_clk_aux_lock_en_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
tm_clk_aux_lock_en_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
tm_clk_aux_locked_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
timestamps_o
:
out
t_txtsu_timestamp
;
timestamps_ack_i
:
in
std_logic
:
=
'1'
;
fc_tx_pause_req_i
:
in
std_logic
:
=
'0'
;
fc_tx_pause_delay_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
fc_tx_pause_ready_o
:
out
std_logic
;
tm_link_up_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
led_act_o
:
out
std_logic
;
led_link_o
:
out
std_logic
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
aux_diag_o
:
out
t_generic_word_array
(
g_diag_rw_size
-1
downto
0
);
link_ok_o
:
out
std_logic
);
end
component
xwrc_board_common
;
...
...
@@ -174,7 +174,7 @@ package body wr_board_pkg is
if
iface_type
>=
always_last_invalid
then
assert
FALSE
report
"WR PTP core fabric interface ["
&
t_board_fabric_iface
'image
(
iface_type
)
&
"] is not supported"
severity
failure
;
severity
FAILURE
;
end
if
;
end
procedure
f_check_fabric_iface_type
;
...
...
@@ -183,11 +183,11 @@ package body wr_board_pkg is
begin
assert
(
diag_id
/=
1
)
report
"g_diag_id=1 is reserved for wr_streamers and cannot be set by users"
severity
failure
;
severity
FAILURE
;
assert
(
not
(
diag_id
/=
0
and
diag_ver
=
0
))
report
assert
(
not
(
diag_id
/=
0
and
diag_ver
=
0
))
report
"If diag_id is set by the user (diag_id > 1), g_diag_ver must be at least 1"
severity
failure
;
severity
FAILURE
;
end
procedure
f_check_diag_id
;
function
f_str2iface_type
(
...
...
@@ -207,7 +207,7 @@ package body wr_board_pkg is
-- this function decides what is the diag_id/ver used in the WRPC and MIB for access
-- via SNMP
function
f_pick_diag_val
(
iface
:
t_board_fabric_iface
;
iface
:
t_board_fabric_iface
;
streamers_val
:
integer
;
application_val
:
integer
)
return
integer
is
...
...
@@ -216,15 +216,15 @@ package body wr_board_pkg is
-- use default streamer's id/ver
if
(
iface
=
STREAMERS
and
application_val
=
0
)
then
return
streamers_val
;
else
-- otherwise, use id/ver specified by the user/application. This is the case also
-- when streamers are used.
else
-- otherwise, use id/ver specified by the user/application. This is the case also
-- when streamers are used.
return
application_val
;
end
if
;
end
f_pick_diag_val
;
-- provide the size of the final diag array.
function
f_pick_diag_size
(
iface
:
t_board_fabric_iface
;
iface
:
t_board_fabric_iface
;
streamers_size
:
integer
;
application_size
:
integer
)
return
integer
is
...
...
@@ -232,7 +232,7 @@ package body wr_board_pkg is
-- when streamers are used, concatenate the array of streamers and application/user
if
(
iface
=
STREAMERS
)
then
return
(
streamers_size
+
application_size
);
else
-- otherwise, only the size provided by the application/user
else
-- otherwise, only the size provided by the application/user
return
application_size
;
end
if
;
end
f_pick_diag_size
;
...
...
@@ -245,7 +245,7 @@ package body wr_board_pkg is
begin
assert
(
diag_vector_size
mod
32
=
0
)
report
"g_diag_ro/w_vector_width must have value that is a mutiple of 32"
severity
failure
;
severity
FAILURE
;
for
i
in
0
to
diag_vector_size
/
32-1
loop
result
(
i
*
32-31
downto
i
*
32
)
:
=
diag_in
(
i
);
end
loop
;
...
...
@@ -260,7 +260,7 @@ package body wr_board_pkg is
begin
assert
(
diag_vector_size
mod
32
=
0
)
report
"g_diag_ro/w_vector_width must have value that is a mutiple of 32"
severity
failure
;
severity
FAILURE
;
for
i
in
0
to
diag_vector_size
/
32-1
loop
result
(
i
)
:
=
diag_in
(
i
*
32-31
downto
i
*
32
);
end
loop
;
...
...
@@ -273,43 +273,43 @@ package body wr_board_pkg is
pcs_16_bit
:
boolean
)
return
string
is
begin
if
((
dpram_initf
=
"default_altera"
or
dpram_initf
=
"default_xilinx"
)
and
pcs_16_bit
=
TRUE
)
then
if
((
dpram_initf
=
"default_altera"
or
dpram_initf
=
"default_xilinx"
)
and
pcs_16_bit
=
TRUE
)
then
assert
FALSE
report
"[Board:Software for LM32 in WR Core] No release binary for "
&
"pcs_16_bit."
severity
failure
;
report
"[Board:Software for LM32 in WR Core] No release binary for "
&
"pcs_16_bit."
severity
FAILURE
;
return
""
;
elsif
(
dpram_initf
/=
"default_altera"
and
dpram_initf
/=
"default_xilinx"
)
then
report
"[Board:Software for LM32 in WR Core] Using user-provided LM32 "
&
"firmware ("
&
dpram_initf
&
")."
severity
note
;
"firmware ("
&
dpram_initf
&
")."
severity
NOTE
;
return
dpram_initf
;
elsif
(
simulation
=
0
and
dpram_initf
=
"default_altera"
and
pcs_16_bit
=
FALSE
and
dpram_initf_default_altera_phy8
/=
""
)
then
elsif
(
simulation
=
0
and
dpram_initf
=
"default_altera"
and
pcs_16_bit
=
FALSE
and
dpram_initf_default_altera_phy8
/=
""
)
then
report
"[Board:Software for LM32 in WR Core] Using release LM32 firmware "
&
"(altera, phy8)."
severity
note
;
"(altera, phy8)."
severity
NOTE
;
return
dpram_initf_default_altera_phy8
;
elsif
(
simulation
=
0
and
dpram_initf
=
"default_xilinx"
and
pcs_16_bit
=
FALSE
and
dpram_initf_default_xilinx_phy8
/=
""
)
then
elsif
(
simulation
=
0
and
dpram_initf
=
"default_xilinx"
and
pcs_16_bit
=
FALSE
and
dpram_initf_default_xilinx_phy8
/=
""
)
then
report
"[Board:Software for LM32 in WR Core] Using release LM32 firmware "
&
"(xilnix, phy8)"
severity
note
;
"(xilnix, phy8)"
severity
NOTE
;
return
dpram_initf_default_xilinx_phy8
;
elsif
(
simulation
=
1
and
dpram_initf
=
"default_altera"
and
pcs_16_bit
=
FALSE
and
dpram_initf_default_altera_phy8_sim
/=
""
)
then
elsif
(
simulation
=
1
and
dpram_initf
=
"default_altera"
and
pcs_16_bit
=
FALSE
and
dpram_initf_default_altera_phy8_sim
/=
""
)
then
report
"Board:[Software for LM32 in WR Core] Using release LM32 firmware "
&
"(altera, phy8, sim)."
severity
note
;
"(altera, phy8, sim)."
severity
NOTE
;
return
dpram_initf_default_altera_phy8_sim
;
elsif
(
simulation
=
1
and
dpram_initf
=
"default_xilinx"
and
pcs_16_bit
=
FALSE
and
dpram_initf_default_xilinx_phy8_sim
/=
""
)
then
elsif
(
simulation
=
1
and
dpram_initf
=
"default_xilinx"
and
pcs_16_bit
=
FALSE
and
dpram_initf_default_xilinx_phy8_sim
/=
""
)
then
report
"[Board:Software for LM32 in WR Core] Using release LM32 firmware "
&
"(xilinx, phy8, sim)."
severity
note
;
"(xilinx, phy8, sim)."
severity
NOTE
;
return
dpram_initf_default_xilinx_phy8_sim
;
else
assert
FALSE
report
"[Board:Software for LM32 in WR Core] Default inclussion of LM32"
&
"binary with software is not supported yet. In your instantiation"
&
"of the board (xwrc_board_{spec,svec,vfchd} set g_dpram_initf to the"
&
"correct path, i.e."
&
"<your wr-cores location>/bin/wrpc/wrc_phy8_sim.{bram, mif} "
severity
failure
;
report
"[Board:Software for LM32 in WR Core] Default inclussion of LM32"
&
"binary with software is not supported yet. In your instantiation"
&
"of the board (xwrc_board_{spec,svec,vfchd} set g_dpram_initf to the"
&
"correct path, i.e."
&
"<your wr-cores location>/bin/wrpc/wrc_phy8_sim.{bram, mif} "
severity
FAILURE
;
return
""
;
end
if
;
end
function
;
...
...
board/common/xwrc_board_common.vhd
View file @
b3ad9a9c
...
...
@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-22
-- Last update: 2017-03-0
7
-- Last update: 2017-03-0
8
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Wrapper for WR PTP core with common features shared between
...
...
@@ -120,21 +120,25 @@ entity xwrc_board_common is
phy16_i
:
in
t_phy_16bits_to_wrc
:
=
c_dummy_phy16_to_wrc
;
---------------------------------------------------------------------------
--GPIO
-- I2C EEPROM
---------------------------------------------------------------------------
scl_o
:
out
std_logic
;
scl_i
:
in
std_logic
:
=
'1'
;
sda_o
:
out
std_logic
;
sda_i
:
in
std_logic
:
=
'1'
;
---------------------------------------------------------------------------
-- SFP management info
---------------------------------------------------------------------------
sfp_scl_o
:
out
std_logic
;
sfp_scl_i
:
in
std_logic
:
=
'1'
;
sfp_sda_o
:
out
std_logic
;
sfp_sda_i
:
in
std_logic
:
=
'1'
;
sfp_det_i
:
in
std_logic
;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
led_act_o
:
out
std_logic
;
led_link_o
:
out
std_logic
;
scl_o
:
out
std_logic
;
scl_i
:
in
std_logic
:
=
'1'
;
sda_o
:
out
std_logic
;
sda_i
:
in
std_logic
:
=
'1'
;
sfp_scl_o
:
out
std_logic
;
sfp_scl_i
:
in
std_logic
:
=
'1'
;
sfp_sda_o
:
out
std_logic
;
sfp_sda_i
:
in
std_logic
:
=
'1'
;
sfp_det_i
:
in
std_logic
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
spi_sclk_o
:
out
std_logic
;
spi_ncs_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
...
...
@@ -174,15 +178,15 @@ entity xwrc_board_common is
-- WR streamers (when g_fabric_iface = STREAMERS)
---------------------------------------------------------------------------
wrs_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
---------------------------------------------------------------------------
-- Etherbone WB master interface (when g_fabric_iface = ETHERBONE)
...
...
@@ -190,6 +194,20 @@ entity xwrc_board_common is
wb_eth_master_o
:
out
t_wishbone_master_out
;
wb_eth_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
---------------------------------------------------------------------------
-- Generic diagnostics interface (access from WRPC via SNMP or uart console
---------------------------------------------------------------------------
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
aux_diag_o
:
out
t_generic_word_array
(
g_diag_rw_size
-1
downto
0
);
---------------------------------------------------------------------------
-- Aux clocks control
---------------------------------------------------------------------------
tm_dac_value_o
:
out
std_logic_vector
(
23
downto
0
);
tm_dac_wr_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tm_clk_aux_lock_en_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
tm_clk_aux_locked_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
---------------------------------------------------------------------------
-- External Tx Timestamping I/F
---------------------------------------------------------------------------
...
...
@@ -204,29 +222,25 @@ entity xwrc_board_common is
fc_tx_pause_ready_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- Timecode
/Servo Control
-- Timecode
I/F
---------------------------------------------------------------------------
tm_link_up_o
:
out
std_logic
;
-- DAC Control
tm_dac_value_o
:
out
std_logic_vector
(
23
downto
0
);
tm_dac_wr_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
-- Aux clock lock enable
tm_clk_aux_lock_en_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
-- Aux clock locked flag
tm_clk_aux_locked_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
-- Timecode output
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
-- 1PPS output
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
tm_link_up_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
-- access from WRPC (via SNMP or uart console) to applications for diagnostics (generic)
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
aux_diag_o
:
out
t_generic_word_array
(
g_diag_rw_size
-1
downto
0
);
link_ok_o
:
out
std_logic
---------------------------------------------------------------------------
-- Buttons, LEDs and PPS output
---------------------------------------------------------------------------
led_act_o
:
out
std_logic
;
led_link_o
:
out
std_logic
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
-- 1PPS output
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
-- Link ok indication
link_ok_o
:
out
std_logic
);
end
entity
xwrc_board_common
;
...
...
@@ -262,16 +276,16 @@ architecture struct of xwrc_board_common is
-- Application diagnostic words are added after streamer's diagnostics in the array that
-- goes to/from WRPC
constant
c_streamers_diag_id
:
integer
:
=
1
;
-- id reserved for streamers
constant
c_streamers_diag_ver
:
integer
:
=
1
;
-- version that will be probably increased
-- when more diagnostics is added to streamers
constant
c_streamers_diag_id
:
integer
:
=
1
;
-- id reserved for streamers
constant
c_streamers_diag_ver
:
integer
:
=
1
;
-- version that will be probably increased
-- when more diagnostics is added to streamers
-- final values that go to WRPC generics (depend on configuration)
constant
c_diag_id
:
integer
:
=
f_pick_diag_val
(
g_fabric_iface
,
c_streamers_diag_id
,
g_diag_id
);
constant
c_diag_ver
:
integer
:
=
f_pick_diag_val
(
g_fabric_iface
,
c_streamers_diag_id
,
g_diag_id
);
constant
c_diag_id
:
integer
:
=
f_pick_diag_val
(
g_fabric_iface
,
c_streamers_diag_id
,
g_diag_id
);
constant
c_diag_ver
:
integer
:
=
f_pick_diag_val
(
g_fabric_iface
,
c_streamers_diag_id
,
g_diag_id
);
constant
c_diag_ro_size
:
integer
:
=
f_pick_diag_size
(
g_fabric_iface
,
c_WR_TRANS_ARR_SIZE_OUT
,
g_diag_ro_size
);
constant
c_diag_rw_size
:
integer
:
=
f_pick_diag_size
(
g_fabric_iface
,
c_WR_TRANS_ARR_SIZE_IN
,
g_diag_rw_size
);
constant
c_diag_rw_size
:
integer
:
=
f_pick_diag_size
(
g_fabric_iface
,
c_WR_TRANS_ARR_SIZE_IN
,
g_diag_rw_size
);
-- WR SNMP
signal
aux_diag_in
:
t_generic_word_array
(
c_diag_ro_size
-1
downto
0
);
...
...
@@ -285,7 +299,7 @@ begin -- architecture struct
-- check whether diag id and version are correct, i.e.:
-- * diag_id =1 is reserved for wr_streamers and cannot be used
-- * diag_ver values should start with 1
f_check_diag_id
(
g_diag_id
,
g_diag_ver
);
f_check_diag_id
(
g_diag_id
,
g_diag_ver
);
-----------------------------------------------------------------------------
-- The WR PTP core itself
...
...
@@ -300,7 +314,7 @@ begin -- architecture struct
g_aux_clks
=>
g_aux_clks
,
g_ep_rxbuf_size
=>
g_ep_rxbuf_size
,
g_tx_runt_padding
=>
g_tx_runt_padding
,
g_dpram_initf
=>
f_find_default_lm32_firmware
(
g_dpram_initf
,
g_simulation
,
g_pcs_16bit
),
g_dpram_initf
=>
f_find_default_lm32_firmware
(
g_dpram_initf
,
g_simulation
,
g_pcs_16bit
),
g_dpram_size
=>
g_dpram_size
,
g_interface_mode
=>
g_interface_mode
,
g_address_granularity
=>
g_address_granularity
,
...
...
@@ -373,8 +387,8 @@ begin -- architecture struct
owr_pwren_o
=>
owr_pwren_o
,
owr_en_o
=>
owr_en_o
,
owr_i
=>
owr_i
,
slave_i
=>
slave_i
,
slave_o
=>
slave_o
,
slave_i
=>
wb_
slave_i
,
slave_o
=>
wb_
slave_o
,
aux_master_o
=>
aux_master_out
,
aux_master_i
=>
aux_master_in
,
wrf_src_o
=>
wrf_src_out
,
...
...
@@ -444,8 +458,8 @@ begin -- architecture struct
aux_master_o
<=
cc_dummy_master_out
;
wb_eth_master_o
<=
cc_dummy_master_out
;
aux_diag_in
(
c_diag_ro_size
-1
downto
c_WR_TRANS_ARR_SIZE_OUT
)
<=
aux_diag_i
;
aux_diag_o
<=
aux_diag_out
(
c_diag_rw_size
-1
downto
c_WR_TRANS_ARR_SIZE_IN
);
aux_diag_in
(
c_diag_ro_size
-1
downto
c_WR_TRANS_ARR_SIZE_OUT
)
<=
aux_diag_i
;
aux_diag_o
<=
aux_diag_out
(
c_diag_rw_size
-1
downto
c_WR_TRANS_ARR_SIZE_IN
);
end
generate
gen_wr_streamers
;
...
...
board/spec/wr_spec_pkg.vhd
View file @
b3ad9a9c
...
...
@@ -5,6 +5,7 @@ library work;
use
work
.
wishbone_pkg
.
all
;
use
work
.
wrcore_pkg
.
all
;
use
work
.
wr_fabric_pkg
.
all
;
use
work
.
endpoint_pkg
.
all
;
use
work
.
wr_board_pkg
.
all
;
package
wr_spec_pkg
is
...
...
@@ -13,7 +14,8 @@ package wr_spec_pkg is
generic
(
g_simulation
:
integer
:
=
0
;
g_with_external_clock_input
:
boolean
:
=
TRUE
;
g_fabric_iface
:
t_board_fabric_iface
:
=
PLAIN
;
g_aux_clks
:
integer
:
=
0
;
g_fabric_iface
:
t_board_fabric_iface
:
=
plain
;
g_tx_streamer_width
:
integer
:
=
32
;
g_rx_streamer_width
:
integer
:
=
32
;
g_dpram_initf
:
string
:
=
"default_xilinx"
;
...
...
@@ -22,81 +24,97 @@ package wr_spec_pkg is
g_diag_ro_size
:
integer
:
=
0
;
g_diag_rw_size
:
integer
:
=
0
);
port
(
areset_n_i
:
in
std_logic
;
clk_20m_vcxo_i
:
in
std_logic
;
clk_125m_pllref_p_i
:
in
std_logic
;
clk_125m_pllref_n_i
:
in
std_logic
;
clk_125m_gtp_n_i
:
in
std_logic
;
clk_125m_gtp_p_i
:
in
std_logic
;
clk_10m_ext_ref_i
:
in
std_logic
:
=
'0'
;
clk_sys_62m5_o
:
out
std_logic
;
clk_ref_125m_o
:
out
std_logic
;
rst_62m5_n_o
:
out
std_logic
;
rst_125m_n_o
:
out
std_logic
;
plldac_sclk_o
:
out
std_logic
;
plldac_din_o
:
out
std_logic
;
pll25dac_cs_n_o
:
out
std_logic
;
pll20dac_cs_n_o
:
out
std_logic
;
sfp_txp_o
:
out
std_logic
;
sfp_txn_o
:
out
std_logic
;
sfp_rxp_i
:
in
std_logic
;
sfp_rxn_i
:
in
std_logic
;
sfp_det_i
:
in
std_logic
:
=
'1'
;
sfp_sda_i
:
in
std_logic
;
sfp_sda_o
:
out
std_logic
;
sfp_scl_i
:
in
std_logic
;
sfp_scl_o
:
out
std_logic
;
sfp_rate_select_o
:
out
std_logic
;
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_los_i
:
in
std_logic
:
=
'0'
;
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
eeprom_scl_o
:
out
std_logic
;
onewire_i
:
in
std_logic
;
onewire_oen_o
:
out
std_logic
;
uart_rxd_i
:
in
std_logic
;
uart_txd_o
:
out
std_logic
;
flash_sclk_o
:
out
std_logic
;
flash_ncs_o
:
out
std_logic
;
flash_mosi_o
:
out
std_logic
;
flash_miso_i
:
in
std_logic
;
wb_slave_o
:
out
t_wishbone_slave_out
;
wb_slave_i
:
in
t_wishbone_slave_in
:
=
cc_dummy_slave_in
;
wrf_src_o
:
out
t_wrf_source_out
;
wrf_src_i
:
in
t_wrf_source_in
:
=
c_dummy_src_in
;
wrf_snk_o
:
out
t_wrf_sink_out
;
wrf_snk_i
:
in
t_wrf_sink_in
:
=
c_dummy_snk_in
;
wrs_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wb_eth_master_o
:
out
t_wishbone_master_out
;
wb_eth_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
pps_ext_i
:
in
std_logic
:
=
'0'
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
led_link_o
:
out
std_logic
;
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
aux_diag_o
:
out
t_generic_word_array
(
g_diag_rw_size
-1
downto
0
);
led_act_o
:
out
std_logic
);
areset_n_i
:
in
std_logic
;
clk_20m_vcxo_i
:
in
std_logic
;
clk_125m_pllref_p_i
:
in
std_logic
;
clk_125m_pllref_n_i
:
in
std_logic
;
clk_125m_gtp_n_i
:
in
std_logic
;
clk_125m_gtp_p_i
:
in
std_logic
;
clk_aux_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
clk_10m_ext_ref_i
:
in
std_logic
:
=
'0'
;
pps_ext_i
:
in
std_logic
:
=
'0'
;
clk_sys_62m5_o
:
out
std_logic
;
clk_ref_125m_o
:
out
std_logic
;
rst_sys_62m5_n_o
:
out
std_logic
;
rst_ref_125m_n_o
:
out
std_logic
;
plldac_sclk_o
:
out
std_logic
;
plldac_din_o
:
out
std_logic
;
pll25dac_cs_n_o
:
out
std_logic
;
pll20dac_cs_n_o
:
out
std_logic
;
sfp_txp_o
:
out
std_logic
;
sfp_txn_o
:
out
std_logic
;
sfp_rxp_i
:
in
std_logic
;
sfp_rxn_i
:
in
std_logic
;
sfp_det_i
:
in
std_logic
:
=
'1'
;
sfp_sda_i
:
in
std_logic
;
sfp_sda_o
:
out
std_logic
;
sfp_scl_i
:
in
std_logic
;
sfp_scl_o
:
out
std_logic
;
sfp_rate_select_o
:
out
std_logic
;
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_los_i
:
in
std_logic
:
=
'0'
;
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
eeprom_scl_o
:
out
std_logic
;
onewire_i
:
in
std_logic
;
onewire_oen_o
:
out
std_logic
;
uart_rxd_i
:
in
std_logic
;
uart_txd_o
:
out
std_logic
;
flash_sclk_o
:
out
std_logic
;
flash_ncs_o
:
out
std_logic
;
flash_mosi_o
:
out
std_logic
;
flash_miso_i
:
in
std_logic
;
wb_slave_o
:
out
t_wishbone_slave_out
;
wb_slave_i
:
in
t_wishbone_slave_in
:
=
cc_dummy_slave_in
;
wrf_src_o
:
out
t_wrf_source_out
;
wrf_src_i
:
in
t_wrf_source_in
:
=
c_dummy_src_in
;
wrf_snk_o
:
out
t_wrf_sink_out
;
wrf_snk_i
:
in
t_wrf_sink_in
:
=
c_dummy_snk_in
;
wrs_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wb_eth_master_o
:
out
t_wishbone_master_out
;
wb_eth_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
aux_diag_o
:
out
t_generic_word_array
(
g_diag_rw_size
-1
downto
0
);
tm_dac_value_o
:
out
std_logic_vector
(
23
downto
0
);
tm_dac_wr_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tm_clk_aux_lock_en_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
tm_clk_aux_locked_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
timestamps_o
:
out
t_txtsu_timestamp
;
timestamps_ack_i
:
in
std_logic
:
=
'1'
;
fc_tx_pause_req_i
:
in
std_logic
:
=
'0'
;
fc_tx_pause_delay_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
fc_tx_pause_ready_o
:
out
std_logic
;
tm_link_up_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
led_act_o
:
out
std_logic
;
led_link_o
:
out
std_logic
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
link_ok_o
:
out
std_logic
);
end
component
xwrc_board_spec
;
component
wrc_board_spec
is
generic
(
g_simulation
:
integer
:
=
0
;
g_with_external_clock_input
:
integer
:
=
1
;
g_fabric_iface
:
string
:
=
"PLAINFBRC"
;
g_aux_clks
:
integer
:
=
0
;
g_fabric_iface
:
string
:
=
"plainfbrc"
;
g_tx_streamer_width
:
integer
:
=
32
;
g_rx_streamer_width
:
integer
:
=
32
;
g_dpram_initf
:
string
:
=
"default_xilinx"
;
...
...
@@ -105,110 +123,127 @@ package wr_spec_pkg is
g_diag_ro_vector_width
:
integer
:
=
0
;
g_diag_rw_vector_width
:
integer
:
=
0
);
port
(
areset_n_i
:
in
std_logic
;
clk_20m_vcxo_i
:
in
std_logic
;
clk_125m_pllref_p_i
:
in
std_logic
;
clk_125m_pllref_n_i
:
in
std_logic
;
clk_125m_gtp_n_i
:
in
std_logic
;
clk_125m_gtp_p_i
:
in
std_logic
;
clk_10m_ext_ref_i
:
in
std_logic
:
=
'0'
;
clk_sys_62m5_o
:
out
std_logic
;
clk_ref_125m_o
:
out
std_logic
;
rst_62m5_n_o
:
out
std_logic
;
rst_125m_n_o
:
out
std_logic
;
plldac_sclk_o
:
out
std_logic
;
plldac_din_o
:
out
std_logic
;
pll25dac_cs_n_o
:
out
std_logic
;
pll20dac_cs_n_o
:
out
std_logic
;
sfp_txp_o
:
out
std_logic
;
sfp_txn_o
:
out
std_logic
;
sfp_rxp_i
:
in
std_logic
;
sfp_rxn_i
:
in
std_logic
;
sfp_det_i
:
in
std_logic
:
=
'1'
;
sfp_sda_i
:
in
std_logic
;
sfp_sda_o
:
out
std_logic
;
sfp_scl_i
:
in
std_logic
;
sfp_scl_o
:
out
std_logic
;
sfp_rate_select_o
:
out
std_logic
;
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_los_i
:
in
std_logic
:
=
'0'
;
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
eeprom_scl_o
:
out
std_logic
;
onewire_i
:
in
std_logic
;
onewire_oen_o
:
out
std_logic
;
uart_rxd_i
:
in
std_logic
;
uart_txd_o
:
out
std_logic
;
flash_sclk_o
:
out
std_logic
;
flash_ncs_o
:
out
std_logic
;
flash_mosi_o
:
out
std_logic
;
flash_miso_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_sel_i
:
in
std_logic_vector
(
c_wishbone_address_width
/
8-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_we_i
:
in
std_logic
:
=
'0'
;
wb_cyc_i
:
in
std_logic
:
=
'0'
;
wb_stb_i
:
in
std_logic
:
=
'0'
;
wb_ack_o
:
out
std_logic
;
wb_int_o
:
out
std_logic
;
wb_err_o
:
out
std_logic
;
wb_rty_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
wrf_src_adr_o
:
out
std_logic_vector
(
1
downto
0
);
wrf_src_dat_o
:
out
std_logic_vector
(
15
downto
0
);
wrf_src_cyc_o
:
out
std_logic
;
wrf_src_stb_o
:
out
std_logic
;
wrf_src_we_o
:
out
std_logic
;
wrf_src_sel_o
:
out
std_logic_vector
(
1
downto
0
);
wrf_src_ack_i
:
in
std_logic
;
wrf_src_stall_i
:
in
std_logic
;
wrf_src_err_i
:
in
std_logic
;
wrf_src_rty_i
:
in
std_logic
;
wrf_snk_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wrf_snk_dat_i
:
in
std_logic_vector
(
15
downto
0
);
wrf_snk_cyc_i
:
in
std_logic
;
wrf_snk_stb_i
:
in
std_logic
;
wrf_snk_we_i
:
in
std_logic
;
wrf_snk_sel_i
:
in
std_logic_vector
(
1
downto
0
);
wrf_snk_ack_o
:
out
std_logic
;
wrf_snk_stall_o
:
out
std_logic
;
wrf_snk_err_o
:
out
std_logic
;
wrf_snk_rty_o
:
out
std_logic
;
wrs_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wb_eth_adr_o
:
out
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
);
wb_eth_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_eth_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_eth_sel_o
:
out
std_logic_vector
(
c_wishbone_address_width
/
8-1
downto
0
);
wb_eth_we_o
:
out
std_logic
;
wb_eth_cyc_o
:
out
std_logic
;
wb_eth_stb_o
:
out
std_logic
;
wb_eth_ack_i
:
in
std_logic
:
=
'0'
;
wb_eth_int_i
:
in
std_logic
:
=
'0'
;
wb_eth_err_i
:
in
std_logic
:
=
'0'
;
wb_eth_rty_i
:
in
std_logic
:
=
'0'
;
wb_eth_stall_i
:
in
std_logic
:
=
'0'
;
pps_ext_i
:
in
std_logic
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
led_link_o
:
out
std_logic
;
aux_diag_i
:
in
std_logic_vector
(
g_diag_ro_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
aux_diag_o
:
out
std_logic_vector
(
g_diag_rw_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
led_act_o
:
out
std_logic
);
areset_n_i
:
in
std_logic
;
clk_20m_vcxo_i
:
in
std_logic
;
clk_125m_pllref_p_i
:
in
std_logic
;
clk_125m_pllref_n_i
:
in
std_logic
;
clk_125m_gtp_n_i
:
in
std_logic
;
clk_125m_gtp_p_i
:
in
std_logic
;
clk_10m_ext_ref_i
:
in
std_logic
:
=
'0'
;
pps_ext_i
:
in
std_logic
:
=
'0'
;
clk_sys_62m5_o
:
out
std_logic
;
clk_ref_125m_o
:
out
std_logic
;
rst_sys_62m5_n_o
:
out
std_logic
;
rst_ref_125m_n_o
:
out
std_logic
;
plldac_sclk_o
:
out
std_logic
;
plldac_din_o
:
out
std_logic
;
pll25dac_cs_n_o
:
out
std_logic
;
pll20dac_cs_n_o
:
out
std_logic
;
sfp_txp_o
:
out
std_logic
;
sfp_txn_o
:
out
std_logic
;
sfp_rxp_i
:
in
std_logic
;
sfp_rxn_i
:
in
std_logic
;
sfp_det_i
:
in
std_logic
:
=
'1'
;
sfp_sda_i
:
in
std_logic
;
sfp_sda_o
:
out
std_logic
;
sfp_scl_i
:
in
std_logic
;
sfp_scl_o
:
out
std_logic
;
sfp_rate_select_o
:
out
std_logic
;
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_los_i
:
in
std_logic
:
=
'0'
;
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
eeprom_scl_o
:
out
std_logic
;
onewire_i
:
in
std_logic
;
onewire_oen_o
:
out
std_logic
;
uart_rxd_i
:
in
std_logic
;
uart_txd_o
:
out
std_logic
;
flash_sclk_o
:
out
std_logic
;
flash_ncs_o
:
out
std_logic
;
flash_mosi_o
:
out
std_logic
;
flash_miso_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_sel_i
:
in
std_logic_vector
(
c_wishbone_address_width
/
8-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_we_i
:
in
std_logic
:
=
'0'
;
wb_cyc_i
:
in
std_logic
:
=
'0'
;
wb_stb_i
:
in
std_logic
:
=
'0'
;
wb_ack_o
:
out
std_logic
;
wb_int_o
:
out
std_logic
;
wb_err_o
:
out
std_logic
;
wb_rty_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
wrf_src_adr_o
:
out
std_logic_vector
(
1
downto
0
);
wrf_src_dat_o
:
out
std_logic_vector
(
15
downto
0
);
wrf_src_cyc_o
:
out
std_logic
;
wrf_src_stb_o
:
out
std_logic
;
wrf_src_we_o
:
out
std_logic
;
wrf_src_sel_o
:
out
std_logic_vector
(
1
downto
0
);
wrf_src_ack_i
:
in
std_logic
;
wrf_src_stall_i
:
in
std_logic
;
wrf_src_err_i
:
in
std_logic
;
wrf_src_rty_i
:
in
std_logic
;
wrf_snk_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wrf_snk_dat_i
:
in
std_logic_vector
(
15
downto
0
);
wrf_snk_cyc_i
:
in
std_logic
;
wrf_snk_stb_i
:
in
std_logic
;
wrf_snk_we_i
:
in
std_logic
;
wrf_snk_sel_i
:
in
std_logic_vector
(
1
downto
0
);
wrf_snk_ack_o
:
out
std_logic
;
wrf_snk_stall_o
:
out
std_logic
;
wrf_snk_err_o
:
out
std_logic
;
wrf_snk_rty_o
:
out
std_logic
;
wrs_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wb_eth_adr_o
:
out
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
);
wb_eth_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_eth_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_eth_sel_o
:
out
std_logic_vector
(
c_wishbone_address_width
/
8-1
downto
0
);
wb_eth_we_o
:
out
std_logic
;
wb_eth_cyc_o
:
out
std_logic
;
wb_eth_stb_o
:
out
std_logic
;
wb_eth_ack_i
:
in
std_logic
:
=
'0'
;
wb_eth_int_i
:
in
std_logic
:
=
'0'
;
wb_eth_err_i
:
in
std_logic
:
=
'0'
;
wb_eth_rty_i
:
in
std_logic
:
=
'0'
;
wb_eth_stall_i
:
in
std_logic
:
=
'0'
;
aux_diag_i
:
in
std_logic_vector
(
g_diag_ro_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
aux_diag_o
:
out
std_logic_vector
(
g_diag_rw_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
tm_dac_value_o
:
out
std_logic_vector
(
23
downto
0
);
tm_dac_wr_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tm_clk_aux_lock_en_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
tm_clk_aux_locked_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tstamps_stb_o
:
out
std_logic
;
tstamps_tsval_o
:
out
std_logic_vector
(
31
downto
0
);
tstamps_port_id_o
:
out
std_logic_vector
(
5
downto
0
);
tstamps_frame_id_o
:
out
std_logic_vector
(
15
downto
0
);
tstamps_incorrect_o
:
out
std_logic
;
tstamps_ack_i
:
in
std_logic
:
=
'1'
;
fc_tx_pause_req_i
:
in
std_logic
:
=
'0'
;
fc_tx_pause_delay_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
fc_tx_pause_ready_o
:
out
std_logic
;
tm_link_up_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
led_act_o
:
out
std_logic
;
led_link_o
:
out
std_logic
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
link_ok_o
:
out
std_logic
);
end
component
wrc_board_spec
;
end
wr_spec_pkg
;
board/spec/wrc_board_spec.vhd
View file @
b3ad9a9c
...
...
@@ -6,8 +6,8 @@
-- File : wrc_board_spec.vhd
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 201
6
-02-17
-- Last update: 2017-03-0
7
-- Created : 201
7
-02-17
-- Last update: 2017-03-0
8
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
...
...
@@ -59,6 +59,8 @@ entity wrc_board_spec is
g_simulation
:
integer
:
=
0
;
-- Select whether to include external ref clock input
g_with_external_clock_input
:
integer
:
=
1
;
-- Number of aux clocks syntonized by WRPC to WR timebase
g_aux_clks
:
integer
:
=
0
;
-- "plainfbrc" = expose WRC fabric interface
-- "streamers" = attach WRC streamers to fabric interface
-- "etherbone" = attach Etherbone slave to fabric interface
...
...
@@ -69,46 +71,39 @@ entity wrc_board_spec is
-- memory initialisation file for embedded CPU
g_dpram_initf
:
string
:
=
"default_xilinx"
;
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
-- size the generic diag interface
g_diag_ro_vector_width
:
integer
:
=
0
;
g_diag_rw_vector_width
:
integer
:
=
0
g_diag_ro_vector_width
:
integer
:
=
0
;
g_diag_rw_vector_width
:
integer
:
=
0
);
port
(
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Reset from system fpga
areset_n_i
:
in
std_logic
;
areset_n_i
:
in
std_logic
;
-- Clock inputs from the board
clk_20m_vcxo_i
:
in
std_logic
;
clk_125m_pllref_p_i
:
in
std_logic
;
clk_125m_pllref_n_i
:
in
std_logic
;
clk_125m_gtp_n_i
:
in
std_logic
;
clk_125m_gtp_p_i
:
in
std_logic
;
clk_20m_vcxo_i
:
in
std_logic
;
clk_125m_pllref_p_i
:
in
std_logic
;
clk_125m_pllref_n_i
:
in
std_logic
;
clk_125m_gtp_n_i
:
in
std_logic
;
clk_125m_gtp_p_i
:
in
std_logic
;
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_10m_ext_ref_i
:
in
std_logic
:
=
'0'
;
clk_10m_ext_ref_i
:
in
std_logic
:
=
'0'
;
-- External PPS input (g_with_external_clock_input = TRUE)
pps_ext_i
:
in
std_logic
:
=
'0'
;
-- 62.5MHz sys clock output
clk_sys_62m5_o
:
out
std_logic
;
clk_sys_62m5_o
:
out
std_logic
;
-- 125MHz ref clock output
clk_ref_125m_o
:
out
std_logic
;
clk_ref_125m_o
:
out
std_logic
;
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_
62m5_n_o
:
out
std_logic
;
rst_
125m_n_o
:
out
std_logic
;
rst_
sys_62m5_n_o
:
out
std_logic
;
rst_
ref_125m_n_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- Shared SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o
:
out
std_logic
;
plldac_din_o
:
out
std_logic
;
pll25dac_cs_n_o
:
out
std_logic
;
...
...
@@ -117,7 +112,6 @@ entity wrc_board_spec is
---------------------------------------------------------------------------
-- SFP I/O for transceiver and SFP management info
---------------------------------------------------------------------------
sfp_txp_o
:
out
std_logic
;
sfp_txn_o
:
out
std_logic
;
sfp_rxp_i
:
in
std_logic
;
...
...
@@ -135,7 +129,6 @@ entity wrc_board_spec is
---------------------------------------------------------------------------
-- I2C EEPROM
---------------------------------------------------------------------------
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
...
...
@@ -144,21 +137,18 @@ entity wrc_board_spec is
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_i
:
in
std_logic
;
onewire_oen_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i
:
in
std_logic
;
uart_txd_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
flash_sclk_o
:
out
std_logic
;
flash_ncs_o
:
out
std_logic
;
flash_mosi_o
:
out
std_logic
;
...
...
@@ -167,7 +157,6 @@ entity wrc_board_spec is
---------------------------------------------------------------------------
-- External WB interface
---------------------------------------------------------------------------
wb_adr_i
:
in
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
...
...
@@ -184,7 +173,6 @@ entity wrc_board_spec is
---------------------------------------------------------------------------
-- WR fabric interface (when g_fabric_iface = "plain")
---------------------------------------------------------------------------
wrf_src_adr_o
:
out
std_logic_vector
(
1
downto
0
);
wrf_src_dat_o
:
out
std_logic_vector
(
15
downto
0
);
wrf_src_cyc_o
:
out
std_logic
;
...
...
@@ -209,22 +197,20 @@ entity wrc_board_spec is
---------------------------------------------------------------------------
-- WR streamers (when g_fabric_iface = "streamers")
---------------------------------------------------------------------------
wrs_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
---------------------------------------------------------------------------
-- Etherbone WB master interface (when g_fabric_iface = "etherbone")
---------------------------------------------------------------------------
wb_eth_adr_o
:
out
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
);
wb_eth_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_eth_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
...
...
@@ -239,19 +225,57 @@ entity wrc_board_spec is
wb_eth_stall_i
:
in
std_logic
:
=
'0'
;
---------------------------------------------------------------------------
--
WRPC timing interface and status
--
Generic diagnostics interface (access from WRPC via SNMP or uart console
---------------------------------------------------------------------------
aux_diag_i
:
in
std_logic_vector
(
g_diag_ro_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
aux_diag_o
:
out
std_logic_vector
(
g_diag_rw_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
pps_ext_i
:
in
std_logic
:
=
'0'
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- Aux clocks control
---------------------------------------------------------------------------
tm_dac_value_o
:
out
std_logic_vector
(
23
downto
0
);
tm_dac_wr_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tm_clk_aux_lock_en_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
tm_clk_aux_locked_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
---------------------------------------------------------------------------
-- External Tx Timestamping I/F
---------------------------------------------------------------------------
tstamps_stb_o
:
out
std_logic
;
tstamps_tsval_o
:
out
std_logic_vector
(
31
downto
0
);
tstamps_port_id_o
:
out
std_logic_vector
(
5
downto
0
);
tstamps_frame_id_o
:
out
std_logic_vector
(
15
downto
0
);
tstamps_incorrect_o
:
out
std_logic
;
tstamps_ack_i
:
in
std_logic
:
=
'1'
;
---------------------------------------------------------------------------
-- Pause Frame Control
---------------------------------------------------------------------------
fc_tx_pause_req_i
:
in
std_logic
:
=
'0'
;
fc_tx_pause_delay_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
fc_tx_pause_ready_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- Timecode I/F
---------------------------------------------------------------------------
tm_link_up_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
led_link_o
:
out
std_logic
;
aux_diag_i
:
in
std_logic_vector
(
g_diag_ro_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
aux_diag_o
:
out
std_logic_vector
(
g_diag_rw_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
led_act_o
:
out
std_logic
);
---------------------------------------------------------------------------
-- Buttons, LEDs and PPS output
---------------------------------------------------------------------------
led_act_o
:
out
std_logic
;
led_link_o
:
out
std_logic
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
-- 1PPS output
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
-- Link ok indication
link_ok_o
:
out
std_logic
);
end
entity
wrc_board_spec
;
...
...
@@ -277,12 +301,14 @@ architecture std_wrapper of wrc_board_spec is
signal
wb_eth_master_in
:
t_wishbone_master_in
;
-- Aux diagnostics
constant
c_diag_ro_size
:
integer
:
=
g_diag_ro_vector_width
/
32
;
constant
c_diag_rw_size
:
integer
:
=
g_diag_rw_vector_width
/
32
;
constant
c_diag_ro_size
:
integer
:
=
g_diag_ro_vector_width
/
32
;
constant
c_diag_rw_size
:
integer
:
=
g_diag_rw_vector_width
/
32
;
signal
aux_diag_in
:
t_generic_word_array
(
c_diag_ro_size
-1
downto
0
);
signal
aux_diag_out
:
t_generic_word_array
(
c_diag_rw_size
-1
downto
0
);
-- External Tx Timestamping I/F
signal
timestamps_out
:
t_txtsu_timestamp
;
begin
-- architecture struct
...
...
@@ -338,15 +364,20 @@ begin -- architecture struct
wb_eth_master_in
.
rty
<=
wb_eth_rty_i
;
wb_eth_master_in
.
stall
<=
wb_eth_stall_i
;
-- auxiliary diagnostics
aux_diag_in
<=
f_de_vectorize_diag
(
aux_diag_i
,
g_diag_ro_vector_width
);
aux_diag_in
<=
f_de_vectorize_diag
(
aux_diag_i
,
g_diag_ro_vector_width
);
aux_diag_o
<=
f_vectorize_diag
(
aux_diag_out
,
g_diag_rw_vector_width
);
tstamps_stb_o
<=
timestamps_out
.
stb
;
tstamps_tsval_o
<=
timestamps_out
.
tsval
;
tstamps_port_id_o
<=
timestamps_out
.
port_id
;
tstamps_frame_id_o
<=
timestamps_out
.
frame_id
;
-- Instantiate the records-based module
cmp_xwrc_board_spec
:
xwrc_board_spec
generic
map
(
g_simulation
=>
g_simulation
,
g_with_external_clock_input
=>
f_int2bool
(
g_with_external_clock_input
),
g_aux_clks
=>
g_aux_clks
,
g_fabric_iface
=>
f_str2iface_type
(
g_fabric_iface
),
g_tx_streamer_width
=>
g_tx_streamer_width
,
g_rx_streamer_width
=>
g_rx_streamer_width
,
...
...
@@ -356,73 +387,86 @@ begin -- architecture struct
g_diag_ro_size
=>
c_diag_ro_size
,
g_diag_rw_size
=>
c_diag_rw_size
)
port
map
(
areset_n_i
=>
areset_n_i
,
clk_20m_vcxo_i
=>
clk_20m_vcxo_i
,
clk_125m_pllref_p_i
=>
clk_125m_pllref_p_i
,
clk_125m_pllref_n_i
=>
clk_125m_pllref_n_i
,
clk_125m_gtp_n_i
=>
clk_125m_gtp_n_i
,
clk_125m_gtp_p_i
=>
clk_125m_gtp_p_i
,
clk_10m_ext_ref_i
=>
clk_10m_ext_ref_i
,
clk_sys_62m5_o
=>
clk_sys_62m5_o
,
clk_ref_125m_o
=>
clk_ref_125m_o
,
rst_62m5_n_o
=>
rst_62m5_n_o
,
rst_125m_n_o
=>
rst_125m_n_o
,
plldac_din_o
=>
plldac_din_o
,
plldac_sclk_o
=>
plldac_sclk_o
,
pll25dac_cs_n_o
=>
pll25dac_cs_n_o
,
pll20dac_cs_n_o
=>
pll20dac_cs_n_o
,
sfp_txp_o
=>
sfp_txp_o
,
sfp_txn_o
=>
sfp_txn_o
,
sfp_rxp_i
=>
sfp_rxp_i
,
sfp_rxn_i
=>
sfp_rxn_i
,
sfp_det_i
=>
sfp_det_i
,
sfp_sda_i
=>
sfp_sda_i
,
sfp_sda_o
=>
sfp_sda_o
,
sfp_scl_i
=>
sfp_scl_i
,
sfp_scl_o
=>
sfp_scl_o
,
sfp_rate_select_o
=>
sfp_rate_select_o
,
sfp_tx_fault_i
=>
sfp_tx_fault_i
,
sfp_tx_disable_o
=>
sfp_tx_disable_o
,
sfp_los_i
=>
sfp_los_i
,
eeprom_sda_i
=>
eeprom_sda_i
,
eeprom_sda_o
=>
eeprom_sda_o
,
eeprom_scl_i
=>
eeprom_scl_i
,
eeprom_scl_o
=>
eeprom_scl_o
,
onewire_i
=>
onewire_i
,
onewire_oen_o
=>
onewire_oen_o
,
uart_rxd_i
=>
uart_rxd_i
,
uart_txd_o
=>
uart_txd_o
,
flash_sclk_o
=>
flash_sclk_o
,
flash_ncs_o
=>
flash_ncs_o
,
flash_mosi_o
=>
flash_mosi_o
,
flash_miso_i
=>
flash_miso_i
,
wb_slave_o
=>
wb_slave_out
,
wb_slave_i
=>
wb_slave_in
,
wrf_src_o
=>
wrf_src_out
,
wrf_src_i
=>
wrf_src_in
,
wrf_snk_o
=>
wrf_snk_out
,
wrf_snk_i
=>
wrf_snk_in
,
wrs_tx_data_i
=>
wrs_tx_data_i
,
wrs_tx_valid_i
=>
wrs_tx_valid_i
,
wrs_tx_dreq_o
=>
wrs_tx_dreq_o
,
wrs_tx_last_i
=>
wrs_tx_last_i
,
wrs_tx_flush_i
=>
wrs_tx_flush_i
,
wrs_rx_first_o
=>
wrs_rx_first_o
,
wrs_rx_last_o
=>
wrs_rx_last_o
,
wrs_rx_data_o
=>
wrs_rx_data_o
,
wrs_rx_valid_o
=>
wrs_rx_valid_o
,
wrs_rx_dreq_i
=>
wrs_rx_dreq_i
,
wb_eth_master_o
=>
wb_eth_master_out
,
wb_eth_master_i
=>
wb_eth_master_in
,
pps_ext_i
=>
pps_ext_i
,
pps_p_o
=>
pps_p_o
,
pps_led_o
=>
pps_led_o
,
tm_time_valid_o
=>
tm_time_valid_o
,
tm_tai_o
=>
tm_tai_o
,
tm_cycles_o
=>
tm_cycles_o
,
led_link_o
=>
led_link_o
,
aux_diag_i
=>
aux_diag_in
,
aux_diag_o
=>
aux_diag_out
,
led_act_o
=>
led_act_o
);
areset_n_i
=>
areset_n_i
,
clk_20m_vcxo_i
=>
clk_20m_vcxo_i
,
clk_125m_pllref_p_i
=>
clk_125m_pllref_p_i
,
clk_125m_pllref_n_i
=>
clk_125m_pllref_n_i
,
clk_125m_gtp_n_i
=>
clk_125m_gtp_n_i
,
clk_125m_gtp_p_i
=>
clk_125m_gtp_p_i
,
clk_10m_ext_ref_i
=>
clk_10m_ext_ref_i
,
pps_ext_i
=>
pps_ext_i
,
clk_sys_62m5_o
=>
clk_sys_62m5_o
,
clk_ref_125m_o
=>
clk_ref_125m_o
,
rst_sys_62m5_n_o
=>
rst_sys_62m5_n_o
,
rst_ref_125m_n_o
=>
rst_ref_125m_n_o
,
plldac_din_o
=>
plldac_din_o
,
plldac_sclk_o
=>
plldac_sclk_o
,
pll25dac_cs_n_o
=>
pll25dac_cs_n_o
,
pll20dac_cs_n_o
=>
pll20dac_cs_n_o
,
sfp_txp_o
=>
sfp_txp_o
,
sfp_txn_o
=>
sfp_txn_o
,
sfp_rxp_i
=>
sfp_rxp_i
,
sfp_rxn_i
=>
sfp_rxn_i
,
sfp_det_i
=>
sfp_det_i
,
sfp_sda_i
=>
sfp_sda_i
,
sfp_sda_o
=>
sfp_sda_o
,
sfp_scl_i
=>
sfp_scl_i
,
sfp_scl_o
=>
sfp_scl_o
,
sfp_rate_select_o
=>
sfp_rate_select_o
,
sfp_tx_fault_i
=>
sfp_tx_fault_i
,
sfp_tx_disable_o
=>
sfp_tx_disable_o
,
sfp_los_i
=>
sfp_los_i
,
eeprom_sda_i
=>
eeprom_sda_i
,
eeprom_sda_o
=>
eeprom_sda_o
,
eeprom_scl_i
=>
eeprom_scl_i
,
eeprom_scl_o
=>
eeprom_scl_o
,
onewire_i
=>
onewire_i
,
onewire_oen_o
=>
onewire_oen_o
,
uart_rxd_i
=>
uart_rxd_i
,
uart_txd_o
=>
uart_txd_o
,
flash_sclk_o
=>
flash_sclk_o
,
flash_ncs_o
=>
flash_ncs_o
,
flash_mosi_o
=>
flash_mosi_o
,
flash_miso_i
=>
flash_miso_i
,
wb_slave_o
=>
wb_slave_out
,
wb_slave_i
=>
wb_slave_in
,
wrf_src_o
=>
wrf_src_out
,
wrf_src_i
=>
wrf_src_in
,
wrf_snk_o
=>
wrf_snk_out
,
wrf_snk_i
=>
wrf_snk_in
,
wrs_tx_data_i
=>
wrs_tx_data_i
,
wrs_tx_valid_i
=>
wrs_tx_valid_i
,
wrs_tx_dreq_o
=>
wrs_tx_dreq_o
,
wrs_tx_last_i
=>
wrs_tx_last_i
,
wrs_tx_flush_i
=>
wrs_tx_flush_i
,
wrs_rx_first_o
=>
wrs_rx_first_o
,
wrs_rx_last_o
=>
wrs_rx_last_o
,
wrs_rx_data_o
=>
wrs_rx_data_o
,
wrs_rx_valid_o
=>
wrs_rx_valid_o
,
wrs_rx_dreq_i
=>
wrs_rx_dreq_i
,
wb_eth_master_o
=>
wb_eth_master_out
,
wb_eth_master_i
=>
wb_eth_master_in
,
aux_diag_i
=>
aux_diag_in
,
aux_diag_o
=>
aux_diag_out
,
tm_dac_value_o
=>
tm_dac_value_o
,
tm_dac_wr_o
=>
tm_dac_wr_o
,
tm_clk_aux_lock_en_i
=>
tm_clk_aux_lock_en_i
,
tm_clk_aux_locked_o
=>
tm_clk_aux_locked_o
,
timestamps_o
=>
timestamps_out
,
timestamps_ack_i
=>
tstamps_ack_i
,
fc_tx_pause_req_i
=>
fc_tx_pause_req_i
,
fc_tx_pause_delay_i
=>
fc_tx_pause_delay_i
,
fc_tx_pause_ready_o
=>
fc_tx_pause_ready_o
,
tm_link_up_o
=>
tm_link_up_o
,
tm_time_valid_o
=>
tm_time_valid_o
,
tm_tai_o
=>
tm_tai_o
,
tm_cycles_o
=>
tm_cycles_o
,
led_act_o
=>
led_act_o
,
led_link_o
=>
led_link_o
,
btn1_i
=>
btn1_i
,
btn2_i
=>
btn2_i
,
pps_p_o
=>
pps_p_o
,
pps_led_o
=>
pps_led_o
,
link_ok_o
=>
link_ok_o
);
end
architecture
std_wrapper
;
board/spec/xwrc_board_spec.vhd
View file @
b3ad9a9c
...
...
@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-17
-- Last update: 2017-03-0
7
-- Last update: 2017-03-0
8
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
...
...
@@ -60,6 +60,8 @@ entity xwrc_board_spec is
g_simulation
:
integer
:
=
0
;
-- Select whether to include external ref clock input
g_with_external_clock_input
:
boolean
:
=
TRUE
;
-- Number of aux clocks syntonized by WRPC to WR timebase
g_aux_clks
:
integer
:
=
0
;
-- plain = expose WRC fabric interface
-- streamers = attach WRC streamers to fabric interface
-- etherbone = attach Etherbone slave to fabric interface
...
...
@@ -70,46 +72,41 @@ entity xwrc_board_spec is
-- memory initialisation file for embedded CPU
g_dpram_initf
:
string
:
=
"default_xilinx"
;
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
-- size the generic diag interface
g_diag_ro_size
:
integer
:
=
0
;
g_diag_rw_size
:
integer
:
=
0
g_diag_ro_size
:
integer
:
=
0
;
g_diag_rw_size
:
integer
:
=
0
);
port
(
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Reset input (active low, can be async)
areset_n_i
:
in
std_logic
;
areset_n_i
:
in
std_logic
;
-- Clock inputs from the board
clk_20m_vcxo_i
:
in
std_logic
;
clk_125m_pllref_p_i
:
in
std_logic
;
clk_125m_pllref_n_i
:
in
std_logic
;
clk_125m_gtp_n_i
:
in
std_logic
;
clk_125m_gtp_p_i
:
in
std_logic
;
clk_20m_vcxo_i
:
in
std_logic
;
clk_125m_pllref_p_i
:
in
std_logic
;
clk_125m_pllref_n_i
:
in
std_logic
;
clk_125m_gtp_n_i
:
in
std_logic
;
clk_125m_gtp_p_i
:
in
std_logic
;
-- Aux clocks, which can be disciplined by the WR Core
clk_aux_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_10m_ext_ref_i
:
in
std_logic
:
=
'0'
;
clk_10m_ext_ref_i
:
in
std_logic
:
=
'0'
;
-- External PPS input (g_with_external_clock_input = TRUE)
pps_ext_i
:
in
std_logic
:
=
'0'
;
-- 62.5MHz sys clock output
clk_sys_62m5_o
:
out
std_logic
;
clk_sys_62m5_o
:
out
std_logic
;
-- 125MHz ref clock output
clk_ref_125m_o
:
out
std_logic
;
clk_ref_125m_o
:
out
std_logic
;
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_
62m5_n_o
:
out
std_logic
;
rst_
125m_n_o
:
out
std_logic
;
rst_
sys_62m5_n_o
:
out
std_logic
;
rst_
ref_125m_n_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- Shared SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o
:
out
std_logic
;
plldac_din_o
:
out
std_logic
;
pll25dac_cs_n_o
:
out
std_logic
;
...
...
@@ -118,7 +115,6 @@ entity xwrc_board_spec is
---------------------------------------------------------------------------
-- SFP I/O for transceiver and SFP management info
---------------------------------------------------------------------------
sfp_txp_o
:
out
std_logic
;
sfp_txn_o
:
out
std_logic
;
sfp_rxp_i
:
in
std_logic
;
...
...
@@ -136,7 +132,6 @@ entity xwrc_board_spec is
---------------------------------------------------------------------------
-- I2C EEPROM
---------------------------------------------------------------------------
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
...
...
@@ -145,21 +140,18 @@ entity xwrc_board_spec is
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_i
:
in
std_logic
;
onewire_oen_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i
:
in
std_logic
;
uart_txd_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
flash_sclk_o
:
out
std_logic
;
flash_ncs_o
:
out
std_logic
;
flash_mosi_o
:
out
std_logic
;
...
...
@@ -168,14 +160,12 @@ entity xwrc_board_spec is
---------------------------------------------------------------------------
-- External WB interface
---------------------------------------------------------------------------
wb_slave_o
:
out
t_wishbone_slave_out
;
wb_slave_i
:
in
t_wishbone_slave_in
:
=
cc_dummy_slave_in
;
---------------------------------------------------------------------------
-- WR fabric interface (when g_fabric_iface = "plainfbrc")
---------------------------------------------------------------------------
wrf_src_o
:
out
t_wrf_source_out
;
wrf_src_i
:
in
t_wrf_source_in
:
=
c_dummy_src_in
;
wrf_snk_o
:
out
t_wrf_sink_out
;
...
...
@@ -184,44 +174,71 @@ entity xwrc_board_spec is
---------------------------------------------------------------------------
-- WR streamers (when g_fabric_iface = "streamers")
---------------------------------------------------------------------------
wrs_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
---------------------------------------------------------------------------
-- Etherbone WB master interface (when g_fabric_iface = "etherbone")
---------------------------------------------------------------------------
wb_eth_master_o
:
out
t_wishbone_master_out
;
wb_eth_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
---------------------------------------------------------------------------
-- Generic diagnostics interface (access from WRPC via SNMP or uart console
---------------------------------------------------------------------------
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
aux_diag_o
:
out
t_generic_word_array
(
g_diag_rw_size
-1
downto
0
);
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
aux_diag_o
:
out
t_generic_word_array
(
g_diag_rw_size
-1
downto
0
);
---------------------------------------------------------------------------
-- Aux clocks control
---------------------------------------------------------------------------
tm_dac_value_o
:
out
std_logic_vector
(
23
downto
0
);
tm_dac_wr_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tm_clk_aux_lock_en_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
tm_clk_aux_locked_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
---------------------------------------------------------------------------
--
WRPC timing interface and status
--
External Tx Timestamping I/F
---------------------------------------------------------------------------
timestamps_o
:
out
t_txtsu_timestamp
;
timestamps_ack_i
:
in
std_logic
:
=
'1'
;
pps_ext_i
:
in
std_logic
:
=
'0'
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- Pause Frame Control
---------------------------------------------------------------------------
fc_tx_pause_req_i
:
in
std_logic
:
=
'0'
;
fc_tx_pause_delay_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
fc_tx_pause_ready_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- Timecode I/F
---------------------------------------------------------------------------
tm_link_up_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
led_link_o
:
out
std_logic
;
led_act_o
:
out
std_logic
);
---------------------------------------------------------------------------
-- Buttons, LEDs and PPS output
---------------------------------------------------------------------------
led_act_o
:
out
std_logic
;
led_link_o
:
out
std_logic
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
-- 1PPS output
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
-- Link ok indication
link_ok_o
:
out
std_logic
);
end
entity
xwrc_board_spec
;
...
...
@@ -332,7 +349,7 @@ begin -- architecture struct
cmp_rstlogic_reset
:
gc_reset
generic
map
(
g_clocks
=>
2
,
-- 62.5MHz
g_clocks
=>
2
,
-- 62.5MHz
, 125MHz
g_logdelay
=>
4
,
-- 16 clock cycles
g_syncdepth
=>
3
)
-- length of sync chains
port
map
(
...
...
@@ -344,8 +361,8 @@ begin -- architecture struct
-- distribution of resets (already synchronized to their clock domains)
rst_62m5_n
<=
rstlogic_rst_out
(
0
);
rst_62m5_n_o
<=
rst_62m5_n
;
rst_125m_n_o
<=
rstlogic_rst_out
(
1
);
rst_
sys_
62m5_n_o
<=
rst_62m5_n
;
rst_
ref_
125m_n_o
<=
rstlogic_rst_out
(
1
);
-----------------------------------------------------------------------------
-- 2x SPI DAC
...
...
@@ -377,7 +394,7 @@ begin -- architecture struct
g_with_external_clock_input
=>
g_with_external_clock_input
,
g_phys_uart
=>
TRUE
,
g_virtual_uart
=>
TRUE
,
g_aux_clks
=>
0
,
g_aux_clks
=>
g_aux_clks
,
g_ep_rxbuf_size
=>
1024
,
g_tx_runt_padding
=>
TRUE
,
g_dpram_initf
=>
g_dpram_initf
,
...
...
@@ -400,7 +417,7 @@ begin -- architecture struct
clk_sys_i
=>
clk_pll_62m5
,
clk_dmtd_i
=>
clk_pll_dmtd
,
clk_ref_i
=>
clk_pll_125m
,
clk_aux_i
=>
(
others
=>
'0'
)
,
clk_aux_i
=>
clk_aux_i
,
clk_ext_i
=>
clk_10m_ext
,
clk_ext_mul_i
=>
ext_ref_mul
,
clk_ext_mul_locked_i
=>
ext_ref_mul_locked
,
...
...
@@ -414,8 +431,6 @@ begin -- architecture struct
dac_dpll_data_o
=>
dac_dpll_data
,
phy8_o
=>
phy8_from_wrc
,
phy8_i
=>
phy8_to_wrc
,
led_act_o
=>
led_act_o
,
led_link_o
=>
led_link_o
,
scl_o
=>
eeprom_scl_o
,
scl_i
=>
eeprom_scl_i
,
sda_o
=>
eeprom_sda_o
,
...
...
@@ -425,8 +440,6 @@ begin -- architecture struct
sfp_sda_o
=>
sfp_sda_o
,
sfp_sda_i
=>
sfp_sda_i
,
sfp_det_i
=>
sfp_det_i
,
btn1_i
=>
'1'
,
btn2_i
=>
'1'
,
spi_sclk_o
=>
flash_sclk_o
,
spi_ncs_o
=>
flash_ncs_o
,
spi_mosi_o
=>
flash_mosi_o
,
...
...
@@ -454,24 +467,28 @@ begin -- architecture struct
wrs_rx_dreq_i
=>
wrs_rx_dreq_i
,
wb_eth_master_o
=>
wb_eth_master_o
,
wb_eth_master_i
=>
wb_eth_master_i
,
timestamps_o
=>
open
,
timestamps_ack_i
=>
'1'
,
fc_tx_pause_req_i
=>
'0'
,
fc_tx_pause_delay_i
=>
(
others
=>
'0'
),
fc_tx_pause_ready_o
=>
open
,
tm_link_up_o
=>
open
,
tm_dac_value_o
=>
open
,
tm_dac_wr_o
=>
open
,
tm_clk_aux_lock_en_i
=>
(
others
=>
'0'
),
tm_clk_aux_locked_o
=>
open
,
aux_diag_i
=>
aux_diag_i
,
aux_diag_o
=>
aux_diag_o
,
tm_dac_value_o
=>
tm_dac_value_o
,
tm_dac_wr_o
=>
tm_dac_wr_o
,
tm_clk_aux_lock_en_i
=>
tm_clk_aux_lock_en_i
,
tm_clk_aux_locked_o
=>
tm_clk_aux_locked_o
,
timestamps_o
=>
timestamps_o
,
timestamps_ack_i
=>
timestamps_ack_i
,
fc_tx_pause_req_i
=>
fc_tx_pause_req_i
,
fc_tx_pause_delay_i
=>
fc_tx_pause_delay_i
,
fc_tx_pause_ready_o
=>
fc_tx_pause_ready_o
,
tm_link_up_o
=>
tm_link_up_o
,
tm_time_valid_o
=>
tm_time_valid_o
,
tm_tai_o
=>
tm_tai_o
,
tm_cycles_o
=>
tm_cycles_o
,
led_act_o
=>
led_act_o
,
led_link_o
=>
led_link_o
,
btn1_i
=>
btn1_i
,
btn2_i
=>
btn2_i
,
pps_p_o
=>
pps_p_o
,
pps_led_o
=>
pps_led_o
,
aux_diag_i
=>
aux_diag_i
,
aux_diag_o
=>
aux_diag_o
,
link_ok_o
=>
open
);
link_ok_o
=>
link_ok_o
);
sfp_rate_select_o
<=
'1'
;
...
...
board/svec/wr_svec_pkg.vhd
View file @
b3ad9a9c
...
...
@@ -5,6 +5,7 @@ library work;
use
work
.
wishbone_pkg
.
all
;
use
work
.
wrcore_pkg
.
all
;
use
work
.
wr_fabric_pkg
.
all
;
use
work
.
endpoint_pkg
.
all
;
use
work
.
wr_board_pkg
.
all
;
package
wr_svec_pkg
is
...
...
@@ -13,7 +14,8 @@ package wr_svec_pkg is
generic
(
g_simulation
:
integer
:
=
0
;
g_with_external_clock_input
:
boolean
:
=
TRUE
;
g_fabric_iface
:
t_board_fabric_iface
:
=
PLAIN
;
g_aux_clks
:
integer
:
=
0
;
g_fabric_iface
:
t_board_fabric_iface
:
=
plain
;
g_tx_streamer_width
:
integer
:
=
32
;
g_rx_streamer_width
:
integer
:
=
32
;
g_dpram_initf
:
string
:
=
"default_xilinx"
;
...
...
@@ -22,195 +24,229 @@ package wr_svec_pkg is
g_diag_ro_size
:
integer
:
=
0
;
g_diag_rw_size
:
integer
:
=
0
);
port
(
areset_n_i
:
in
std_logic
;
clk_20m_vcxo_i
:
in
std_logic
;
clk_125m_pllref_p_i
:
in
std_logic
;
clk_125m_pllref_n_i
:
in
std_logic
;
clk_125m_gtp_n_i
:
in
std_logic
;
clk_125m_gtp_p_i
:
in
std_logic
;
clk_10m_ext_ref_i
:
in
std_logic
:
=
'0'
;
clk_sys_62m5_o
:
out
std_logic
;
clk_ref_125m_o
:
out
std_logic
;
rst_sys_62m5_n_o
:
out
std_logic
;
pll20dac_din_o
:
out
std_logic
;
pll20dac_sclk_o
:
out
std_logic
;
pll20dac_sync_n_o
:
out
std_logic
;
pll25dac_din_o
:
out
std_logic
;
pll25dac_sclk_o
:
out
std_logic
;
pll25dac_sync_n_o
:
out
std_logic
;
sfp_txp_o
:
out
std_logic
;
sfp_txn_o
:
out
std_logic
;
sfp_rxp_i
:
in
std_logic
;
sfp_rxn_i
:
in
std_logic
;
sfp_det_i
:
in
std_logic
:
=
'1'
;
sfp_sda_i
:
in
std_logic
;
sfp_sda_o
:
out
std_logic
;
sfp_scl_i
:
in
std_logic
;
sfp_scl_o
:
out
std_logic
;
sfp_rate_select_o
:
out
std_logic
;
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_los_i
:
in
std_logic
:
=
'0'
;
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
eeprom_scl_o
:
out
std_logic
;
onewire_i
:
in
std_logic
;
onewire_oen_o
:
out
std_logic
;
uart_rxd_i
:
in
std_logic
;
uart_txd_o
:
out
std_logic
;
spi_sclk_o
:
out
std_logic
;
spi_ncs_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
;
wb_slave_o
:
out
t_wishbone_slave_out
;
wb_slave_i
:
in
t_wishbone_slave_in
:
=
cc_dummy_slave_in
;
wrf_src_o
:
out
t_wrf_source_out
;
wrf_src_i
:
in
t_wrf_source_in
:
=
c_dummy_src_in
;
wrf_snk_o
:
out
t_wrf_sink_out
;
wrf_snk_i
:
in
t_wrf_sink_in
:
=
c_dummy_snk_in
;
wrs_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wb_eth_master_o
:
out
t_wishbone_master_out
;
wb_eth_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
pps_ext_i
:
in
std_logic
:
=
'0'
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
led_link_o
:
out
std_logic
;
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
aux_diag_o
:
out
t_generic_word_array
(
g_diag_rw_size
-1
downto
0
);
led_act_o
:
out
std_logic
);
areset_n_i
:
in
std_logic
;
clk_20m_vcxo_i
:
in
std_logic
;
clk_125m_pllref_p_i
:
in
std_logic
;
clk_125m_pllref_n_i
:
in
std_logic
;
clk_125m_gtp_n_i
:
in
std_logic
;
clk_125m_gtp_p_i
:
in
std_logic
;
clk_aux_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
clk_10m_ext_ref_i
:
in
std_logic
:
=
'0'
;
pps_ext_i
:
in
std_logic
:
=
'0'
;
clk_sys_62m5_o
:
out
std_logic
;
clk_ref_125m_o
:
out
std_logic
;
rst_sys_62m5_n_o
:
out
std_logic
;
rst_ref_125m_n_o
:
out
std_logic
;
pll20dac_din_o
:
out
std_logic
;
pll20dac_sclk_o
:
out
std_logic
;
pll20dac_sync_n_o
:
out
std_logic
;
pll25dac_din_o
:
out
std_logic
;
pll25dac_sclk_o
:
out
std_logic
;
pll25dac_sync_n_o
:
out
std_logic
;
sfp_txp_o
:
out
std_logic
;
sfp_txn_o
:
out
std_logic
;
sfp_rxp_i
:
in
std_logic
;
sfp_rxn_i
:
in
std_logic
;
sfp_det_i
:
in
std_logic
:
=
'1'
;
sfp_sda_i
:
in
std_logic
;
sfp_sda_o
:
out
std_logic
;
sfp_scl_i
:
in
std_logic
;
sfp_scl_o
:
out
std_logic
;
sfp_rate_select_o
:
out
std_logic
;
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_los_i
:
in
std_logic
:
=
'0'
;
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
eeprom_scl_o
:
out
std_logic
;
onewire_i
:
in
std_logic
;
onewire_oen_o
:
out
std_logic
;
uart_rxd_i
:
in
std_logic
;
uart_txd_o
:
out
std_logic
;
spi_sclk_o
:
out
std_logic
;
spi_ncs_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
;
wb_slave_o
:
out
t_wishbone_slave_out
;
wb_slave_i
:
in
t_wishbone_slave_in
:
=
cc_dummy_slave_in
;
wrf_src_o
:
out
t_wrf_source_out
;
wrf_src_i
:
in
t_wrf_source_in
:
=
c_dummy_src_in
;
wrf_snk_o
:
out
t_wrf_sink_out
;
wrf_snk_i
:
in
t_wrf_sink_in
:
=
c_dummy_snk_in
;
wrs_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wb_eth_master_o
:
out
t_wishbone_master_out
;
wb_eth_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
aux_diag_o
:
out
t_generic_word_array
(
g_diag_rw_size
-1
downto
0
);
tm_dac_value_o
:
out
std_logic_vector
(
23
downto
0
);
tm_dac_wr_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tm_clk_aux_lock_en_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
tm_clk_aux_locked_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
timestamps_o
:
out
t_txtsu_timestamp
;
timestamps_ack_i
:
in
std_logic
:
=
'1'
;
fc_tx_pause_req_i
:
in
std_logic
:
=
'0'
;
fc_tx_pause_delay_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
fc_tx_pause_ready_o
:
out
std_logic
;
tm_link_up_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
led_act_o
:
out
std_logic
;
led_link_o
:
out
std_logic
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
link_ok_o
:
out
std_logic
);
end
component
xwrc_board_svec
;
component
wrc_board_svec
is
generic
(
g_simulation
:
integer
:
=
0
;
g_with_external_clock_input
:
integer
:
=
1
;
g_fabric_iface
:
string
:
=
"PLAINFBRC"
;
g_aux_clks
:
integer
:
=
0
;
g_fabric_iface
:
string
:
=
"plainfbrc"
;
g_tx_streamer_width
:
integer
:
=
32
;
g_rx_streamer_width
:
integer
:
=
32
;
g_dpram_initf
:
string
:
=
"default_xilinx"
;
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
g_diag_ro_vector_width
:
integer
:
=
0
;
g_diag_rw_vector_width
:
integer
:
=
0
);
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
g_diag_ro_vector_width
:
integer
:
=
0
;
g_diag_rw_vector_width
:
integer
:
=
0
);
port
(
areset_n_i
:
in
std_logic
;
clk_20m_vcxo_i
:
in
std_logic
;
clk_125m_pllref_p_i
:
in
std_logic
;
clk_125m_pllref_n_i
:
in
std_logic
;
clk_125m_gtp_n_i
:
in
std_logic
;
clk_125m_gtp_p_i
:
in
std_logic
;
clk_10m_ext_ref_i
:
in
std_logic
:
=
'0'
;
clk_sys_62m5_o
:
out
std_logic
;
clk_ref_125m_o
:
out
std_logic
;
rst_sys_62m5_n_o
:
out
std_logic
;
pll20dac_din_o
:
out
std_logic
;
pll20dac_sclk_o
:
out
std_logic
;
pll20dac_sync_n_o
:
out
std_logic
;
pll25dac_din_o
:
out
std_logic
;
pll25dac_sclk_o
:
out
std_logic
;
pll25dac_sync_n_o
:
out
std_logic
;
sfp_txp_o
:
out
std_logic
;
sfp_txn_o
:
out
std_logic
;
sfp_rxp_i
:
in
std_logic
;
sfp_rxn_i
:
in
std_logic
;
sfp_det_i
:
in
std_logic
:
=
'1'
;
sfp_sda_i
:
in
std_logic
;
sfp_sda_o
:
out
std_logic
;
sfp_scl_i
:
in
std_logic
;
sfp_scl_o
:
out
std_logic
;
sfp_rate_select_o
:
out
std_logic
;
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_los_i
:
in
std_logic
:
=
'0'
;
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
eeprom_scl_o
:
out
std_logic
;
onewire_i
:
in
std_logic
;
onewire_oen_o
:
out
std_logic
;
uart_rxd_i
:
in
std_logic
;
uart_txd_o
:
out
std_logic
;
spi_sclk_o
:
out
std_logic
;
spi_ncs_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_sel_i
:
in
std_logic_vector
(
c_wishbone_address_width
/
8-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_we_i
:
in
std_logic
:
=
'0'
;
wb_cyc_i
:
in
std_logic
:
=
'0'
;
wb_stb_i
:
in
std_logic
:
=
'0'
;
wb_ack_o
:
out
std_logic
;
wb_int_o
:
out
std_logic
;
wb_err_o
:
out
std_logic
;
wb_rty_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
wrf_src_adr_o
:
out
std_logic_vector
(
1
downto
0
);
wrf_src_dat_o
:
out
std_logic_vector
(
15
downto
0
);
wrf_src_cyc_o
:
out
std_logic
;
wrf_src_stb_o
:
out
std_logic
;
wrf_src_we_o
:
out
std_logic
;
wrf_src_sel_o
:
out
std_logic_vector
(
1
downto
0
);
wrf_src_ack_i
:
in
std_logic
;
wrf_src_stall_i
:
in
std_logic
;
wrf_src_err_i
:
in
std_logic
;
wrf_src_rty_i
:
in
std_logic
;
wrf_snk_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wrf_snk_dat_i
:
in
std_logic_vector
(
15
downto
0
);
wrf_snk_cyc_i
:
in
std_logic
;
wrf_snk_stb_i
:
in
std_logic
;
wrf_snk_we_i
:
in
std_logic
;
wrf_snk_sel_i
:
in
std_logic_vector
(
1
downto
0
);
wrf_snk_ack_o
:
out
std_logic
;
wrf_snk_stall_o
:
out
std_logic
;
wrf_snk_err_o
:
out
std_logic
;
wrf_snk_rty_o
:
out
std_logic
;
wrs_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wb_eth_adr_o
:
out
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
);
wb_eth_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_eth_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_eth_sel_o
:
out
std_logic_vector
(
c_wishbone_address_width
/
8-1
downto
0
);
wb_eth_we_o
:
out
std_logic
;
wb_eth_cyc_o
:
out
std_logic
;
wb_eth_stb_o
:
out
std_logic
;
wb_eth_ack_i
:
in
std_logic
:
=
'0'
;
wb_eth_int_i
:
in
std_logic
:
=
'0'
;
wb_eth_err_i
:
in
std_logic
:
=
'0'
;
wb_eth_rty_i
:
in
std_logic
:
=
'0'
;
wb_eth_stall_i
:
in
std_logic
:
=
'0'
;
pps_ext_i
:
in
std_logic
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
led_link_o
:
out
std_logic
;
aux_diag_i
:
in
std_logic_vector
(
g_diag_ro_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
aux_diag_o
:
out
std_logic_vector
(
g_diag_rw_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
led_act_o
:
out
std_logic
);
areset_n_i
:
in
std_logic
;
clk_20m_vcxo_i
:
in
std_logic
;
clk_125m_pllref_p_i
:
in
std_logic
;
clk_125m_pllref_n_i
:
in
std_logic
;
clk_125m_gtp_n_i
:
in
std_logic
;
clk_125m_gtp_p_i
:
in
std_logic
;
clk_10m_ext_ref_i
:
in
std_logic
:
=
'0'
;
pps_ext_i
:
in
std_logic
:
=
'0'
;
clk_sys_62m5_o
:
out
std_logic
;
clk_ref_125m_o
:
out
std_logic
;
rst_sys_62m5_n_o
:
out
std_logic
;
rst_ref_125m_n_o
:
out
std_logic
;
pll20dac_din_o
:
out
std_logic
;
pll20dac_sclk_o
:
out
std_logic
;
pll20dac_sync_n_o
:
out
std_logic
;
pll25dac_din_o
:
out
std_logic
;
pll25dac_sclk_o
:
out
std_logic
;
pll25dac_sync_n_o
:
out
std_logic
;
sfp_txp_o
:
out
std_logic
;
sfp_txn_o
:
out
std_logic
;
sfp_rxp_i
:
in
std_logic
;
sfp_rxn_i
:
in
std_logic
;
sfp_det_i
:
in
std_logic
:
=
'1'
;
sfp_sda_i
:
in
std_logic
;
sfp_sda_o
:
out
std_logic
;
sfp_scl_i
:
in
std_logic
;
sfp_scl_o
:
out
std_logic
;
sfp_rate_select_o
:
out
std_logic
;
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_los_i
:
in
std_logic
:
=
'0'
;
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
eeprom_scl_o
:
out
std_logic
;
onewire_i
:
in
std_logic
;
onewire_oen_o
:
out
std_logic
;
uart_rxd_i
:
in
std_logic
;
uart_txd_o
:
out
std_logic
;
spi_sclk_o
:
out
std_logic
;
spi_ncs_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_sel_i
:
in
std_logic_vector
(
c_wishbone_address_width
/
8-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_we_i
:
in
std_logic
:
=
'0'
;
wb_cyc_i
:
in
std_logic
:
=
'0'
;
wb_stb_i
:
in
std_logic
:
=
'0'
;
wb_ack_o
:
out
std_logic
;
wb_int_o
:
out
std_logic
;
wb_err_o
:
out
std_logic
;
wb_rty_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
wrf_src_adr_o
:
out
std_logic_vector
(
1
downto
0
);
wrf_src_dat_o
:
out
std_logic_vector
(
15
downto
0
);
wrf_src_cyc_o
:
out
std_logic
;
wrf_src_stb_o
:
out
std_logic
;
wrf_src_we_o
:
out
std_logic
;
wrf_src_sel_o
:
out
std_logic_vector
(
1
downto
0
);
wrf_src_ack_i
:
in
std_logic
;
wrf_src_stall_i
:
in
std_logic
;
wrf_src_err_i
:
in
std_logic
;
wrf_src_rty_i
:
in
std_logic
;
wrf_snk_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wrf_snk_dat_i
:
in
std_logic_vector
(
15
downto
0
);
wrf_snk_cyc_i
:
in
std_logic
;
wrf_snk_stb_i
:
in
std_logic
;
wrf_snk_we_i
:
in
std_logic
;
wrf_snk_sel_i
:
in
std_logic_vector
(
1
downto
0
);
wrf_snk_ack_o
:
out
std_logic
;
wrf_snk_stall_o
:
out
std_logic
;
wrf_snk_err_o
:
out
std_logic
;
wrf_snk_rty_o
:
out
std_logic
;
wrs_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wb_eth_adr_o
:
out
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
);
wb_eth_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_eth_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_eth_sel_o
:
out
std_logic_vector
(
c_wishbone_address_width
/
8-1
downto
0
);
wb_eth_we_o
:
out
std_logic
;
wb_eth_cyc_o
:
out
std_logic
;
wb_eth_stb_o
:
out
std_logic
;
wb_eth_ack_i
:
in
std_logic
:
=
'0'
;
wb_eth_int_i
:
in
std_logic
:
=
'0'
;
wb_eth_err_i
:
in
std_logic
:
=
'0'
;
wb_eth_rty_i
:
in
std_logic
:
=
'0'
;
wb_eth_stall_i
:
in
std_logic
:
=
'0'
;
aux_diag_i
:
in
std_logic_vector
(
g_diag_ro_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
aux_diag_o
:
out
std_logic_vector
(
g_diag_rw_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
tm_dac_value_o
:
out
std_logic_vector
(
23
downto
0
);
tm_dac_wr_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tm_clk_aux_lock_en_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
tm_clk_aux_locked_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tstamps_stb_o
:
out
std_logic
;
tstamps_tsval_o
:
out
std_logic_vector
(
31
downto
0
);
tstamps_port_id_o
:
out
std_logic_vector
(
5
downto
0
);
tstamps_frame_id_o
:
out
std_logic_vector
(
15
downto
0
);
tstamps_incorrect_o
:
out
std_logic
;
tstamps_ack_i
:
in
std_logic
:
=
'1'
;
fc_tx_pause_req_i
:
in
std_logic
:
=
'0'
;
fc_tx_pause_delay_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
fc_tx_pause_ready_o
:
out
std_logic
;
tm_link_up_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
led_act_o
:
out
std_logic
;
led_link_o
:
out
std_logic
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
link_ok_o
:
out
std_logic
);
end
component
wrc_board_svec
;
end
wr_svec_pkg
;
board/svec/wrc_board_svec.vhd
View file @
b3ad9a9c
...
...
@@ -6,8 +6,8 @@
-- File : wrc_board_svec.vhd
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 201
6
-02-16
-- Last update: 2017-0
2-22
-- Created : 201
7
-02-16
-- Last update: 2017-0
3-08
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
...
...
@@ -16,7 +16,7 @@
-- instantiation).
-- http://www.ohwr.org/projects/svec/
-------------------------------------------------------------------------------
-- Copyright (c) 201
6-201
7 CERN
-- Copyright (c) 2017 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
...
...
@@ -59,6 +59,8 @@ entity wrc_board_svec is
g_simulation
:
integer
:
=
0
;
-- Select whether to include external ref clock input
g_with_external_clock_input
:
integer
:
=
1
;
-- Number of aux clocks syntonized by WRPC to WR timebase
g_aux_clks
:
integer
:
=
0
;
-- "plainfbrc" = expose WRC fabric interface
-- "streamers" = attach WRC streamers to fabric interface
-- "etherbone" = attach Etherbone slave to fabric interface
...
...
@@ -69,43 +71,36 @@ entity wrc_board_svec is
-- memory initialisation file for embedded CPU
g_dpram_initf
:
string
:
=
"default_xilinx"
;
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
-- size the generic diag interface
g_diag_ro_vector_width
:
integer
:
=
0
;
g_diag_rw_vector_width
:
integer
:
=
0
g_diag_ro_vector_width
:
integer
:
=
0
;
g_diag_rw_vector_width
:
integer
:
=
0
);
port
(
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Reset from system fpga
areset_n_i
:
in
std_logic
;
areset_n_i
:
in
std_logic
;
-- Clock inputs from the board
clk_20m_vcxo_i
:
in
std_logic
;
clk_125m_pllref_p_i
:
in
std_logic
;
clk_125m_pllref_n_i
:
in
std_logic
;
clk_125m_gtp_n_i
:
in
std_logic
;
clk_125m_gtp_p_i
:
in
std_logic
;
clk_20m_vcxo_i
:
in
std_logic
;
clk_125m_pllref_p_i
:
in
std_logic
;
clk_125m_pllref_n_i
:
in
std_logic
;
clk_125m_gtp_n_i
:
in
std_logic
;
clk_125m_gtp_p_i
:
in
std_logic
;
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_10m_ext_ref_i
:
in
std_logic
:
=
'0'
;
clk_10m_ext_ref_i
:
in
std_logic
:
=
'0'
;
-- External PPS input (g_with_external_clock_input = TRUE)
pps_ext_i
:
in
std_logic
:
=
'0'
;
-- 62.5MHz sys clock output
clk_sys_62m5_o
:
out
std_logic
;
clk_sys_62m5_o
:
out
std_logic
;
-- 125MHz ref clock output
clk_ref_125m_o
:
out
std_logic
;
clk_ref_125m_o
:
out
std_logic
;
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o
:
out
std_logic
;
rst_ref_125m_n_o
:
out
std_logic
;
-- active low reset output, synchronous to clk_sys_62m5_o
rst_sys_62m5_n_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- SPI interfaces to DACs
---------------------------------------------------------------------------
pll20dac_din_o
:
out
std_logic
;
...
...
@@ -118,7 +113,6 @@ entity wrc_board_svec is
---------------------------------------------------------------------------
-- SFP I/O for transceiver and SFP management info
---------------------------------------------------------------------------
sfp_txp_o
:
out
std_logic
;
sfp_txn_o
:
out
std_logic
;
sfp_rxp_i
:
in
std_logic
;
...
...
@@ -136,7 +130,6 @@ entity wrc_board_svec is
---------------------------------------------------------------------------
-- I2C EEPROM
---------------------------------------------------------------------------
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
...
...
@@ -145,14 +138,12 @@ entity wrc_board_svec is
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_i
:
in
std_logic
;
onewire_oen_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i
:
in
std_logic
;
uart_txd_o
:
out
std_logic
;
...
...
@@ -160,7 +151,6 @@ entity wrc_board_svec is
-- SPI (flash is connected to SFPGA and routed to AFPGA
-- once the boot process is complete)
---------------------------------------------------------------------------
spi_sclk_o
:
out
std_logic
;
spi_ncs_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
...
...
@@ -169,7 +159,6 @@ entity wrc_board_svec is
---------------------------------------------------------------------------
-- External WB interface
---------------------------------------------------------------------------
wb_adr_i
:
in
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
...
...
@@ -186,7 +175,6 @@ entity wrc_board_svec is
---------------------------------------------------------------------------
-- WR fabric interface (when g_fabric_iface = "plain")
---------------------------------------------------------------------------
wrf_src_adr_o
:
out
std_logic_vector
(
1
downto
0
);
wrf_src_dat_o
:
out
std_logic_vector
(
15
downto
0
);
wrf_src_cyc_o
:
out
std_logic
;
...
...
@@ -211,22 +199,20 @@ entity wrc_board_svec is
---------------------------------------------------------------------------
-- WR streamers (when g_fabric_iface = "streamers")
---------------------------------------------------------------------------
wrs_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
---------------------------------------------------------------------------
-- Etherbone WB master interface (when g_fabric_iface = "etherbone")
---------------------------------------------------------------------------
wb_eth_adr_o
:
out
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
);
wb_eth_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_eth_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
...
...
@@ -241,19 +227,57 @@ entity wrc_board_svec is
wb_eth_stall_i
:
in
std_logic
:
=
'0'
;
---------------------------------------------------------------------------
--
WRPC timing interface and status
--
Generic diagnostics interface (access from WRPC via SNMP or uart console
---------------------------------------------------------------------------
aux_diag_i
:
in
std_logic_vector
(
g_diag_ro_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
aux_diag_o
:
out
std_logic_vector
(
g_diag_rw_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
pps_ext_i
:
in
std_logic
:
=
'0'
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- Aux clocks control
---------------------------------------------------------------------------
tm_dac_value_o
:
out
std_logic_vector
(
23
downto
0
);
tm_dac_wr_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tm_clk_aux_lock_en_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
tm_clk_aux_locked_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
---------------------------------------------------------------------------
-- External Tx Timestamping I/F
---------------------------------------------------------------------------
tstamps_stb_o
:
out
std_logic
;
tstamps_tsval_o
:
out
std_logic_vector
(
31
downto
0
);
tstamps_port_id_o
:
out
std_logic_vector
(
5
downto
0
);
tstamps_frame_id_o
:
out
std_logic_vector
(
15
downto
0
);
tstamps_incorrect_o
:
out
std_logic
;
tstamps_ack_i
:
in
std_logic
:
=
'1'
;
---------------------------------------------------------------------------
-- Pause Frame Control
---------------------------------------------------------------------------
fc_tx_pause_req_i
:
in
std_logic
:
=
'0'
;
fc_tx_pause_delay_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
fc_tx_pause_ready_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- Timecode I/F
---------------------------------------------------------------------------
tm_link_up_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
led_link_o
:
out
std_logic
;
aux_diag_i
:
in
std_logic_vector
(
g_diag_ro_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
aux_diag_o
:
out
std_logic_vector
(
g_diag_rw_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
led_act_o
:
out
std_logic
);
---------------------------------------------------------------------------
-- Buttons, LEDs and PPS output
---------------------------------------------------------------------------
led_act_o
:
out
std_logic
;
led_link_o
:
out
std_logic
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
-- 1PPS output
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
-- Link ok indication
link_ok_o
:
out
std_logic
);
end
entity
wrc_board_svec
;
...
...
@@ -279,12 +303,15 @@ architecture std_wrapper of wrc_board_svec is
signal
wb_eth_master_in
:
t_wishbone_master_in
;
-- Aux diagnostics
constant
c_diag_ro_size
:
integer
:
=
g_diag_ro_vector_width
/
32
;
constant
c_diag_rw_size
:
integer
:
=
g_diag_rw_vector_width
/
32
;
constant
c_diag_ro_size
:
integer
:
=
g_diag_ro_vector_width
/
32
;
constant
c_diag_rw_size
:
integer
:
=
g_diag_rw_vector_width
/
32
;
signal
aux_diag_in
:
t_generic_word_array
(
c_diag_ro_size
-1
downto
0
);
signal
aux_diag_out
:
t_generic_word_array
(
c_diag_rw_size
-1
downto
0
);
-- External Tx Timestamping I/F
signal
timestamps_out
:
t_txtsu_timestamp
;
begin
-- architecture struct
-- Map top-level signals to internal records
...
...
@@ -339,15 +366,20 @@ begin -- architecture struct
wb_eth_master_in
.
rty
<=
wb_eth_rty_i
;
wb_eth_master_in
.
stall
<=
wb_eth_stall_i
;
-- auxiliary diagnostics
aux_diag_in
<=
f_de_vectorize_diag
(
aux_diag_i
,
g_diag_ro_vector_width
);
aux_diag_in
<=
f_de_vectorize_diag
(
aux_diag_i
,
g_diag_ro_vector_width
);
aux_diag_o
<=
f_vectorize_diag
(
aux_diag_out
,
g_diag_rw_vector_width
);
tstamps_stb_o
<=
timestamps_out
.
stb
;
tstamps_tsval_o
<=
timestamps_out
.
tsval
;
tstamps_port_id_o
<=
timestamps_out
.
port_id
;
tstamps_frame_id_o
<=
timestamps_out
.
frame_id
;
-- Instantiate the records-based module
cmp_xwrc_board_svec
:
xwrc_board_svec
generic
map
(
g_simulation
=>
g_simulation
,
g_with_external_clock_input
=>
f_int2bool
(
g_with_external_clock_input
),
g_aux_clks
=>
g_aux_clks
,
g_fabric_iface
=>
f_str2iface_type
(
g_fabric_iface
),
g_tx_streamer_width
=>
g_tx_streamer_width
,
g_rx_streamer_width
=>
g_rx_streamer_width
,
...
...
@@ -357,74 +389,88 @@ begin -- architecture struct
g_diag_ro_size
=>
c_diag_ro_size
,
g_diag_rw_size
=>
c_diag_rw_size
)
port
map
(
areset_n_i
=>
areset_n_i
,
clk_20m_vcxo_i
=>
clk_20m_vcxo_i
,
clk_125m_pllref_p_i
=>
clk_125m_pllref_p_i
,
clk_125m_pllref_n_i
=>
clk_125m_pllref_n_i
,
clk_125m_gtp_n_i
=>
clk_125m_gtp_n_i
,
clk_125m_gtp_p_i
=>
clk_125m_gtp_p_i
,
clk_10m_ext_ref_i
=>
clk_10m_ext_ref_i
,
clk_sys_62m5_o
=>
clk_sys_62m5_o
,
clk_ref_125m_o
=>
clk_ref_125m_o
,
rst_sys_62m5_n_o
=>
rst_sys_62m5_n_o
,
pll20dac_din_o
=>
pll20dac_din_o
,
pll20dac_sclk_o
=>
pll20dac_sclk_o
,
pll20dac_sync_n_o
=>
pll20dac_sync_n_o
,
pll25dac_din_o
=>
pll25dac_din_o
,
pll25dac_sclk_o
=>
pll25dac_sclk_o
,
pll25dac_sync_n_o
=>
pll25dac_sync_n_o
,
sfp_txp_o
=>
sfp_txp_o
,
sfp_txn_o
=>
sfp_txn_o
,
sfp_rxp_i
=>
sfp_rxp_i
,
sfp_rxn_i
=>
sfp_rxn_i
,
sfp_det_i
=>
sfp_det_i
,
sfp_sda_i
=>
sfp_sda_i
,
sfp_sda_o
=>
sfp_sda_o
,
sfp_scl_i
=>
sfp_scl_i
,
sfp_scl_o
=>
sfp_scl_o
,
sfp_rate_select_o
=>
sfp_rate_select_o
,
sfp_tx_fault_i
=>
sfp_tx_fault_i
,
sfp_tx_disable_o
=>
sfp_tx_disable_o
,
sfp_los_i
=>
sfp_los_i
,
eeprom_sda_i
=>
eeprom_sda_i
,
eeprom_sda_o
=>
eeprom_sda_o
,
eeprom_scl_i
=>
eeprom_scl_i
,
eeprom_scl_o
=>
eeprom_scl_o
,
onewire_i
=>
onewire_i
,
onewire_oen_o
=>
onewire_oen_o
,
uart_rxd_i
=>
uart_rxd_i
,
uart_txd_o
=>
uart_txd_o
,
spi_sclk_o
=>
spi_sclk_o
,
spi_ncs_o
=>
spi_ncs_o
,
spi_mosi_o
=>
spi_mosi_o
,
spi_miso_i
=>
spi_miso_i
,
wb_slave_o
=>
wb_slave_out
,
wb_slave_i
=>
wb_slave_in
,
wrf_src_o
=>
wrf_src_out
,
wrf_src_i
=>
wrf_src_in
,
wrf_snk_o
=>
wrf_snk_out
,
wrf_snk_i
=>
wrf_snk_in
,
wrs_tx_data_i
=>
wrs_tx_data_i
,
wrs_tx_valid_i
=>
wrs_tx_valid_i
,
wrs_tx_dreq_o
=>
wrs_tx_dreq_o
,
wrs_tx_last_i
=>
wrs_tx_last_i
,
wrs_tx_flush_i
=>
wrs_tx_flush_i
,
wrs_rx_first_o
=>
wrs_rx_first_o
,
wrs_rx_last_o
=>
wrs_rx_last_o
,
wrs_rx_data_o
=>
wrs_rx_data_o
,
wrs_rx_valid_o
=>
wrs_rx_valid_o
,
wrs_rx_dreq_i
=>
wrs_rx_dreq_i
,
wb_eth_master_o
=>
wb_eth_master_out
,
wb_eth_master_i
=>
wb_eth_master_in
,
pps_ext_i
=>
pps_ext_i
,
pps_p_o
=>
pps_p_o
,
pps_led_o
=>
pps_led_o
,
tm_time_valid_o
=>
tm_time_valid_o
,
tm_tai_o
=>
tm_tai_o
,
tm_cycles_o
=>
tm_cycles_o
,
led_link_o
=>
led_link_o
,
aux_diag_i
=>
aux_diag_in
,
aux_diag_o
=>
aux_diag_out
,
led_act_o
=>
led_act_o
);
areset_n_i
=>
areset_n_i
,
clk_20m_vcxo_i
=>
clk_20m_vcxo_i
,
clk_125m_pllref_p_i
=>
clk_125m_pllref_p_i
,
clk_125m_pllref_n_i
=>
clk_125m_pllref_n_i
,
clk_125m_gtp_n_i
=>
clk_125m_gtp_n_i
,
clk_125m_gtp_p_i
=>
clk_125m_gtp_p_i
,
clk_10m_ext_ref_i
=>
clk_10m_ext_ref_i
,
pps_ext_i
=>
pps_ext_i
,
clk_sys_62m5_o
=>
clk_sys_62m5_o
,
clk_ref_125m_o
=>
clk_ref_125m_o
,
rst_sys_62m5_n_o
=>
rst_sys_62m5_n_o
,
rst_ref_125m_n_o
=>
rst_ref_125m_n_o
,
pll20dac_din_o
=>
pll20dac_din_o
,
pll20dac_sclk_o
=>
pll20dac_sclk_o
,
pll20dac_sync_n_o
=>
pll20dac_sync_n_o
,
pll25dac_din_o
=>
pll25dac_din_o
,
pll25dac_sclk_o
=>
pll25dac_sclk_o
,
pll25dac_sync_n_o
=>
pll25dac_sync_n_o
,
sfp_txp_o
=>
sfp_txp_o
,
sfp_txn_o
=>
sfp_txn_o
,
sfp_rxp_i
=>
sfp_rxp_i
,
sfp_rxn_i
=>
sfp_rxn_i
,
sfp_det_i
=>
sfp_det_i
,
sfp_sda_i
=>
sfp_sda_i
,
sfp_sda_o
=>
sfp_sda_o
,
sfp_scl_i
=>
sfp_scl_i
,
sfp_scl_o
=>
sfp_scl_o
,
sfp_rate_select_o
=>
sfp_rate_select_o
,
sfp_tx_fault_i
=>
sfp_tx_fault_i
,
sfp_tx_disable_o
=>
sfp_tx_disable_o
,
sfp_los_i
=>
sfp_los_i
,
eeprom_sda_i
=>
eeprom_sda_i
,
eeprom_sda_o
=>
eeprom_sda_o
,
eeprom_scl_i
=>
eeprom_scl_i
,
eeprom_scl_o
=>
eeprom_scl_o
,
onewire_i
=>
onewire_i
,
onewire_oen_o
=>
onewire_oen_o
,
uart_rxd_i
=>
uart_rxd_i
,
uart_txd_o
=>
uart_txd_o
,
spi_sclk_o
=>
spi_sclk_o
,
spi_ncs_o
=>
spi_ncs_o
,
spi_mosi_o
=>
spi_mosi_o
,
spi_miso_i
=>
spi_miso_i
,
wb_slave_o
=>
wb_slave_out
,
wb_slave_i
=>
wb_slave_in
,
wrf_src_o
=>
wrf_src_out
,
wrf_src_i
=>
wrf_src_in
,
wrf_snk_o
=>
wrf_snk_out
,
wrf_snk_i
=>
wrf_snk_in
,
wrs_tx_data_i
=>
wrs_tx_data_i
,
wrs_tx_valid_i
=>
wrs_tx_valid_i
,
wrs_tx_dreq_o
=>
wrs_tx_dreq_o
,
wrs_tx_last_i
=>
wrs_tx_last_i
,
wrs_tx_flush_i
=>
wrs_tx_flush_i
,
wrs_rx_first_o
=>
wrs_rx_first_o
,
wrs_rx_last_o
=>
wrs_rx_last_o
,
wrs_rx_data_o
=>
wrs_rx_data_o
,
wrs_rx_valid_o
=>
wrs_rx_valid_o
,
wrs_rx_dreq_i
=>
wrs_rx_dreq_i
,
wb_eth_master_o
=>
wb_eth_master_out
,
wb_eth_master_i
=>
wb_eth_master_in
,
aux_diag_i
=>
aux_diag_in
,
aux_diag_o
=>
aux_diag_out
,
tm_dac_value_o
=>
tm_dac_value_o
,
tm_dac_wr_o
=>
tm_dac_wr_o
,
tm_clk_aux_lock_en_i
=>
tm_clk_aux_lock_en_i
,
tm_clk_aux_locked_o
=>
tm_clk_aux_locked_o
,
timestamps_o
=>
timestamps_out
,
timestamps_ack_i
=>
tstamps_ack_i
,
fc_tx_pause_req_i
=>
fc_tx_pause_req_i
,
fc_tx_pause_delay_i
=>
fc_tx_pause_delay_i
,
fc_tx_pause_ready_o
=>
fc_tx_pause_ready_o
,
tm_link_up_o
=>
tm_link_up_o
,
tm_time_valid_o
=>
tm_time_valid_o
,
tm_tai_o
=>
tm_tai_o
,
tm_cycles_o
=>
tm_cycles_o
,
led_act_o
=>
led_act_o
,
led_link_o
=>
led_link_o
,
btn1_i
=>
btn1_i
,
btn2_i
=>
btn2_i
,
pps_p_o
=>
pps_p_o
,
pps_led_o
=>
pps_led_o
,
link_ok_o
=>
link_ok_o
);
end
architecture
std_wrapper
;
board/svec/xwrc_board_svec.vhd
View file @
b3ad9a9c
...
...
@@ -7,14 +7,14 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2017-03-0
7
-- Last update: 2017-03-0
8
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
-- needed to operate the core on the SVEC board.
-- http://www.ohwr.org/projects/svec/
-------------------------------------------------------------------------------
-- Copyright (c) 201
6-201
7 CERN
-- Copyright (c) 2017 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
...
...
@@ -60,55 +60,53 @@ entity xwrc_board_svec is
g_simulation
:
integer
:
=
0
;
-- Select whether to include external ref clock input
g_with_external_clock_input
:
boolean
:
=
TRUE
;
-- Number of aux clocks syntonized by WRPC to WR timebase
g_aux_clks
:
integer
:
=
0
;
-- plain = expose WRC fabric interface
-- streamers = attach WRC streamers to fabric interface
-- etherbone = attach Etherbone slave to fabric interface
g_fabric_iface
:
t_board_fabric_iface
:
=
plain
;
-- data width when g_fabric_iface = "streamers" (otherwise ignored)
g_tx_streamer_width
:
integer
:
=
32
;
g_rx_streamer_width
:
integer
:
=
32
;
g_tx_streamer_width
:
integer
:
=
32
;
g_rx_streamer_width
:
integer
:
=
32
;
-- memory initialisation file for embedded CPU
g_dpram_initf
:
string
:
=
"default_xilinx"
;
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
-- size the generic diag interface
g_diag_ro_size
:
integer
:
=
0
;
g_diag_rw_size
:
integer
:
=
0
g_diag_ro_size
:
integer
:
=
0
;
g_diag_rw_size
:
integer
:
=
0
);
port
(
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Reset from system fpga
areset_n_i
:
in
std_logic
;
-- Reset input (active low, can be async)
areset_n_i
:
in
std_logic
;
-- Clock inputs from the board
clk_20m_vcxo_i
:
in
std_logic
;
clk_125m_pllref_p_i
:
in
std_logic
;
clk_125m_pllref_n_i
:
in
std_logic
;
clk_125m_gtp_n_i
:
in
std_logic
;
clk_125m_gtp_p_i
:
in
std_logic
;
clk_20m_vcxo_i
:
in
std_logic
;
clk_125m_pllref_p_i
:
in
std_logic
;
clk_125m_pllref_n_i
:
in
std_logic
;
clk_125m_gtp_n_i
:
in
std_logic
;
clk_125m_gtp_p_i
:
in
std_logic
;
-- Aux clocks, which can be disciplined by the WR Core
clk_aux_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_10m_ext_ref_i
:
in
std_logic
:
=
'0'
;
clk_10m_ext_ref_i
:
in
std_logic
:
=
'0'
;
-- External PPS input (g_with_external_clock_input = TRUE)
pps_ext_i
:
in
std_logic
:
=
'0'
;
-- 62.5MHz sys clock output
clk_sys_62m5_o
:
out
std_logic
;
clk_sys_62m5_o
:
out
std_logic
;
-- 125MHz ref clock output
clk_ref_125m_o
:
out
std_logic
;
-- active low reset output, synchronous to clk_sys_62m5_o
rst_
sys_62m5_n_o
:
out
std_logic
;
clk_ref_125m_o
:
out
std_logic
;
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o
:
out
std_logic
;
rst_
ref_125m_n_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- SPI interfaces to DACs
---------------------------------------------------------------------------
pll20dac_din_o
:
out
std_logic
;
pll20dac_sclk_o
:
out
std_logic
;
pll20dac_sync_n_o
:
out
std_logic
;
...
...
@@ -119,7 +117,6 @@ entity xwrc_board_svec is
---------------------------------------------------------------------------
-- SFP I/O for transceiver and SFP management info
---------------------------------------------------------------------------
sfp_txp_o
:
out
std_logic
;
sfp_txn_o
:
out
std_logic
;
sfp_rxp_i
:
in
std_logic
;
...
...
@@ -137,7 +134,6 @@ entity xwrc_board_svec is
---------------------------------------------------------------------------
-- I2C EEPROM
---------------------------------------------------------------------------
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
...
...
@@ -146,14 +142,12 @@ entity xwrc_board_svec is
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_i
:
in
std_logic
;
onewire_oen_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i
:
in
std_logic
;
uart_txd_o
:
out
std_logic
;
...
...
@@ -161,7 +155,6 @@ entity xwrc_board_svec is
-- SPI (flash is connected to SFPGA and routed to AFPGA
-- once the boot process is complete)
---------------------------------------------------------------------------
spi_sclk_o
:
out
std_logic
;
spi_ncs_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
...
...
@@ -170,14 +163,12 @@ entity xwrc_board_svec is
---------------------------------------------------------------------------
-- External WB interface
---------------------------------------------------------------------------
wb_slave_o
:
out
t_wishbone_slave_out
;
wb_slave_i
:
in
t_wishbone_slave_in
:
=
cc_dummy_slave_in
;
---------------------------------------------------------------------------
-- WR fabric interface (when g_fabric_iface = "plainfbrc")
---------------------------------------------------------------------------
wrf_src_o
:
out
t_wrf_source_out
;
wrf_src_i
:
in
t_wrf_source_in
:
=
c_dummy_src_in
;
wrf_snk_o
:
out
t_wrf_sink_out
;
...
...
@@ -186,44 +177,71 @@ entity xwrc_board_svec is
---------------------------------------------------------------------------
-- WR streamers (when g_fabric_iface = "streamers")
---------------------------------------------------------------------------
wrs_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
---------------------------------------------------------------------------
-- Etherbone WB master interface (when g_fabric_iface = "etherbone")
---------------------------------------------------------------------------
wb_eth_master_o
:
out
t_wishbone_master_out
;
wb_eth_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
---------------------------------------------------------------------------
-- Generic diagnostics interface (access from WRPC via SNMP or uart console
---------------------------------------------------------------------------
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
aux_diag_o
:
out
t_generic_word_array
(
g_diag_rw_size
-1
downto
0
);
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
aux_diag_o
:
out
t_generic_word_array
(
g_diag_rw_size
-1
downto
0
);
---------------------------------------------------------------------------
-- Aux clocks control
---------------------------------------------------------------------------
tm_dac_value_o
:
out
std_logic_vector
(
23
downto
0
);
tm_dac_wr_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tm_clk_aux_lock_en_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
tm_clk_aux_locked_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
---------------------------------------------------------------------------
--
WRPC timing interface and status
--
External Tx Timestamping I/F
---------------------------------------------------------------------------
timestamps_o
:
out
t_txtsu_timestamp
;
timestamps_ack_i
:
in
std_logic
:
=
'1'
;
pps_ext_i
:
in
std_logic
:
=
'0'
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- Pause Frame Control
---------------------------------------------------------------------------
fc_tx_pause_req_i
:
in
std_logic
:
=
'0'
;
fc_tx_pause_delay_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
fc_tx_pause_ready_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- Timecode I/F
---------------------------------------------------------------------------
tm_link_up_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
led_link_o
:
out
std_logic
;
led_act_o
:
out
std_logic
);
---------------------------------------------------------------------------
-- Buttons, LEDs and PPS output
---------------------------------------------------------------------------
led_act_o
:
out
std_logic
;
led_link_o
:
out
std_logic
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
-- 1PPS output
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
-- Link ok indication
link_ok_o
:
out
std_logic
);
end
entity
xwrc_board_svec
;
...
...
@@ -247,8 +265,8 @@ architecture struct of xwrc_board_svec is
-- Reset logic
signal
rst_62m5_n
:
std_logic
;
signal
rstlogic_arst_n
:
std_logic
;
signal
rstlogic_clk_in
:
std_logic_vector
(
0
downto
0
);
signal
rstlogic_rst_out
:
std_logic_vector
(
0
downto
0
);
signal
rstlogic_clk_in
:
std_logic_vector
(
1
downto
0
);
signal
rstlogic_rst_out
:
std_logic_vector
(
1
downto
0
);
-- PLL DAC ARB
signal
dac_sync_n
:
std_logic_vector
(
1
downto
0
);
...
...
@@ -264,10 +282,8 @@ architecture struct of xwrc_board_svec is
signal
onewire_en
:
std_logic_vector
(
1
downto
0
);
-- PHY
signal
phy8_to_wrc
:
t_phy_8bits_to_wrc
;
signal
phy8_from_wrc
:
t_phy_8bits_from_wrc
;
signal
phy16_to_wrc
:
t_phy_16bits_to_wrc
;
signal
phy16_from_wrc
:
t_phy_16bits_from_wrc
;
signal
phy8_to_wrc
:
t_phy_8bits_to_wrc
;
signal
phy8_from_wrc
:
t_phy_8bits_from_wrc
;
-- External reference
signal
ext_ref_mul
:
std_logic
;
...
...
@@ -318,8 +334,6 @@ begin -- architecture struct
clk_10m_ext_o
=>
clk_10m_ext
,
phy8_o
=>
phy8_to_wrc
,
phy8_i
=>
phy8_from_wrc
,
phy16_o
=>
phy16_to_wrc
,
phy16_i
=>
phy16_from_wrc
,
ext_ref_mul_o
=>
ext_ref_mul
,
ext_ref_mul_locked_o
=>
ext_ref_mul_locked
,
ext_ref_mul_stopped_o
=>
ext_ref_mul_stopped
,
...
...
@@ -337,10 +351,11 @@ begin -- architecture struct
-- concatenation of all clocks required to have synced resets
rstlogic_clk_in
(
0
)
<=
clk_pll_62m5
;
rstlogic_clk_in
(
1
)
<=
clk_pll_125m
;
cmp_rstlogic_reset
:
gc_reset
generic
map
(
g_clocks
=>
1
,
-- 62.
5MHz
g_clocks
=>
2
,
-- 62.5MHz, 12
5MHz
g_logdelay
=>
4
,
-- 16 clock cycles
g_syncdepth
=>
3
)
-- length of sync chains
port
map
(
...
...
@@ -353,6 +368,7 @@ begin -- architecture struct
rst_62m5_n
<=
rstlogic_rst_out
(
0
);
rst_sys_62m5_n_o
<=
rst_62m5_n
;
rst_ref_125m_n_o
<=
rstlogic_rst_out
(
1
);
-----------------------------------------------------------------------------
-- 2x SPI DAC
...
...
@@ -390,7 +406,7 @@ begin -- architecture struct
g_with_external_clock_input
=>
g_with_external_clock_input
,
g_phys_uart
=>
TRUE
,
g_virtual_uart
=>
TRUE
,
g_aux_clks
=>
0
,
g_aux_clks
=>
g_aux_clks
,
g_ep_rxbuf_size
=>
1024
,
g_tx_runt_padding
=>
TRUE
,
g_dpram_initf
=>
g_dpram_initf
,
...
...
@@ -413,7 +429,7 @@ begin -- architecture struct
clk_sys_i
=>
clk_pll_62m5
,
clk_dmtd_i
=>
clk_pll_dmtd
,
clk_ref_i
=>
clk_pll_125m
,
clk_aux_i
=>
(
others
=>
'0'
)
,
clk_aux_i
=>
clk_aux_i
,
clk_ext_i
=>
clk_10m_ext
,
clk_ext_mul_i
=>
ext_ref_mul
,
clk_ext_mul_locked_i
=>
ext_ref_mul_locked
,
...
...
@@ -427,10 +443,6 @@ begin -- architecture struct
dac_dpll_data_o
=>
dac_dpll_data
,
phy8_o
=>
phy8_from_wrc
,
phy8_i
=>
phy8_to_wrc
,
phy16_o
=>
phy16_from_wrc
,
phy16_i
=>
phy16_to_wrc
,
led_act_o
=>
led_act_o
,
led_link_o
=>
led_link_o
,
scl_o
=>
eeprom_scl_o
,
scl_i
=>
eeprom_scl_i
,
sda_o
=>
eeprom_sda_o
,
...
...
@@ -440,8 +452,6 @@ begin -- architecture struct
sfp_sda_o
=>
sfp_sda_o
,
sfp_sda_i
=>
sfp_sda_i
,
sfp_det_i
=>
sfp_det_i
,
btn1_i
=>
'1'
,
btn2_i
=>
'1'
,
spi_sclk_o
=>
spi_sclk_o
,
spi_ncs_o
=>
spi_ncs_o
,
spi_mosi_o
=>
spi_mosi_o
,
...
...
@@ -469,24 +479,28 @@ begin -- architecture struct
wrs_rx_dreq_i
=>
wrs_rx_dreq_i
,
wb_eth_master_o
=>
wb_eth_master_o
,
wb_eth_master_i
=>
wb_eth_master_i
,
timestamps_o
=>
open
,
timestamps_ack_i
=>
'1'
,
fc_tx_pause_req_i
=>
'0'
,
fc_tx_pause_delay_i
=>
(
others
=>
'0'
),
fc_tx_pause_ready_o
=>
open
,
tm_link_up_o
=>
open
,
tm_dac_value_o
=>
open
,
tm_dac_wr_o
=>
open
,
tm_clk_aux_lock_en_i
=>
(
others
=>
'0'
),
tm_clk_aux_locked_o
=>
open
,
aux_diag_i
=>
aux_diag_i
,
aux_diag_o
=>
aux_diag_o
,
tm_dac_value_o
=>
tm_dac_value_o
,
tm_dac_wr_o
=>
tm_dac_wr_o
,
tm_clk_aux_lock_en_i
=>
tm_clk_aux_lock_en_i
,
tm_clk_aux_locked_o
=>
tm_clk_aux_locked_o
,
timestamps_o
=>
timestamps_o
,
timestamps_ack_i
=>
timestamps_ack_i
,
fc_tx_pause_req_i
=>
fc_tx_pause_req_i
,
fc_tx_pause_delay_i
=>
fc_tx_pause_delay_i
,
fc_tx_pause_ready_o
=>
fc_tx_pause_ready_o
,
tm_link_up_o
=>
tm_link_up_o
,
tm_time_valid_o
=>
tm_time_valid_o
,
tm_tai_o
=>
tm_tai_o
,
tm_cycles_o
=>
tm_cycles_o
,
led_act_o
=>
led_act_o
,
led_link_o
=>
led_link_o
,
btn1_i
=>
btn1_i
,
btn2_i
=>
btn2_i
,
pps_p_o
=>
pps_p_o
,
pps_led_o
=>
pps_led_o
,
aux_diag_i
=>
aux_diag_i
,
aux_diag_o
=>
aux_diag_o
,
link_ok_o
=>
open
);
link_ok_o
=>
link_ok_o
);
sfp_rate_select_o
<=
'1'
;
...
...
board/vfchd/wr_vfchd_pkg.vhd
View file @
b3ad9a9c
...
...
@@ -5,6 +5,7 @@ library work;
use
work
.
wrcore_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
wr_fabric_pkg
.
all
;
use
work
.
endpoint_pkg
.
all
;
use
work
.
wr_board_pkg
.
all
;
package
wr_vfchd_pkg
is
...
...
@@ -13,8 +14,9 @@ package wr_vfchd_pkg is
generic
(
g_simulation
:
integer
:
=
0
;
g_with_external_clock_input
:
boolean
:
=
TRUE
;
g_aux_clks
:
integer
:
=
0
;
g_pcs_16bit
:
boolean
:
=
FALSE
;
g_fabric_iface
:
t_board_fabric_iface
:
=
PLAIN
;
g_fabric_iface
:
t_board_fabric_iface
:
=
plain
;
g_tx_streamer_width
:
integer
:
=
32
;
g_rx_streamer_width
:
integer
:
=
32
;
g_dpram_initf
:
string
:
=
"default_altera"
;
...
...
@@ -23,58 +25,73 @@ package wr_vfchd_pkg is
g_diag_ro_size
:
integer
:
=
0
;
g_diag_rw_size
:
integer
:
=
0
);
port
(
clk_board_125m_i
:
in
std_logic
;
clk_board_20m_i
:
in
std_logic
;
clk_ext_10m_i
:
in
std_logic
;
areset_n_i
:
in
std_logic
;
clk_sys_62m5_o
:
out
std_logic
;
clk_ref_125m_o
:
out
std_logic
;
rst_sys_62m5_n_o
:
out
std_logic
;
dac_ref_sync_n_o
:
out
std_logic
;
dac_dmtd_sync_n_o
:
out
std_logic
;
dac_din_o
:
out
std_logic
;
dac_sclk_o
:
out
std_logic
;
sfp_tx_o
:
out
std_logic
;
sfp_rx_i
:
in
std_logic
;
sfp_det_valid_i
:
in
std_logic
;
sfp_data_i
:
in
std_logic_vector
(
127
downto
0
);
sfp_tx_fault_i
:
in
std_logic
;
sfp_los_i
:
in
std_logic
;
sfp_tx_disable_o
:
out
std_logic
;
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
eeprom_scl_o
:
out
std_logic
;
onewire_i
:
in
std_logic
;
onewire_oen_o
:
out
std_logic
;
wb_slave_o
:
out
t_wishbone_slave_out
;
wb_slave_i
:
in
t_wishbone_slave_in
:
=
cc_dummy_slave_in
;
wrf_src_o
:
out
t_wrf_source_out
;
wrf_src_i
:
in
t_wrf_source_in
:
=
c_dummy_src_in
;
wrf_snk_o
:
out
t_wrf_sink_out
;
wrf_snk_i
:
in
t_wrf_sink_in
:
=
c_dummy_snk_in
;
wrs_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wb_eth_master_o
:
out
t_wishbone_master_out
;
wb_eth_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
pps_ext_i
:
in
std_logic
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
led_link_o
:
out
std_logic
;
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
aux_diag_o
:
out
t_generic_word_array
(
g_diag_rw_size
-1
downto
0
);
led_act_o
:
out
std_logic
);
clk_board_125m_i
:
in
std_logic
;
clk_board_20m_i
:
in
std_logic
;
clk_aux_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
clk_ext_10m_i
:
in
std_logic
:
=
'0'
;
pps_ext_i
:
in
std_logic
:
=
'0'
;
areset_n_i
:
in
std_logic
;
clk_sys_62m5_o
:
out
std_logic
;
clk_ref_125m_o
:
out
std_logic
;
rst_sys_62m5_n_o
:
out
std_logic
;
rst_ref_125m_n_o
:
out
std_logic
;
dac_ref_sync_n_o
:
out
std_logic
;
dac_dmtd_sync_n_o
:
out
std_logic
;
dac_din_o
:
out
std_logic
;
dac_sclk_o
:
out
std_logic
;
sfp_tx_o
:
out
std_logic
;
sfp_rx_i
:
in
std_logic
;
sfp_det_valid_i
:
in
std_logic
:
=
'0'
;
sfp_data_i
:
in
std_logic_vector
(
127
downto
0
);
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_los_i
:
in
std_logic
:
=
'0'
;
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
eeprom_scl_o
:
out
std_logic
;
onewire_i
:
in
std_logic
;
onewire_oen_o
:
out
std_logic
;
wb_slave_o
:
out
t_wishbone_slave_out
;
wb_slave_i
:
in
t_wishbone_slave_in
:
=
cc_dummy_slave_in
;
wrf_src_o
:
out
t_wrf_source_out
;
wrf_src_i
:
in
t_wrf_source_in
:
=
c_dummy_src_in
;
wrf_snk_o
:
out
t_wrf_sink_out
;
wrf_snk_i
:
in
t_wrf_sink_in
:
=
c_dummy_snk_in
;
wrs_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wb_eth_master_o
:
out
t_wishbone_master_out
;
wb_eth_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
aux_diag_o
:
out
t_generic_word_array
(
g_diag_rw_size
-1
downto
0
);
tm_dac_value_o
:
out
std_logic_vector
(
23
downto
0
);
tm_dac_wr_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tm_clk_aux_lock_en_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
tm_clk_aux_locked_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
timestamps_o
:
out
t_txtsu_timestamp
;
timestamps_ack_i
:
in
std_logic
:
=
'1'
;
fc_tx_pause_req_i
:
in
std_logic
:
=
'0'
;
fc_tx_pause_delay_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
fc_tx_pause_ready_o
:
out
std_logic
;
tm_link_up_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
led_act_o
:
out
std_logic
;
led_link_o
:
out
std_logic
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
link_ok_o
:
out
std_logic
);
end
component
xwrc_board_vfchd
;
component
wrc_board_vfchd
is
...
...
@@ -82,103 +99,123 @@ package wr_vfchd_pkg is
g_simulation
:
integer
:
=
0
;
g_with_external_clock_input
:
integer
:
=
1
;
g_pcs_16bit
:
integer
:
=
0
;
g_fabric_iface
:
string
:
=
"PLAINFBRC"
;
g_aux_clks
:
integer
:
=
0
;
g_fabric_iface
:
string
:
=
"plainfbrc"
;
g_tx_streamer_width
:
integer
:
=
32
;
g_rx_streamer_width
:
integer
:
=
32
;
g_dpram_initf
:
string
:
=
"default_altera"
;
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
g_diag_ro_vector_width
:
integer
:
=
0
;
g_diag_rw_vector_width
:
integer
:
=
0
);
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
g_diag_ro_vector_width
:
integer
:
=
0
;
g_diag_rw_vector_width
:
integer
:
=
0
);
port
(
clk_board_125m_i
:
in
std_logic
;
clk_board_20m_i
:
in
std_logic
;
clk_ext_10m_i
:
in
std_logic
;
areset_n_i
:
in
std_logic
;
clk_sys_62m5_o
:
out
std_logic
;
clk_ref_125m_o
:
out
std_logic
;
rst_sys_62m5_n_o
:
out
std_logic
;
dac_ref_sync_n_o
:
out
std_logic
;
dac_dmtd_sync_n_o
:
out
std_logic
;
dac_din_o
:
out
std_logic
;
dac_sclk_o
:
out
std_logic
;
sfp_tx_o
:
out
std_logic
;
sfp_rx_i
:
in
std_logic
;
sfp_det_valid_i
:
in
std_logic
;
sfp_data_i
:
in
std_logic_vector
(
127
downto
0
);
sfp_tx_fault_i
:
in
std_logic
;
sfp_los_i
:
in
std_logic
;
sfp_tx_disable_o
:
out
std_logic
;
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
eeprom_scl_o
:
out
std_logic
;
onewire_i
:
in
std_logic
;
onewire_oen_o
:
out
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_sel_i
:
in
std_logic_vector
(
c_wishbone_address_width
/
8-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_we_i
:
in
std_logic
:
=
'0'
;
wb_cyc_i
:
in
std_logic
:
=
'0'
;
wb_stb_i
:
in
std_logic
:
=
'0'
;
wb_ack_o
:
out
std_logic
;
wb_int_o
:
out
std_logic
;
wb_err_o
:
out
std_logic
;
wb_rty_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
wrf_src_adr
:
out
std_logic_vector
(
1
downto
0
);
wrf_src_dat
:
out
std_logic_vector
(
15
downto
0
);
wrf_src_cyc
:
out
std_logic
;
wrf_src_stb
:
out
std_logic
;
wrf_src_we
:
out
std_logic
;
wrf_src_sel
:
out
std_logic_vector
(
1
downto
0
);
wrf_src_ack
:
in
std_logic
;
wrf_src_stall
:
in
std_logic
;
wrf_src_err
:
in
std_logic
;
wrf_src_rty
:
in
std_logic
;
wrf_snk_adr
:
in
std_logic_vector
(
1
downto
0
);
wrf_snk_dat
:
in
std_logic_vector
(
15
downto
0
);
wrf_snk_cyc
:
in
std_logic
;
wrf_snk_stb
:
in
std_logic
;
wrf_snk_we
:
in
std_logic
;
wrf_snk_sel
:
in
std_logic_vector
(
1
downto
0
);
wrf_snk_ack
:
out
std_logic
;
wrf_snk_stall
:
out
std_logic
;
wrf_snk_err
:
out
std_logic
;
wrf_snk_rty
:
out
std_logic
;
trans_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
trans_tx_valid_i
:
in
std_logic
:
=
'0'
;
trans_tx_dreq_o
:
out
std_logic
;
trans_tx_last_i
:
in
std_logic
:
=
'1'
;
trans_tx_flush_i
:
in
std_logic
:
=
'0'
;
trans_rx_first_o
:
out
std_logic
;
trans_rx_last_o
:
out
std_logic
;
trans_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_width
-1
downto
0
);
trans_rx_valid_o
:
out
std_logic
;
trans_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wb_eth_adr_o
:
out
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
);
wb_eth_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_eth_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_eth_sel_o
:
out
std_logic_vector
(
c_wishbone_address_width
/
8-1
downto
0
);
wb_eth_we_o
:
out
std_logic
;
wb_eth_cyc_o
:
out
std_logic
;
wb_eth_stb_o
:
out
std_logic
;
wb_eth_ack_i
:
in
std_logic
:
=
'0'
;
wb_eth_int_i
:
in
std_logic
:
=
'0'
;
wb_eth_err_i
:
in
std_logic
:
=
'0'
;
wb_eth_rty_i
:
in
std_logic
:
=
'0'
;
wb_eth_stall_i
:
in
std_logic
:
=
'0'
;
pps_ext_i
:
in
std_logic
:
=
'0'
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
led_link_o
:
out
std_logic
;
aux_diag_i
:
in
std_logic_vector
(
g_diag_ro_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
aux_diag_o
:
out
std_logic_vector
(
g_diag_rw_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
led_act_o
:
out
std_logic
);
clk_board_125m_i
:
in
std_logic
;
clk_board_20m_i
:
in
std_logic
;
clk_aux_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
clk_ext_10m_i
:
in
std_logic
:
=
'0'
;
pps_ext_i
:
in
std_logic
:
=
'0'
;
areset_n_i
:
in
std_logic
;
clk_sys_62m5_o
:
out
std_logic
;
clk_ref_125m_o
:
out
std_logic
;
rst_sys_62m5_n_o
:
out
std_logic
;
rst_ref_125m_n_o
:
out
std_logic
;
dac_ref_sync_n_o
:
out
std_logic
;
dac_dmtd_sync_n_o
:
out
std_logic
;
dac_din_o
:
out
std_logic
;
dac_sclk_o
:
out
std_logic
;
sfp_tx_o
:
out
std_logic
;
sfp_rx_i
:
in
std_logic
;
sfp_det_valid_i
:
in
std_logic
:
=
'0'
;
sfp_data_i
:
in
std_logic_vector
(
127
downto
0
);
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_los_i
:
in
std_logic
:
=
'0'
;
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
eeprom_scl_o
:
out
std_logic
;
onewire_i
:
in
std_logic
;
onewire_oen_o
:
out
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_sel_i
:
in
std_logic_vector
(
c_wishbone_address_width
/
8-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_we_i
:
in
std_logic
:
=
'0'
;
wb_cyc_i
:
in
std_logic
:
=
'0'
;
wb_stb_i
:
in
std_logic
:
=
'0'
;
wb_ack_o
:
out
std_logic
;
wb_int_o
:
out
std_logic
;
wb_err_o
:
out
std_logic
;
wb_rty_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
wrf_src_adr_o
:
out
std_logic_vector
(
1
downto
0
);
wrf_src_dat_o
:
out
std_logic_vector
(
15
downto
0
);
wrf_src_cyc_o
:
out
std_logic
;
wrf_src_stb_o
:
out
std_logic
;
wrf_src_we_o
:
out
std_logic
;
wrf_src_sel_o
:
out
std_logic_vector
(
1
downto
0
);
wrf_src_ack_i
:
in
std_logic
;
wrf_src_stall_i
:
in
std_logic
;
wrf_src_err_i
:
in
std_logic
;
wrf_src_rty_i
:
in
std_logic
;
wrf_snk_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wrf_snk_dat_i
:
in
std_logic_vector
(
15
downto
0
);
wrf_snk_cyc_i
:
in
std_logic
;
wrf_snk_stb_i
:
in
std_logic
;
wrf_snk_we_i
:
in
std_logic
;
wrf_snk_sel_i
:
in
std_logic_vector
(
1
downto
0
);
wrf_snk_ack_o
:
out
std_logic
;
wrf_snk_stall_o
:
out
std_logic
;
wrf_snk_err_o
:
out
std_logic
;
wrf_snk_rty_o
:
out
std_logic
;
wrs_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wb_eth_adr_o
:
out
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
);
wb_eth_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_eth_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_eth_sel_o
:
out
std_logic_vector
(
c_wishbone_address_width
/
8-1
downto
0
);
wb_eth_we_o
:
out
std_logic
;
wb_eth_cyc_o
:
out
std_logic
;
wb_eth_stb_o
:
out
std_logic
;
wb_eth_ack_i
:
in
std_logic
:
=
'0'
;
wb_eth_int_i
:
in
std_logic
:
=
'0'
;
wb_eth_err_i
:
in
std_logic
:
=
'0'
;
wb_eth_rty_i
:
in
std_logic
:
=
'0'
;
wb_eth_stall_i
:
in
std_logic
:
=
'0'
;
aux_diag_i
:
in
std_logic_vector
(
g_diag_ro_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
aux_diag_o
:
out
std_logic_vector
(
g_diag_rw_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
tm_dac_value_o
:
out
std_logic_vector
(
23
downto
0
);
tm_dac_wr_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tm_clk_aux_lock_en_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
tm_clk_aux_locked_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tstamps_stb_o
:
out
std_logic
;
tstamps_tsval_o
:
out
std_logic_vector
(
31
downto
0
);
tstamps_port_id_o
:
out
std_logic_vector
(
5
downto
0
);
tstamps_frame_id_o
:
out
std_logic_vector
(
15
downto
0
);
tstamps_incorrect_o
:
out
std_logic
;
tstamps_ack_i
:
in
std_logic
:
=
'1'
;
fc_tx_pause_req_i
:
in
std_logic
:
=
'0'
;
fc_tx_pause_delay_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
fc_tx_pause_ready_o
:
out
std_logic
;
tm_link_up_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
led_act_o
:
out
std_logic
;
led_link_o
:
out
std_logic
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
link_ok_o
:
out
std_logic
);
end
component
wrc_board_vfchd
;
component
sfp_i2c_adapter
is
...
...
board/vfchd/wrc_board_vfchd.vhd
View file @
b3ad9a9c
...
...
@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2016-07-26
-- Last update: 2017-0
2-22
-- Last update: 2017-0
3-08
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
...
...
@@ -61,6 +61,8 @@ entity wrc_board_vfchd is
g_with_external_clock_input
:
integer
:
=
1
;
-- set to 1 to use 16bit PCS (instead of default 8bit PCS)
g_pcs_16bit
:
integer
:
=
0
;
-- Number of aux clocks syntonized by WRPC to WR timebase
g_aux_clks
:
integer
:
=
0
;
-- "plainfbrc" = expose WRC fabric interface
-- "streamers" = attach WRC streamers to fabric interface
-- "etherbone" = attach Etherbone slave to fabric interface
...
...
@@ -71,40 +73,38 @@ entity wrc_board_vfchd is
-- memory initialisation file for embedded CPU
g_dpram_initf
:
string
:
=
"default_altera"
;
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
-- size the generic diag interface
g_diag_ro_vector_width
:
integer
:
=
0
;
g_diag_rw_vector_width
:
integer
:
=
0
g_diag_ro_vector_width
:
integer
:
=
0
;
g_diag_rw_vector_width
:
integer
:
=
0
);
port
(
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Clock inputs from the board
clk_board_125m_i
:
in
std_logic
;
clk_board_20m_i
:
in
std_logic
;
clk_board_125m_i
:
in
std_logic
;
clk_board_20m_i
:
in
std_logic
;
-- Aux clocks, which can be disciplined by the WR Core
clk_aux_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_ext_10m_i
:
in
std_logic
:
=
'0'
;
clk_ext_10m_i
:
in
std_logic
:
=
'0'
;
-- External PPS input (g_with_external_clock_input = TRUE)
pps_ext_i
:
in
std_logic
:
=
'0'
;
-- Reset input (active low, can be async)
areset_n_i
:
in
std_logic
;
areset_n_i
:
in
std_logic
;
-- 62.5MHz sys clock output
clk_sys_62m5_o
:
out
std_logic
;
clk_sys_62m5_o
:
out
std_logic
;
-- 125MHz ref clock output
clk_ref_125m_o
:
out
std_logic
;
-- active low reset output, synchronous to clk_sys_62m5_o
clk_ref_125m_o
:
out
std_logic
;
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o
:
out
std_logic
;
rst_ref_125m_n_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- SPI interfaces to DACs
---------------------------------------------------------------------------
dac_ref_sync_n_o
:
out
std_logic
;
dac_dmtd_sync_n_o
:
out
std_logic
;
dac_din_o
:
out
std_logic
;
...
...
@@ -113,26 +113,22 @@ entity wrc_board_vfchd is
---------------------------------------------------------------------------
-- SFP I/O for transceiver and SFP management info from VFC-HD
---------------------------------------------------------------------------
sfp_tx_o
:
out
std_logic
;
sfp_rx_i
:
in
std_logic
;
sfp_tx_o
:
out
std_logic
;
sfp_rx_i
:
in
std_logic
;
-- HIGH if both of the following are true:
-- 1. SFP is detected (plugged in)
-- 2. The part number has been successfully read after the SFP detection
sfp_det_valid_i
:
in
std_logic
;
sfp_det_valid_i
:
in
std_logic
:
=
'0'
;
-- 16 byte vendor Part Number (PN)
-- (ASCII encoded, first character byte in bits 127 downto 120)
sfp_data_i
:
in
std_logic_vector
(
127
downto
0
);
sfp_tx_fault_i
:
in
std_logic
;
sfp_los_i
:
in
std_logic
;
sfp_data_i
:
in
std_logic_vector
(
127
downto
0
);
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_los_i
:
in
std_logic
:
=
'0'
;
---------------------------------------------------------------------------
-- I2C EEPROM
---------------------------------------------------------------------------
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
...
...
@@ -141,14 +137,12 @@ entity wrc_board_vfchd is
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_i
:
in
std_logic
;
onewire_oen_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- External WB interface
---------------------------------------------------------------------------
wb_adr_i
:
in
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
...
...
@@ -165,7 +159,6 @@ entity wrc_board_vfchd is
---------------------------------------------------------------------------
-- WR fabric interface (when g_fabric_iface = "plain")
---------------------------------------------------------------------------
wrf_src_adr_o
:
out
std_logic_vector
(
1
downto
0
);
wrf_src_dat_o
:
out
std_logic_vector
(
15
downto
0
);
wrf_src_cyc_o
:
out
std_logic
;
...
...
@@ -190,22 +183,20 @@ entity wrc_board_vfchd is
---------------------------------------------------------------------------
-- WR streamers (when g_fabric_iface = "streamers")
---------------------------------------------------------------------------
wrs_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
---------------------------------------------------------------------------
-- Etherbone WB master interface (when g_fabric_iface = "etherbone")
---------------------------------------------------------------------------
wb_eth_adr_o
:
out
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
);
wb_eth_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_eth_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
...
...
@@ -222,21 +213,55 @@ entity wrc_board_vfchd is
---------------------------------------------------------------------------
-- Generic diagnostics interface (access from WRPC via SNMP or uart console
---------------------------------------------------------------------------
aux_diag_i
:
in
std_logic_vector
(
g_diag_ro_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
aux_diag_o
:
out
std_logic_vector
(
g_diag_rw_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
aux_diag_i
:
in
std_logic_vector
(
g_diag_ro_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
aux_diag_o
:
out
std_logic_vector
(
g_diag_rw_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
---------------------------------------------------------------------------
-- Aux clocks control
---------------------------------------------------------------------------
tm_dac_value_o
:
out
std_logic_vector
(
23
downto
0
);
tm_dac_wr_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tm_clk_aux_lock_en_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
tm_clk_aux_locked_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
---------------------------------------------------------------------------
--
WRPC timing interface and status
--
External Tx Timestamping I/F
---------------------------------------------------------------------------
tstamps_stb_o
:
out
std_logic
;
tstamps_tsval_o
:
out
std_logic_vector
(
31
downto
0
);
tstamps_port_id_o
:
out
std_logic_vector
(
5
downto
0
);
tstamps_frame_id_o
:
out
std_logic_vector
(
15
downto
0
);
tstamps_incorrect_o
:
out
std_logic
;
tstamps_ack_i
:
in
std_logic
:
=
'1'
;
pps_ext_i
:
in
std_logic
:
=
'0'
;
pps_p_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- Pause Frame Control
---------------------------------------------------------------------------
fc_tx_pause_req_i
:
in
std_logic
:
=
'0'
;
fc_tx_pause_delay_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
fc_tx_pause_ready_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- Timecode I/F
---------------------------------------------------------------------------
tm_link_up_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
led_link_o
:
out
std_logic
;
led_act_o
:
out
std_logic
);
---------------------------------------------------------------------------
-- Buttons, LEDs and PPS output
---------------------------------------------------------------------------
led_act_o
:
out
std_logic
;
led_link_o
:
out
std_logic
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
-- 1PPS output
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
-- Link ok indication
link_ok_o
:
out
std_logic
);
end
entity
wrc_board_vfchd
;
...
...
@@ -262,12 +287,15 @@ architecture std_wrapper of wrc_board_vfchd is
signal
wb_eth_master_in
:
t_wishbone_master_in
;
-- Aux diagnostics
constant
c_diag_ro_size
:
integer
:
=
g_diag_ro_vector_width
/
32
;
constant
c_diag_rw_size
:
integer
:
=
g_diag_rw_vector_width
/
32
;
constant
c_diag_ro_size
:
integer
:
=
g_diag_ro_vector_width
/
32
;
constant
c_diag_rw_size
:
integer
:
=
g_diag_rw_vector_width
/
32
;
signal
aux_diag_in
:
t_generic_word_array
(
c_diag_ro_size
-1
downto
0
);
signal
aux_diag_out
:
t_generic_word_array
(
c_diag_rw_size
-1
downto
0
);
-- External Tx Timestamping I/F
signal
timestamps_out
:
t_txtsu_timestamp
;
begin
-- architecture struct
-- Map top-level signals to internal records
...
...
@@ -322,15 +350,20 @@ begin -- architecture struct
wb_eth_master_in
.
rty
<=
wb_eth_rty_i
;
wb_eth_master_in
.
stall
<=
wb_eth_stall_i
;
-- auxiliary diagnostics
aux_diag_in
<=
f_de_vectorize_diag
(
aux_diag_i
,
g_diag_ro_vector_width
);
aux_diag_in
<=
f_de_vectorize_diag
(
aux_diag_i
,
g_diag_ro_vector_width
);
aux_diag_o
<=
f_vectorize_diag
(
aux_diag_out
,
g_diag_rw_vector_width
);
tstamps_stb_o
<=
timestamps_out
.
stb
;
tstamps_tsval_o
<=
timestamps_out
.
tsval
;
tstamps_port_id_o
<=
timestamps_out
.
port_id
;
tstamps_frame_id_o
<=
timestamps_out
.
frame_id
;
-- Instantiate the records-based module
cmp_xwrc_board_vfchd
:
xwrc_board_vfchd
generic
map
(
g_simulation
=>
g_simulation
,
g_with_external_clock_input
=>
f_int2bool
(
g_with_external_clock_input
),
g_aux_clks
=>
g_aux_clks
,
g_pcs_16bit
=>
f_int2bool
(
g_pcs_16bit
),
g_fabric_iface
=>
f_str2iface_type
(
g_fabric_iface
),
g_tx_streamer_width
=>
g_tx_streamer_width
,
...
...
@@ -341,56 +374,71 @@ begin -- architecture struct
g_diag_ro_size
=>
c_diag_ro_size
,
g_diag_rw_size
=>
c_diag_rw_size
)
port
map
(
clk_board_125m_i
=>
clk_board_125m_i
,
clk_board_20m_i
=>
clk_board_20m_i
,
clk_ext_10m_i
=>
clk_ext_10m_i
,
areset_n_i
=>
areset_n_i
,
clk_sys_62m5_o
=>
clk_sys_62m5_o
,
clk_ref_125m_o
=>
clk_ref_125m_o
,
rst_sys_62m5_n_o
=>
rst_sys_62m5_n_o
,
dac_ref_sync_n_o
=>
dac_ref_sync_n_o
,
dac_dmtd_sync_n_o
=>
dac_dmtd_sync_n_o
,
dac_din_o
=>
dac_din_o
,
dac_sclk_o
=>
dac_sclk_o
,
sfp_tx_o
=>
sfp_tx_o
,
sfp_rx_i
=>
sfp_rx_i
,
sfp_det_valid_i
=>
sfp_det_valid_i
,
sfp_data_i
=>
sfp_data_i
,
sfp_tx_fault_i
=>
sfp_tx_fault_i
,
sfp_los_i
=>
sfp_los_i
,
sfp_tx_disable_o
=>
sfp_tx_disable_o
,
eeprom_sda_i
=>
eeprom_sda_i
,
eeprom_sda_o
=>
eeprom_sda_o
,
eeprom_scl_i
=>
eeprom_scl_i
,
eeprom_scl_o
=>
eeprom_scl_o
,
onewire_i
=>
onewire_i
,
onewire_oen_o
=>
onewire_oen_o
,
wb_slave_o
=>
wb_slave_out
,
wb_slave_i
=>
wb_slave_in
,
wrf_src_o
=>
wrf_src_out
,
wrf_src_i
=>
wrf_src_in
,
wrf_snk_o
=>
wrf_snk_out
,
wrf_snk_i
=>
wrf_snk_in
,
wrs_tx_data_i
=>
wrs_tx_data_i
,
wrs_tx_valid_i
=>
wrs_tx_valid_i
,
wrs_tx_dreq_o
=>
wrs_tx_dreq_o
,
wrs_tx_last_i
=>
wrs_tx_last_i
,
wrs_tx_flush_i
=>
wrs_tx_flush_i
,
wrs_rx_first_o
=>
wrs_rx_first_o
,
wrs_rx_last_o
=>
wrs_rx_last_o
,
wrs_rx_data_o
=>
wrs_rx_data_o
,
wrs_rx_valid_o
=>
wrs_rx_valid_o
,
wrs_rx_dreq_i
=>
wrs_rx_dreq_i
,
wb_eth_master_o
=>
wb_eth_master_out
,
wb_eth_master_i
=>
wb_eth_master_in
,
pps_ext_i
=>
pps_ext_i
,
pps_p_o
=>
pps_p_o
,
tm_time_valid_o
=>
tm_time_valid_o
,
tm_tai_o
=>
tm_tai_o
,
tm_cycles_o
=>
tm_cycles_o
,
led_link_o
=>
led_link_o
,
aux_diag_i
=>
aux_diag_in
,
aux_diag_o
=>
aux_diag_out
,
led_act_o
=>
led_act_o
);
clk_board_125m_i
=>
clk_board_125m_i
,
clk_board_20m_i
=>
clk_board_20m_i
,
clk_aux_i
=>
clk_aux_i
,
clk_ext_10m_i
=>
clk_ext_10m_i
,
areset_n_i
=>
areset_n_i
,
clk_sys_62m5_o
=>
clk_sys_62m5_o
,
clk_ref_125m_o
=>
clk_ref_125m_o
,
rst_sys_62m5_n_o
=>
rst_sys_62m5_n_o
,
rst_ref_125m_n_o
=>
rst_ref_125m_n_o
,
dac_ref_sync_n_o
=>
dac_ref_sync_n_o
,
dac_dmtd_sync_n_o
=>
dac_dmtd_sync_n_o
,
dac_din_o
=>
dac_din_o
,
dac_sclk_o
=>
dac_sclk_o
,
sfp_tx_o
=>
sfp_tx_o
,
sfp_rx_i
=>
sfp_rx_i
,
sfp_det_valid_i
=>
sfp_det_valid_i
,
sfp_data_i
=>
sfp_data_i
,
sfp_tx_fault_i
=>
sfp_tx_fault_i
,
sfp_tx_disable_o
=>
sfp_tx_disable_o
,
sfp_los_i
=>
sfp_los_i
,
eeprom_sda_i
=>
eeprom_sda_i
,
eeprom_sda_o
=>
eeprom_sda_o
,
eeprom_scl_i
=>
eeprom_scl_i
,
eeprom_scl_o
=>
eeprom_scl_o
,
onewire_i
=>
onewire_i
,
onewire_oen_o
=>
onewire_oen_o
,
wb_slave_o
=>
wb_slave_out
,
wb_slave_i
=>
wb_slave_in
,
wrf_src_o
=>
wrf_src_out
,
wrf_src_i
=>
wrf_src_in
,
wrf_snk_o
=>
wrf_snk_out
,
wrf_snk_i
=>
wrf_snk_in
,
wrs_tx_data_i
=>
wrs_tx_data_i
,
wrs_tx_valid_i
=>
wrs_tx_valid_i
,
wrs_tx_dreq_o
=>
wrs_tx_dreq_o
,
wrs_tx_last_i
=>
wrs_tx_last_i
,
wrs_tx_flush_i
=>
wrs_tx_flush_i
,
wrs_rx_first_o
=>
wrs_rx_first_o
,
wrs_rx_last_o
=>
wrs_rx_last_o
,
wrs_rx_data_o
=>
wrs_rx_data_o
,
wrs_rx_valid_o
=>
wrs_rx_valid_o
,
wrs_rx_dreq_i
=>
wrs_rx_dreq_i
,
wb_eth_master_o
=>
wb_eth_master_out
,
wb_eth_master_i
=>
wb_eth_master_in
,
aux_diag_i
=>
aux_diag_in
,
aux_diag_o
=>
aux_diag_out
,
tm_dac_value_o
=>
tm_dac_value_o
,
tm_dac_wr_o
=>
tm_dac_wr_o
,
tm_clk_aux_lock_en_i
=>
tm_clk_aux_lock_en_i
,
tm_clk_aux_locked_o
=>
tm_clk_aux_locked_o
,
timestamps_o
=>
timestamps_out
,
timestamps_ack_i
=>
tstamps_ack_i
,
fc_tx_pause_req_i
=>
fc_tx_pause_req_i
,
fc_tx_pause_delay_i
=>
fc_tx_pause_delay_i
,
fc_tx_pause_ready_o
=>
fc_tx_pause_ready_o
,
tm_link_up_o
=>
tm_link_up_o
,
tm_time_valid_o
=>
tm_time_valid_o
,
tm_tai_o
=>
tm_tai_o
,
tm_cycles_o
=>
tm_cycles_o
,
led_act_o
=>
led_act_o
,
led_link_o
=>
led_link_o
,
btn1_i
=>
btn1_i
,
btn2_i
=>
btn2_i
,
pps_p_o
=>
pps_p_o
,
pps_led_o
=>
pps_led_o
,
link_ok_o
=>
link_ok_o
);
end
architecture
std_wrapper
;
board/vfchd/xwrc_board_vfchd.vhd
View file @
b3ad9a9c
...
...
@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2016-07-26
-- Last update: 2017-03-0
7
-- Last update: 2017-03-0
8
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
...
...
@@ -57,6 +57,8 @@ entity xwrc_board_vfchd is
g_simulation
:
integer
:
=
0
;
-- Select whether to include external ref clock input
g_with_external_clock_input
:
boolean
:
=
TRUE
;
-- Number of aux clocks syntonized by WRPC to WR timebase
g_aux_clks
:
integer
:
=
0
;
-- set to TRUE to use 16bit PCS (instead of default 8bit PCS)
g_pcs_16bit
:
boolean
:
=
FALSE
;
-- plain = expose WRC fabric interface
...
...
@@ -64,45 +66,43 @@ entity xwrc_board_vfchd is
-- etherbone = attach Etherbone slave to fabric interface
g_fabric_iface
:
t_board_fabric_iface
:
=
plain
;
-- data width when g_fabric_iface = "streamers" (otherwise ignored)
g_tx_streamer_width
:
integer
:
=
32
;
g_rx_streamer_width
:
integer
:
=
32
;
g_tx_streamer_width
:
integer
:
=
32
;
g_rx_streamer_width
:
integer
:
=
32
;
-- memory initialisation file for embedded CPU
g_dpram_initf
:
string
:
=
"default_altera"
;
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
-- size the generic diag interface
g_diag_ro_size
:
integer
:
=
0
;
g_diag_rw_size
:
integer
:
=
0
g_diag_ro_size
:
integer
:
=
0
;
g_diag_rw_size
:
integer
:
=
0
);
port
(
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Clock inputs from the board
clk_board_125m_i
:
in
std_logic
;
clk_board_20m_i
:
in
std_logic
;
clk_board_125m_i
:
in
std_logic
;
clk_board_20m_i
:
in
std_logic
;
-- Aux clocks, which can be disciplined by the WR Core
clk_aux_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_ext_10m_i
:
in
std_logic
:
=
'0'
;
clk_ext_10m_i
:
in
std_logic
:
=
'0'
;
-- External PPS input (g_with_external_clock_input = TRUE)
pps_ext_i
:
in
std_logic
:
=
'0'
;
-- Reset input (active low, can be async)
areset_n_i
:
in
std_logic
;
areset_n_i
:
in
std_logic
;
-- 62.5MHz sys clock output
clk_sys_62m5_o
:
out
std_logic
;
clk_sys_62m5_o
:
out
std_logic
;
-- 125MHz ref clock output
clk_ref_125m_o
:
out
std_logic
;
-- active low reset output, synchronous to clk_sys_62m5_o
clk_ref_125m_o
:
out
std_logic
;
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o
:
out
std_logic
;
rst_ref_125m_n_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- SPI interfaces to DACs
---------------------------------------------------------------------------
dac_ref_sync_n_o
:
out
std_logic
;
dac_dmtd_sync_n_o
:
out
std_logic
;
dac_din_o
:
out
std_logic
;
...
...
@@ -111,26 +111,22 @@ entity xwrc_board_vfchd is
---------------------------------------------------------------------------
-- SFP I/O for transceiver and SFP management info from VFC-HD
---------------------------------------------------------------------------
sfp_tx_o
:
out
std_logic
;
sfp_rx_i
:
in
std_logic
;
sfp_tx_o
:
out
std_logic
;
sfp_rx_i
:
in
std_logic
;
-- HIGH if both of the following are true:
-- 1. SFP is detected (plugged in)
-- 2. The part number has been successfully read after the SFP detection
sfp_det_valid_i
:
in
std_logic
;
sfp_det_valid_i
:
in
std_logic
:
=
'0'
;
-- 16 byte vendor Part Number (PN)
-- (ASCII encoded, first character byte in bits 127 downto 120)
sfp_data_i
:
in
std_logic_vector
(
127
downto
0
);
sfp_tx_fault_i
:
in
std_logic
;
sfp_los_i
:
in
std_logic
;
sfp_data_i
:
in
std_logic_vector
(
127
downto
0
);
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_los_i
:
in
std_logic
:
=
'0'
;
---------------------------------------------------------------------------
-- I2C EEPROM
---------------------------------------------------------------------------
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
...
...
@@ -139,21 +135,18 @@ entity xwrc_board_vfchd is
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_i
:
in
std_logic
;
onewire_oen_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- External WB interface
---------------------------------------------------------------------------
wb_slave_o
:
out
t_wishbone_slave_out
;
wb_slave_i
:
in
t_wishbone_slave_in
:
=
cc_dummy_slave_in
;
---------------------------------------------------------------------------
-- WR fabric interface (when g_fabric_iface = "plain")
---------------------------------------------------------------------------
wrf_src_o
:
out
t_wrf_source_out
;
wrf_src_i
:
in
t_wrf_source_in
:
=
c_dummy_src_in
;
wrf_snk_o
:
out
t_wrf_sink_out
;
...
...
@@ -162,44 +155,71 @@ entity xwrc_board_vfchd is
---------------------------------------------------------------------------
-- WR streamers (when g_fabric_iface = "streamers")
---------------------------------------------------------------------------
wrs_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
---------------------------------------------------------------------------
-- Etherbone WB master interface (when g_fabric_iface = "etherbone")
---------------------------------------------------------------------------
wb_eth_master_o
:
out
t_wishbone_master_out
;
wb_eth_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
---------------------------------------------------------------------------
-- Generic diagnostics interface (access from WRPC via SNMP or uart console
---------------------------------------------------------------------------
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
aux_diag_o
:
out
t_generic_word_array
(
g_diag_rw_size
-1
downto
0
);
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
aux_diag_o
:
out
t_generic_word_array
(
g_diag_rw_size
-1
downto
0
);
---------------------------------------------------------------------------
-- Aux clocks control
---------------------------------------------------------------------------
tm_dac_value_o
:
out
std_logic_vector
(
23
downto
0
);
tm_dac_wr_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tm_clk_aux_lock_en_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
tm_clk_aux_locked_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
---------------------------------------------------------------------------
--
WRPC timing interface and status
--
External Tx Timestamping I/F
---------------------------------------------------------------------------
timestamps_o
:
out
t_txtsu_timestamp
;
timestamps_ack_i
:
in
std_logic
:
=
'1'
;
pps_ext_i
:
in
std_logic
:
=
'0'
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- Pause Frame Control
---------------------------------------------------------------------------
fc_tx_pause_req_i
:
in
std_logic
:
=
'0'
;
fc_tx_pause_delay_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
fc_tx_pause_ready_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- Timecode I/F
---------------------------------------------------------------------------
tm_link_up_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
led_link_o
:
out
std_logic
;
led_act_o
:
out
std_logic
);
---------------------------------------------------------------------------
-- Buttons, LEDs and PPS output
---------------------------------------------------------------------------
led_act_o
:
out
std_logic
;
led_link_o
:
out
std_logic
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
-- 1PPS output
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
-- Link ok indication
link_ok_o
:
out
std_logic
);
end
entity
xwrc_board_vfchd
;
...
...
@@ -220,8 +240,8 @@ architecture struct of xwrc_board_vfchd is
-- Reset logic
signal
rst_62m5_n
:
std_logic
;
signal
rstlogic_arst_n
:
std_logic
;
signal
rstlogic_clk_in
:
std_logic_vector
(
0
downto
0
);
signal
rstlogic_rst_out
:
std_logic_vector
(
0
downto
0
);
signal
rstlogic_clk_in
:
std_logic_vector
(
1
downto
0
);
signal
rstlogic_rst_out
:
std_logic_vector
(
1
downto
0
);
-- PLL DAC ARB
signal
dac_sync_n
:
std_logic_vector
(
1
downto
0
);
...
...
@@ -298,10 +318,11 @@ begin -- architecture struct
-- concatenation of all clocks required to have synced resets
rstlogic_clk_in
(
0
)
<=
clk_pll_62m5
;
rstlogic_clk_in
(
1
)
<=
clk_pll_125m
;
cmp_rstlogic_reset
:
gc_reset
generic
map
(
g_clocks
=>
1
,
-- 62.
5MHz
g_clocks
=>
2
,
-- 62.5MHz, 12
5MHz
g_logdelay
=>
4
,
-- 16 clock cycles
g_syncdepth
=>
3
)
-- length of sync chains
port
map
(
...
...
@@ -314,6 +335,7 @@ begin -- architecture struct
rst_62m5_n
<=
rstlogic_rst_out
(
0
);
rst_sys_62m5_n_o
<=
rst_62m5_n
;
rst_ref_125m_n_o
<=
rstlogic_rst_out
(
1
);
-----------------------------------------------------------------------------
-- SPI DAC (2-channel)
...
...
@@ -370,7 +392,7 @@ begin -- architecture struct
-- temporary, without it vuart receives but is not able to transmit
g_phys_uart
=>
TRUE
,
g_virtual_uart
=>
TRUE
,
g_aux_clks
=>
0
,
g_aux_clks
=>
g_aux_clks
,
g_ep_rxbuf_size
=>
1024
,
g_tx_runt_padding
=>
TRUE
,
g_dpram_initf
=>
g_dpram_initf
,
...
...
@@ -393,7 +415,7 @@ begin -- architecture struct
clk_sys_i
=>
clk_pll_62m5
,
clk_dmtd_i
=>
clk_pll_dmtd
,
clk_ref_i
=>
clk_pll_125m
,
clk_aux_i
=>
(
others
=>
'0'
)
,
clk_aux_i
=>
clk_aux_i
,
clk_ext_i
=>
clk_10m_ext
,
clk_ext_mul_i
=>
ext_ref_mul
,
clk_ext_mul_locked_i
=>
ext_ref_mul_locked
,
...
...
@@ -409,8 +431,6 @@ begin -- architecture struct
phy8_i
=>
phy8_to_wrc
,
phy16_o
=>
phy16_from_wrc
,
phy16_i
=>
phy16_to_wrc
,
led_act_o
=>
led_act_o
,
led_link_o
=>
led_link_o
,
scl_o
=>
eeprom_scl_o
,
scl_i
=>
eeprom_scl_i
,
sda_o
=>
eeprom_sda_o
,
...
...
@@ -420,8 +440,6 @@ begin -- architecture struct
sfp_sda_o
=>
sfp_i2c_sda_in
,
sfp_sda_i
=>
not
sfp_i2c_sda_en
,
sfp_det_i
=>
not
sfp_det_valid_i
,
-- WRPC-SW expects this active low
btn1_i
=>
'1'
,
btn2_i
=>
'1'
,
spi_sclk_o
=>
open
,
spi_ncs_o
=>
open
,
spi_mosi_o
=>
open
,
...
...
@@ -449,23 +467,27 @@ begin -- architecture struct
wrs_rx_dreq_i
=>
wrs_rx_dreq_i
,
wb_eth_master_o
=>
wb_eth_master_o
,
wb_eth_master_i
=>
wb_eth_master_i
,
timestamps_o
=>
open
,
timestamps_ack_i
=>
'1'
,
fc_tx_pause_req_i
=>
'0'
,
fc_tx_pause_delay_i
=>
(
others
=>
'0'
),
fc_tx_pause_ready_o
=>
open
,
tm_link_up_o
=>
open
,
tm_dac_value_o
=>
open
,
tm_dac_wr_o
=>
open
,
tm_clk_aux_lock_en_i
=>
(
others
=>
'0'
),
tm_clk_aux_locked_o
=>
open
,
aux_diag_i
=>
aux_diag_i
,
aux_diag_o
=>
aux_diag_o
,
tm_dac_value_o
=>
tm_dac_value_o
,
tm_dac_wr_o
=>
tm_dac_wr_o
,
tm_clk_aux_lock_en_i
=>
tm_clk_aux_lock_en_i
,
tm_clk_aux_locked_o
=>
tm_clk_aux_locked_o
,
timestamps_o
=>
timestamps_o
,
timestamps_ack_i
=>
timestamps_ack_i
,
fc_tx_pause_req_i
=>
fc_tx_pause_req_i
,
fc_tx_pause_delay_i
=>
fc_tx_pause_delay_i
,
fc_tx_pause_ready_o
=>
fc_tx_pause_ready_o
,
tm_link_up_o
=>
tm_link_up_o
,
tm_time_valid_o
=>
tm_time_valid_o
,
tm_tai_o
=>
tm_tai_o
,
tm_cycles_o
=>
tm_cycles_o
,
led_act_o
=>
led_act_o
,
led_link_o
=>
led_link_o
,
btn1_i
=>
btn1_i
,
btn2_i
=>
btn2_i
,
pps_p_o
=>
pps_p_o
,
pps_led_o
=>
pps_led_o
,
aux_diag_i
=>
aux_diag_i
,
aux_diag_o
=>
aux_diag_o
,
link_ok_o
=>
open
);
link_ok_o
=>
link_ok_o
);
end
architecture
struct
;
top/spec_ref_design/spec_wr_ref_top.vhd
View file @
b3ad9a9c
...
...
@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-20
-- Last update: 2017-0
2-22
-- Last update: 2017-0
3-08
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the SPEC.
...
...
@@ -428,8 +428,8 @@ begin -- architecture top
clk_10m_ext_ref_i
=>
clk_ext_10m
,
clk_sys_62m5_o
=>
clk_sys_62m5
,
clk_ref_125m_o
=>
clk_ref_125m
,
rst_
62m5_n_o
=>
rst_sys_62m5_n
,
rst_
125m_n_o
=>
rst_ref_125m_n
,
rst_
sys_62m5_n_o
=>
rst_sys_62m5_n
,
rst_
ref_125m_n_o
=>
rst_ref_125m_n
,
plldac_sclk_o
=>
plldac_sclk_o
,
plldac_din_o
=>
plldac_din_o
,
...
...
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