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White Rabbit core collection
Commit b3506d5f authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_endpoint: removed latches on some comb signals

parent a32d3348
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Showing with 10 additions and 3 deletions
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @ b3506d5f
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski -- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT -- Company : CERN BE-CO-HT
-- Created : 2010-11-18 -- Created : 2010-11-18
-- Last update: 2011-10-21 -- Last update: 2011-10-26
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -361,6 +361,7 @@ package body endpoint_private_pkg is ...@@ -361,6 +361,7 @@ package body endpoint_private_pkg is
else else
if(fab.sof = '1' or fab.error = '1' or fab.eof = '1' or fab.has_rx_timestamp = '1') then if(fab.sof = '1' or fab.error = '1' or fab.eof = '1' or fab.has_rx_timestamp = '1') then
-- tag = 01 -- tag = 01
dout(17) <= 'X';
dout(16) <= '1'; dout(16) <= '1';
dout(15) <= fab.sof; dout(15) <= fab.sof;
dout(14) <= fab.eof; dout(14) <= fab.eof;
...@@ -408,6 +409,7 @@ package body endpoint_private_pkg is ...@@ -408,6 +409,7 @@ package body endpoint_private_pkg is
fab.bytesel <= (not din(16)) and din(17); fab.bytesel <= (not din(16)) and din(17);
end if; end if;
else else
fab.bytesel <= 'X';
fab.dvalid <= '0'; fab.dvalid <= '0';
fab.sof <= '0'; fab.sof <= '0';
fab.eof <= '0'; fab.eof <= '0';
......
modules/wr_endpoint/ep_rx_buffer.vhd
View file @ b3506d5f
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski -- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT -- Company : CERN BE-CO-HT
-- Created : 2010-11-18 -- Created : 2010-11-18
-- Last update: 2011-10-18 -- Last update: 2011-10-26
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -84,7 +84,7 @@ architecture behavioral of ep_rx_buffer is ...@@ -84,7 +84,7 @@ architecture behavioral of ep_rx_buffer is
dout(15) <= fab.sof; dout(15) <= fab.sof;
dout(14) <= fab.eof; dout(14) <= fab.eof;
dout(13) <= fab.error; dout(13) <= fab.error;
dout(11 downto 0) <= (others => 'X'); dout(12 downto 0) <= (others => 'X');
dout_valid <= '1'; dout_valid <= '1';
elsif(fab.dvalid = '1') then elsif(fab.dvalid = '1') then
...@@ -114,6 +114,7 @@ architecture behavioral of ep_rx_buffer is ...@@ -114,6 +114,7 @@ architecture behavioral of ep_rx_buffer is
fab.data <= din(15 downto 0); fab.data <= din(15 downto 0);
if(din_valid = '1') then if(din_valid = '1') then
if(din(17 downto 16) = "10") then -- some fancy encoding is necessary here if(din(17 downto 16) = "10") then -- some fancy encoding is necessary here
case cur_addr(1 downto 0) is case cur_addr(1 downto 0) is
when c_WRF_DATA => when c_WRF_DATA =>
...@@ -132,11 +133,15 @@ architecture behavioral of ep_rx_buffer is ...@@ -132,11 +133,15 @@ architecture behavioral of ep_rx_buffer is
fab.eof <= din(14) and din(17) and din(16); fab.eof <= din(14) and din(17) and din(16);
fab.error <= din(13) and din(17) and din(16); fab.error <= din(13) and din(17) and din(16);
fab.bytesel <= not din(17) and din(16); fab.bytesel <= not din(17) and din(16);
else else
fab.bytesel <= 'X';
fab.addr <= (others => 'X');
fab.dvalid <= '0'; fab.dvalid <= '0';
fab.sof <= '0'; fab.sof <= '0';
fab.eof <= '0'; fab.eof <= '0';
fab.error <= '0'; fab.error <= '0';
fab.addr <= (others => 'X');
fab.data <= (others => 'X'); fab.data <= (others => 'X');
end if; end if;
end f_unpack_rbuf_contents; end f_unpack_rbuf_contents;
......
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