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W
White Rabbit core collection
Commit ab452357 authored by Tristan Gingold's avatar Tristan Gingold
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spec_wr_ref_top: re-add firmware file

parent 77d87dfb
Pipeline #3433 failed with stage
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    modules/wrc_core/wrc_urv_wrapper.vhd
    View file @ ab452357
    ......@@ -173,7 +173,7 @@ begin
    g_WITH_BYTE_ENABLE => TRUE,
    g_ADDR_CONFLICT_RESOLUTION => "dont_care",
    g_INIT_FILE => g_IRAM_INIT,
    g_FAIL_IF_FILE_NOT_FOUND => FALSE,
    g_FAIL_IF_FILE_NOT_FOUND => TRUE,
    g_DUAL_CLOCK => FALSE)
    port map (
    rst_n_i => rst_n_i,
    ......
    top/spec_ref_design/spec_wr_ref_top.vhd
    View file @ ab452357
    ......@@ -7,7 +7,7 @@
    -- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
    -- Company : CERN (BE-CO-HT)
    -- Created : 2017-02-20
    -- Last update: 2021-02-25
    -- Last update: 2022-03-29
    -- Standard : VHDL'93
    -------------------------------------------------------------------------------
    -- Description: Top-level file for the WRPC reference design on the SPEC.
    ......@@ -56,14 +56,13 @@ use work.wishbone_pkg.all;
    use work.gn4124_core_pkg.all;
    use work.wr_board_pkg.all;
    use work.wr_spec_pkg.all;
    use work.synthesis_descriptor.all;
    library unisim;
    use unisim.vcomponents.all;
    entity spec_wr_ref_top is
    generic (
    g_DPRAM_INITF : string := "";
    g_DPRAM_INITF : string := "../../bin/wrpc/wrc_phy8.bram";
    -- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
    -- changed to non-zero in the instantiation of the top level DUT in the testbench.
    -- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
    ......
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