[board/svec] trivial bugfix: was missing std_logic declaration of input port

aa77538e · Maciej Lipinski · 6609da1c · aa77538e
Commit aa77538e authored Feb 23, 2017 by Maciej Lipinski
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wrc_board_svec.vhd board/svec/wrc_board_svec.vhd +1 -1

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--- a/board/svec/wrc_board_svec.vhd
+++ b/board/svec/wrc_board_svec.vhd
@@ -243,7 +243,7 @@ entity wrc_board_svec is
    -- WRPC timing interface and status
    ---------------------------------------------------------------------------
-    pps_ext_i       : in                                                     := '0';
+    pps_ext_i       : in  std_logic                                         := '0';
    pps_p_o         : out std_logic;
    pps_led_o       : out std_logic;
    tm_time_valid_o : out std_logic;