Skip to content

W
White Rabbit core collection
Commit a47d2c65 authored by CI's avatar CI
Browse files
Options

Testbench wr_endpoint/full_tb now uses Riviera-Pro

parent 3408c881
Pipeline #3519 canceled with stage
    Expand all Hide whitespace changes
    Inline Side-by-side
    Showing with 172 additions and 11 deletions
    testbench/Makefile
    View file @ a47d2c65
    ......@@ -9,10 +9,11 @@
    #TB_DIRS+=wr_streamers/streamers-only-fixed-latency
    #TB_DIRS+=wr_streamers/streamers-only_multiword-transfer
    #TB_DIRS+=xwrf_mux
    TB_DIRS+=wr_endpoint/full_tb
    #TB_DIRS+=wr_streamers/streamers-on-spec-trigger-distribution
    TB_DIRS+=wr_streamers/streamers_multi_test
    #TB_DIRS+=xwrf_mux
    #TB_DIRS+=wr_streamers/streamers_multi_test
    test_results_xml=test_results.xml
    ......
    testbench/wr_endpoint/full_tb/Manifest.py
    View file @ a47d2c65
    ......@@ -3,19 +3,21 @@ action = "simulation"
    syn_device = "xc6slx45t"
    syn_grade = "-3"
    syn_package = "fgg484"
    sim_tool = "modelsim"
    #sim_tool = "modelsim"
    sim_tool = "riviera"
    top_module = "main"
    files = "main.sv"
    fetchto = "../../../ip_cores"
    vcom_opt="-relax -packagevhdlsv"
    vlog_opt="+incdir+../../../sim +incdir+../../../sim/fabric_emu"
    include_dirs = [ "../../../sim" ]
    include_dirs = [ "../../../sim", "../../../sim/fabric_emu" ]
    modules ={"git" : [ "git@ohwr.org:hdl-core-lib/general-cores.git" ],
    "local" : ["../../../modules/wr_endpoint",
    "../../../modules/timing",
    "../../../modules/fabric",
    "../../../modules/wr_tbi_phy",
    "../old_ep",
    "../../../platform/xilinx/wr_gtp_phy" ] };
    modules ={"git" : ["git@ohwr.org:hdl-core-lib/general-cores.git" ],
    "local" : ["../../../modules/wr_endpoint",
    "../../../modules/timing",
    "../../../modules/fabric",
    "../../../modules/wr_tbi_phy",
    "../old_ep",
    "../../../platform/xilinx/wr_gtp_phy" ] };
    testbench/wr_endpoint/full_tb/run_ci_riv.do 0 → 100644
    View file @ a47d2c65
    null make -f Makefile
    vsim -L unisim -t 10fs work.main +access +r
    set StdArithNoWarnings 1
    set NumericStdNoWarnings 1
    do wave.do
    radix -hexadecimal
    run 250us
    wave zoomfull
    radix -hexadecimal
    testbench/wr_endpoint/full_tb/wave_ci.do 0 → 100644
    View file @ a47d2c65
    This diff is collapsed.
    Markdown is supported
    0% or
    You are about to add 0 people to the discussion. Proceed with caution.
    Finish editing this message first!
    Please register or to comment