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White Rabbit core collection
Commit a0b3fb48 authored by Peter Jansweijer's avatar Peter Jansweijer
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gen_10mhz avoid lut in reset path and add multicycle constraint due to tight 500 mhz timing.

parent 3231de61
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    top/spec7_ref_design/gen_10mhz.vhd
    View file @ a0b3fb48
    ......@@ -58,9 +58,9 @@ end gen_10mhz;
    architecture rtl of gen_10mhz is
    signal rst_synced : std_logic := '0';
    signal pps_synced : std_logic := '0';
    signal pps_delayed : std_logic := '0';
    signal rst_n_synced : std_logic := '0';
    signal pps_synced : std_logic := '0';
    signal pps_delayed : std_logic := '0';
    begin -- rtl
    process (clk_500m_i)
    ......@@ -69,16 +69,16 @@ begin -- rtl
    -- clk_500m is locked to the reference clock domain
    -- although clocks are phase locked, first synchronize pps_i
    -- and rst_n_i to 500 MHz to ease timing closure.
    rst_synced <= not rst_n_i;
    pps_synced <= pps_i;
    pps_delayed <= pps_synced;
    rst_n_synced <= rst_n_i;
    pps_synced <= pps_i;
    pps_delayed <= pps_synced;
    end if;
    end process;
    pr_10mhz_gen : process (clk_500m_i, rst_synced)
    pr_10mhz_gen : process (clk_500m_i, rst_n_synced)
    variable cntr: integer range 0 to 99;
    begin -- process pr_10mhz_gen
    if rst_synced = '1' then
    if rst_n_synced = '0' then
    cntr := 0;
    elsif rising_edge(clk_500m_i) then
    if ((pps_synced = '1' and pps_delayed = '0') or cntr = 49) then
    ......
    top/spec7_ref_design/spec7_wr_ref_top.xdc
    View file @ a0b3fb48
    ......@@ -49,12 +49,13 @@ set_clock_groups -asynchronous \
    -group be_clk_ext_10m \
    -group clk_ext_mul
    # TXOUTCLK = 16 ns = 8 clock periods of clk_500m which has 2 ns period
    # clk_ref_62m5_div2 = 16 ns = 8 clock periods of clk_500m which has 2 ns period
    # Setup requirement at edge 8, hold requirement at edge 7
    # See also:
    # https://www.xilinx.com/video/hardware/timing-exception-multicycle-path-constraints.html
    set_multicycle_path 8 -setup -from [get_clocks clk_ref_62m5_div2] -to [get_clocks "*clk_500m*"]
    set_multicycle_path 7 -hold -from [get_clocks clk_ref_62m5_div2] -to [get_clocks "*clk_500m*"]
    # See: "Multicycle Path and Positive phase shift" (due to the clk_ref_62m5_div2 to clk_500 delay through MMCME2_ADV)
    set_multicycle_path 2 -setup -from [get_clocks clk_ref_62m5_div2] -to [get_clocks "*clk_500m*"]
    set_multicycle_path 1 -hold -from [get_clocks clk_ref_62m5_div2] -to [get_clocks "*clk_500m*"]
    # Set BMM_INFO_DESIGN property to avoid ERROR during "Write Bitstream"
    set_property BMM_INFO_DESIGN spec7_wr_ref_top.bmm [current_design]
    ......
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